JP3477117B2 - Semiconductor integrated circuit device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device having a plurality of internal circuits having different power supply voltages, and more specifically, an active element for transmitting and receiving a signal between such internal circuits is electrostatically discharged. Related to technology to protect from destruction by the like. As a semiconductor integrated circuit device, a multifunctional LS
I (large-scale integrated circuit device), digital / analog mixed LSI, multi-power supply digital LSI, and the like can be mentioned. In such a large-scale integrated circuit, a gate array, a custom LSI, an ASIC (an IC for a specific application) ), Etc., a wide variety of manufacturing items, generalization of the manufacturing process, automation of design, etc. are being promoted on the premise of standardization of the basic cell structure and regular arrangement. The present invention is particularly suitable for such a large scale integrated circuit device,
In addition to protection from electrostatic breakdown, suitability for automatic circuit design etc. is also considered.

[0002]

BACKGROUND ART FIG. 7 shows a typical structure of a semiconductor integrated circuit device in which a plurality of internal circuits having different power supply lines are built in one chip. FIG. 7A is a schematic layout diagram of the entire chip. (B) is a circuit diagram of a main part. FIG. 8 shows a portion for transmitting and receiving a signal between the internal circuits at an element level. (A) is a detailed circuit diagram, (b) is a layout diagram of a semiconductor region, (c) is a pattern of gates and power supply lines. A layout diagram of the formed device, (d) a layout diagram of the signal wiring pattern formed, and (e) are vertical cross-sectional perspective views of a semiconductor region and a gate, which are basic cells for active elements, that is, a basic unit. . Note that in FIG. 8D, the signal wiring is shown by a thick solid line, connection points such as contact holes where the signal wiring reaches the semiconductor layer are shown by black circles, and the signal wiring reaches the layer of the power supply line but does not reach the semiconductor layer below it. Connection points that do not reach are indicated by small squares. The same applies to FIGS. 1 (b), 2 (b), 4 (b), and 5 (b) described later.

In a large-scale integrated circuit device, an external connection terminal 2 such as a bonding pad, an external signal input / output circuit, and an internal circuit are arranged in this order from the peripheral portion to the central portion. 7 (a)), internal circuit 4A
And the internal circuit 4B have different power supply voltages,
The left external signal input / output circuit 3A located near the left internal circuit 4A and some external connection terminals 2 on the left side are arranged while being divided into left and right blocks.
Is exclusively connected to the internal circuit 4A to perform signal relay with the outside regarding the internal circuit 4A and reception of electric power. Further, the remaining external signal input / output circuit 3B and the external connection terminal 2 are exclusively connected to the internal circuit 4B so as to perform signal relay with respect to the internal circuit 4B to the outside and reception of electric power.

As an example of a combination of power supply voltages supplied to these internal circuits 4A and 4B, 12V vs. 5V and 5V
There are various types such as vs. 3V, 3V vs. 2V, etc., but the circuit (the one on the left side in the figure) to which a relatively high power supply voltage is supplied, the element thereof, etc., are marked with an "A" at the end. On the other hand, the circuit to which a relatively low power supply voltage is supplied (the one on the right side in the figure), its element, and the like are indicated by adding "B" to the end of the reference numeral. Note that FIG. 9 and FIG.
The same applies to FIG.

In such a case, at least a pair of power supply lines, for example, a power supply line 8A for applying a positive voltage and a power supply line 9A for grounding are required in order to receive power supply from the outside to the internal circuit 4A. Many external connection terminals 2
At least one of them is a high power supply terminal 5A, and one power supply line 8A is connected to this, and at least one of the remaining external connection terminals 2 is a grounding terminal 6A.
Then, the other power supply line 9A is connected to this. Each of the power supply lines 8A and 9A extends as an unillustrated annular wiring or dendritic / striped wiring (see FIG. 7A),
It is connected to the input protection circuit 3AA in the external signal input / output circuit 3A, reaches the internal circuit 4A via the input protection circuit 3AA, and is also connected to many internal elements 11A, 12A, 13A there (see FIG. 7B). .

The input protection circuit 3AA (see FIG. 7B) is connected to the connection line between the input / output terminal 7A of the external connection terminal 2 which is assigned to the input to the internal element 11A and the internal element 11A. A rectifying element such as a pair of or a pair of diodes or transistors connected to the connection line and the power supply lines 8A and 9A is provided, and surge noise such as static electricity is applied to the input / output terminal 7A. At such times, the surge noise is released to the high power supply terminal 5A and the grounding terminal 6A to protect the internal element 11A.

Further, although the detailed description which will be repeated is omitted, the power supply line 8 is also provided on the internal circuit 4B side (see FIG. 7).
A power supply line 8B for applying a positive voltage lower than A reaches the internal circuit 4B from the low power supply terminal 5B through the external signal input / output circuit 3B, and is paired with the power supply line 9B for grounding.
From the grounding terminal 6B to the internal circuit 4B also via the external signal input / output circuit 3B, and these are connected to the input protection circuit 3BB in the external signal input / output circuit 3B and internal elements 11B, 12B, 13B in the internal circuit 4B. Connected to
A connection line from the input / output terminal 7B to the internal element 11B is connected to the input protection circuit 3BB. All or at least the power supply line 8A and the power supply line 8B are connected indirectly via a protection circuit or the like, but are directly or short-circuited in the semiconductor integrated circuit device 1 Internal circuits 4A, 4B
Are a plurality of internal circuits having different power supply lines.

Further (see FIG. 7B), the internal circuit 4
When a signal is transmitted and received between A and 4B as well, an inter-circuit signal wiring 12 that connects the output element 12A of the internal circuit 4A and the input element 12B of the internal circuit 4B and the output element 1 of the internal circuit 4B are connected.
The inter-circuit signal wirings 13 that connect 3B and the input element 13A of the internal circuit 4A are also provided between the internal circuits 4A and 4B by the number required for transmitting and receiving signals.

The output element 12A is composed of one or a plurality of active elements such as transistors. For example, in the case of a CMOS inverter (see FIG. 8A), the source is connected to the power supply line 8A and the drain is an inter-circuit signal wiring. PMOS transistor 12AP having a gate connected to the internal signal wiring SA in the internal circuit 4A, a source connected to the power supply line 9A, a drain connected to the inter-circuit signal wiring 12, and a gate connected to the internal circuit 4A. An nMOS transistor 12AN connected to the signal wiring SA. Similarly, the source of the input element 12B is the power line 8 as well.
A pair of pMOS transistors 12 connected to B and 9B
The BP and the nMOS transistor 12BN are provided, the gates of which are connected to the inter-circuit signal wiring 12 and the drains thereof are connected to the internal signal wiring SB of the internal circuit 4B.

The input element 13A and the output element 13B have the same signal transmission / reception directions but the same transistor pair 13
AP, 13AN and transistor pair 13BP, 13BN
The drain or the gate is connected to the inter-circuit signal wiring 13. Such a transistor 12AP, 1
2AN, 12BP, 12BN, 13AP, 13AN, 1
Each of 3BP and 13BN is a first active element connected to the inter-circuit signal wiring.

In order to fabricate the semiconductor integrated circuit device 1 having such a circuit on a silicon wafer or the like (see FIG. 8).
(See (b) to (e)) Normally, fine basic cells for active elements are repeatedly arranged vertically and horizontally at equal pitches in the regions of the internal circuits 4A and 4B assigned to each chip. For example, for a CMOS basic cell (see FIG. 8B), nMO
The nMOS cells are composed of cells for S and cells for pMOS, and the cells for nMOS are scattered in a p-type substrate (p-Sub) like islands, and each has an n-type semiconductor region, a gate oxide film region, and an n-type semiconductor region. Is sufficient, but as shown in the figure, the n-type semiconductor region, the gate oxide film region, the n-type semiconductor region, the gate oxide film region, and the n-type semiconductor region are formed in advance, and the central n-type semiconductor region is shared. 2 nM by doing
In many cases, it is possible to create an OS transistor.

Further, the pMOS cells are scattered in the n-type well region (n-Well) like islands, and n
The n-type semiconductor region of the nMOS cell is replaced with the p-type semiconductor region so as to have a one-to-one correspondence with the MOS cell. Then, an isolated pattern of a metal or the like to be a gate and a lead-out portion thereof is individually formed on the gate oxide film region of each basic cell (see FIG. 8E), and an appropriate insulating layer or the like is interposed. From above, a power supply line 8A is formed on the series of pMOS basic cells of the internal circuit 4A by patterning a conductor layer such as a metal layer, and the series of nMO of the internal circuit 4A is formed.
A power supply line 9A is formed on the S basic cell, and a power supply line 8 is formed on the series of pMOS basic cells of the internal circuit 4B.
B is formed, and the power supply line 9B is formed on the series of basic cells for nMOS of the internal circuit 4B (see FIG. 8C).

Thus, the basic cells for active elements are regularly arranged in the same structure or the same structure until the middle of the pre-process of the semiconductor process, and a highly versatile wafer is completed. Then, when the allocation of the active elements is specifically determined based on the application, for example (see FIG. 8C), the first active elements 12AP and 12AN are allocated to the adjacent basic cells in the internal circuit 4A and the internal cells are internally allocated. In the circuit 4B as well, when the first active elements 12BP and 12BN are assigned to the adjacent basic cells, the necessary wiring associated therewith is almost uniquely determined as follows.

That is (see FIG. 8 (d)), in the corresponding basic cell, a contact hole such as a VIA hole (see a black circle in the figure) is formed at the center of the cell, so that the first active elements 12AP, 12AN, 12BP are formed. , 12BN are connected to the power supply lines 8A, 9A, 8B, 9B, respectively, and in the internal circuit 4A, the internal signal wiring SA is connected to the gate of the first active element 12AP and the gates of the first active elements 12AP, 12AN. They are also connected to each other, and one end of the inter-circuit signal wiring 12 is branched and connected to the drains of the first active elements 12AP and 12AN at the corners of the basic cells.

The other end of the inter-circuit signal wiring 12 extends into the internal circuit 4B and is connected to the gate of the first active element 12BP. In the internal circuit 4B, the first active element 12BP,
The gates of 12BN are connected to each other, and one end of the internal signal wiring SB is branched to be connected to the drains of the first active elements 12BP and 12BN at the corners of the basic cells, respectively, and they are merged to each other in the internal circuit 4B. It is connected to internal elements. In this way, the base semiconductor part can be generalized and shared, and various circuits can be embodied by changing the allocation of the active elements and the wiring formed in the upper layer, etc., which are determined thereafter. It is possible to quickly and accurately respond to the application of.

[0016]

2. Description of the Related Art Conventionally, such a semiconductor integrated circuit device 1
Then, as a countermeasure against electrostatic breakdown, in addition to the input protection circuits 3AA and 3BB described above, an inter-block protection circuit has been provided between both blocks of the internal circuits 4A and 4B. The inter-block protection circuit is composed of a resistor, a rectifying element, a Zener diode or a transistor having a similar function, and is also connected to power supply lines 8A, 8B, 9A and 9B having different power supply voltages to be supplied. When the breakdown voltage of the internal element becomes weaker due to the miniaturization of the internal circuit, etc., the input protection circuit, which is smaller in number than the internal element, is enlarged, or the inter-block protection circuit is increased or further enlarged to prevent electrostatic discharge. It had enhanced protection from destruction.

[0017]

However, since miniaturization and speeding up of internal circuits continue to progress, sufficient protection can no longer be obtained simply by repeating the conventional method of increasing the number of such protection circuits. Absent. Due to the miniaturization of the device, etc., the proof stress of the device itself such as the gate breakdown voltage will decrease.
This is because the capacitance that is incidental or parasitic on the elements, wirings, etc. is reduced, while the inductance is increased, so that the ability to propagate / diffuse the surge noise and reduce it is reduced.

For this reason, for example, surge noise rides on the internal circuit 4B, which causes the internal circuit 4A and the internal circuit 4
When the potential difference from B expands, the potential of the input element 12B and the output element 13B to which the potential of the internal circuit 4A is transmitted via the inter-circuit signal wirings 12 and 13 and its vicinity is increased in the internal circuit 4B. It becomes a suddenly changing local (Fig. 9
(Refer to the chain double-dashed line in (a)) In such a case, in the conventional case, the potential difference between the internal circuits 4A and 4B is alleviated by the inter-block protection circuit 4c while the input element 12B and the like are still enduring. Although the electrostatic breakdown was avoided, in the situation that the relaxation rate was decreased in addition to the decrease in withstand voltage (see the chain double-dashed line in FIG. 9B), the electrostatic breakdown was avoided. Is difficult

Further, under such a situation, for example (see FIG. 9C), when the input / output terminal 7B is subjected to surge noise, the input protection circuit 3BB for protecting the internal element 11B is present. , For another internal element 12B,
Sometimes it backfires. Surge noise is input protection circuit 3
It is released to the power supply lines 8B and 9B via BB, and then released from the low power supply terminal 5B and the grounding terminal 6B to the outside and also propagates and diffuses to the entire internal circuit 4B. 9 (c), such as the alternate long and two short dashes line), the time to reach the first active element 12BP via the power supply line 8B,
The difference between the time taken to reach the first active element 12BN through the power supply line 9B cannot be ignored, and it and the inter-circuit signal wiring 1
This is because it is considered that the element that is intensively and locally affected by the potential difference from the element 2 is likely to be destroyed.

Therefore, it is a technical subject to devise a new protection circuit based on these findings and predictions. However, as the degree of integration and circuit scale increase, the difficulty of designing continues to increase. Therefore, when introducing a new protection circuit, it becomes difficult to apply automatic design when embodying the protection circuit. It is also important to take further measures so that commonality and versatility of semiconductor processes are not impaired.

The present invention has been made in order to solve such a problem, and an object thereof is to realize a semiconductor integrated circuit device which is resistant to electrostatic breakdown and is suitable for automatic design and the like.

[0022]

With respect to the first to ninth solving means invented in order to solve the above problems,
The configuration and action and effect will be described below.

[First Solving Means] The semiconductor integrated circuit device of the first solving means (as described in claim 1 at the beginning of the application) is (for positive voltage / negative voltage / high voltage / low voltage). Multiple internal circuits with different power lines (for grounding, grounding, etc.),
In a semiconductor integrated circuit device provided with (in a single chip) an inter-circuit signal wiring provided over these (at least any one of a pair of) internal circuits (for transmitting / receiving a signal between those internal circuits) An arrangement in which the inter-circuit signal wiring is sandwiched (directly or indirectly) or surrounded in the vicinity of the first active element (for signal input / reception or for signal transmission / transmission) to which the circuit signal wiring is connected. In this state, other active elements (that is, second, third, which will be described later) having the same structure as or similar to that of the internal circuit connected to the power supply line of the corresponding internal circuit and separated from the signal wiring other than the inter-circuit signal wiring. , 4th
Any of the active elements or protective elements that are connected to the power supply line of the relevant internal circuit but are not connected to the signal wiring in the relevant internal circuit (repeating the same type or mixing different types) ) It is said that a plurality is provided.

In the semiconductor integrated circuit device of the first solving means, the other newly introduced active element is connected to the signal wiring in the internal circuit in a normal state without surge noise. Since it is not present, it does not prevent the proper operation of the first active element and other internal elements.
On the other hand, when the surge noise propagates to the power supply line by riding on the external connection terminal and the time until it reaches the first active element varies among the power supply lines, the power supply line with the earlier noise arrival time Part of the surge noise is immediately diverted to the slower power supply line through the other active element. This is also performed at a plurality of places such as both sides and the periphery of the first active element.

As a result, in the first active element and its vicinity, potential fluctuations due to surge noise are dispersed even if locally, so that the gradient of the potential distribution is relaxed and its peak is suppressed to a low level. Moreover, it is possible to disperse and alleviate as uniformly as possible, with the feeling of balancing the surrounding points at multiple points. Also, regarding the portion that shares the voltage difference with the potential of the signal wiring between circuits, not only the portion connected to the earlier power supply line in the first active element, but also the portion connected to the later power supply line is promptly connected. Since the influence of the inter-circuit signal wiring is also dispersed due to the additional dispersion, the peak of the potential difference can be suppressed from this point as well.

Further, since the other active elements newly introduced as the protective element have the same structure and the same structure as the first active element, the basic cells arranged and arranged in the periphery of the first active element are appropriately selected. In addition to selecting the ones and connecting them to a nearby power supply line, etc., they are embodied in the same procedure as the internal elements such as the first active element, so they are compatible with automatic design and have commonality in semiconductor processes. Versatility is maintained as before. Therefore, according to the present invention, it is possible to realize a semiconductor integrated circuit device that is resistant to electrostatic damage and is suitable for automatic design and the like.

[Second Solving Means] The semiconductor integrated circuit device of the second solving means (as described in claim 2 at the beginning of the application) is (for positive voltage / negative voltage / high voltage / low voltage). Multiple internal circuits with different power lines (for grounding, grounding, etc.),
In a semiconductor integrated circuit device provided with (in a single chip) an inter-circuit signal wiring provided over these (at least any one of a pair of) internal circuits (for transmitting / receiving a signal between those internal circuits) , In the vicinity of the first active element (for signal input / reception or for signal transmission / transmission) to which the inter-circuit signal wiring is connected, having the same structure as or similar to that of the first active element A second active element connected to the power supply line and separated from the inter-circuit signal wiring and the other signal wiring (that is, for protection, which is not directly connected to any signal wiring driven by an active element other than itself) It is provided.

In the semiconductor integrated circuit device of the second solving means, the newly introduced second active element is
Unlike the other active elements described above, since it is not connected to the signal wiring in the internal circuit or the signal wiring between circuits, it does not interfere with the proper operation of the first active element or the like in the normal state. In an abnormal state where the arrival time of noise varies between power supply lines, a part of the noise is immediately diverted from the earlier power supply line to the later power supply line. This allows
In the vicinity, the potential fluctuation due to surge noise is dispersed and the peak is suppressed to a low level, and the part that shares the influence of the inter-circuit signal wiring is also distributed to the connection part with each power supply line to further reduce the potential difference. The peak will be kept low.

A second protective element is newly introduced.
The active element, like the other active elements described above, is embodied in the same procedure as the internal element such as the first active element. Moreover, it can be installed regardless of whether the power supply voltage supplied to the relevant internal circuit is higher or lower than the power supply voltage supplied to other internal circuits existing ahead of the inter-circuit signal wiring, so that it can be installed easily and the applicable range is also increased. wide. Therefore, according to the present invention, it is possible to realize a semiconductor integrated circuit device that is resistant to electrostatic damage and is suitable for automatic design and the like.

[Third Solving Means] A semiconductor integrated circuit device of a third solving means (as described in claim 3 at the beginning of the application) is a semiconductor integrated circuit device of the above second solving means. , In the vicinity of the first active element, which has the same structure as or a structure similar to that of the first active element and is connected to the power supply line of the corresponding internal circuit and the inter-circuit signal wiring and separated from other signal wiring (that is, other than its own). A third active element (for protection) which is not directly connected to any signal wiring except the inter-circuit signal wiring among the signal wirings driven by the active element is also provided.

In the semiconductor integrated circuit device of the third means as described above, the third active element is in a normal state in consideration of the level of the power supply voltage even if it is connected to the inter-circuit signal wiring. It is introduced only where there is no possibility of interfering with signal transmission, and the second active element is provided where there is a possibility of that. With respect to the surge noise as described above, in addition to the above-mentioned protection by the second active element, the influence of the inter-circuit signal wiring is also influenced by the third active element. However, since it is more positively dispersed, the peak of the potential difference can be further suppressed. Further, the third active element newly introduced as a protection element is also embodied in the same procedure as the above-mentioned first and second active elements. Therefore, according to the present invention, it is possible to realize a semiconductor integrated circuit device that is more resistant to electrostatic breakdown and is suitable for automatic design and the like.

[Fourth Solving Means] The semiconductor integrated circuit device of the fourth solving means (as described in claim 4 at the beginning of the application) is the semiconductor integrated circuit device of the third solving means. , A plurality of (at least) any one of the plurality of internal circuits is provided with a plurality of the inter-circuit signal wirings having different transmission and reception directions, and one of the pair of internal circuits (that is, a relative circuit). The second active element and the third active element are provided near the first active element on the receiving side of the inter-circuit signal wiring (that is, for signal input / reception) in the internal circuit to which a relatively low power supply voltage is supplied. An active element is provided, and the other side of the pair of internal circuits (that is, the internal circuit to which a relatively high power supply voltage is supplied) receives the inter-circuit signal wiring (that is, for signal input / reception). Near the first active element , The or in place of the second active element is omitted it (i.e. the second active element is not provided) and the third active element (preferably a plurality) is provided, is that.

In the semiconductor integrated circuit device of the fourth solving means as described above, the voltage of the inter-circuit signal wiring becomes higher than the voltage of the power supply line of the corresponding portion depending on the signal value of the inter-circuit signal wiring. For example, there is a restriction in connecting active elements to both the inter-circuit signal wiring and the power supply line in order to obtain (such as inter-circuit signal in the internal circuit to which relatively low power supply voltage is supplied. The second side and the third active element are appropriately combined and provided on the receiving side of the wiring, that is, where the input element is typical. On the other hand, there is no such restriction and it is weak against the influence of the inter-circuit signal wiring. However, at least one third active element is provided at such a location (where the receiving side of the inter-circuit signal wiring in the internal circuit to which a relatively high power supply voltage is supplied, that is, an input element is typical). Rubeku are many provided.

As a result, in a place where the influence of the inter-circuit signal wiring is weak, the protection by the third active element that positively disperses the influence of the inter-circuit signal wiring is preferentially applied. The peak will be suppressed even lower. Therefore, according to the present invention, it is possible to realize a semiconductor integrated circuit device that is stronger against electrostatic breakdown and is suitable for automatic design and the like.

[Fifth Solving Means] A semiconductor integrated circuit device according to the fifth solving means (as described in claim 5 at the beginning of application) is (for positive voltage / negative voltage / high voltage / low voltage). Multiple internal circuits with different power lines (for grounding, grounding, etc.),
In a semiconductor integrated circuit device provided with (in a single chip) an inter-circuit signal wiring provided over these (at least any one of a pair of) internal circuits (for transmitting / receiving a signal between those internal circuits) , A static part in the vicinity of the connection part of the inter-circuit signal wiring (that is, a part where the electrical state does not dynamically change in a normal operating state such as a place where no direct connection is made to any signal wiring) The inter-circuit auxiliary wiring connected (preferably so as to run in parallel with the inter-circuit signal wiring) is provided.

In the semiconductor integrated circuit device of the fifth solving means as described above, the inter-circuit auxiliary wiring is newly introduced. However, in this, the electrical state dynamically changes in the normal operating state. Since it is not connected to such a place, it does not interfere with the proper operation of the first active element and other internal elements in a normal state where there is no surge noise or the like. On the other hand, surge noise travels on one of the external connection terminals and is transmitted to only one internal circuit, which widens the potential difference between the other internal circuit and the other internal circuit, and is connected by the inter-circuit signal wiring. When the potential at the first active element in one of the internal circuits changes suddenly locally, the presence of the inter-circuit auxiliary wiring causes a similar potential change to the point near the first active element. Is triggered. When this potential change is also transmitted to the first active element, the potential of the entire first active element also moves to the same side as the sudden change potential of the inter-circuit signal wiring connection portion to some extent. The potential difference between the portion connected to the inter-signal wiring and the portion not connected thereto is offset by that amount.

As a result, the local potential fluctuation generated at the first active element due to the inter-circuit signal wiring is also caused by another similar local fluctuation caused in the vicinity thereof by the inter-circuit auxiliary wiring. Since the peak of the potential difference generated in the first active element is suppressed to a low level because it is immediately followed by a large potential change, the possibility that the first active element will escape electrostatic breakdown increases. Further, the newly introduced inter-circuit auxiliary wiring, connection to a static portion, and the like can be realized by adding and changing wiring patterns, and it is not necessary to change the structure of the basic cell or other semiconductor layers. Therefore, according to the present invention, it is possible to realize a semiconductor integrated circuit device that is resistant to electrostatic damage and is suitable for automatic design and the like.

[Sixth Solving Means] The semiconductor integrated circuit device of the sixth solving means (as described in claim 6 at the beginning of the application) is the semiconductor integrated circuit device of the fifth solving means. , Of the first active elements to which the inter-circuit signal wiring is connected to the static points (where some of the inter-circuit auxiliary wirings are connected) on the sending side (that is, for signal output / transmission) In the active element, a partial region connected to the power supply line of the corresponding internal circuit, and a part of the first active element having the same structure as or the same structure as the receiving side (that is, for signal input / reception) Provided near it (apart from the connection to the power supply line), separated from the signal wiring other than the inter-circuit auxiliary wiring (that is, not directly connected to any signal wiring driven by an active element other than itself) With a fourth active element (for protection) Who is included, is that.

In the semiconductor integrated circuit device of the sixth means as described above, the fourth active element is in a normal state in consideration of the level of the power supply voltage even if it is connected to the inter-circuit auxiliary wiring. It is introduced only in the place where short circuit of different power source does not occur, but when the fourth active element is provided, the
The local potential fluctuation generated in the active element is not only followed by the similar potential fluctuation due to the inter-circuit auxiliary wiring, but is actively released through the fourth active element and the inter-circuit auxiliary wiring.

As a result, the influence of the inter-circuit signal wiring generated on the relatively weak receiving side is dispersed to the relatively strong transmitting side, so that the first active element may escape electrostatic breakdown. Will increase further. Further, the fourth active element newly introduced as a protection element is also embodied in the same procedure as the above-mentioned first to third active elements. Therefore, according to the present invention, it is possible to realize a semiconductor integrated circuit device that is more resistant to electrostatic breakdown and is suitable for automatic design and the like.

[Seventh Solving Means] The semiconductor integrated circuit device of the seventh solving means (as described in claim 7 at the beginning of the application) is the semiconductor integrated circuit device of the sixth solving means. Instead of the partial area, the inter-circuit auxiliary wiring is connected to a neighboring area that overlaps or is close to the partial area in a corresponding power supply line connected thereto.

In the semiconductor integrated circuit device of the seventh solving means as described above, since the connection points of the inter-circuit auxiliary wiring are close, they are moved to another place where they are functionally equivalent. This expands the range of choices when designing wiring,
Since the restrictions are relaxed, the design becomes easier accordingly. Therefore, according to the present invention, it is possible to realize a semiconductor integrated circuit device that is more resistant to electrostatic breakdown and is more suitable for automatic design and the like.

[Eighth Solving Means] The semiconductor integrated circuit device of the eighth solving means (as described in claim 8 at the beginning of the application) is the semiconductor integrated circuit device of the sixth and seventh solving means. Of the plurality of internal circuits (at least)
For any one pair, a plurality of inter-circuit signal wirings having different transmission and reception directions are provided, and one circuit of the pair of internal circuits (that is, an internal circuit to which a relatively low power supply voltage is supplied is supplied. In the vicinity of the first active element on the receiving side of the inter-circuit signal wiring (that is, for signal input / reception) in (4), the fourth active element has the same or similar structure to that of the fourth active element. Connected to the power supply line of the internal circuit and separated from the inter-circuit signal wiring and other signal wiring and the inter-circuit auxiliary wiring (that is, not directly connected to any signal wiring driven by an active element other than itself) ) A second active element is also provided and is provided on the receiving side of the inter-circuit signal wiring (that is, in the other circuit of the pair of internal circuits (that is, the internal circuit to which a relatively high power supply voltage is supplied)). No. for input and reception) in the vicinity of the first active device, the second or instead to the active element by omitting it (i.e. the second active element is not provided) the fourth
That is, (preferably a plurality of) active elements are provided.

In the semiconductor integrated circuit device of the eighth solving means as described above, there is a restriction in connecting active elements to both the inter-circuit auxiliary wiring and the power supply line, and the inter-circuit signal wiring is The second, fourth areas are vulnerable to the influence of (the receiving side of the inter-circuit signal wiring in the internal circuit to which a relatively low power supply voltage is supplied, that is, the input element is typical). While active elements are appropriately combined and provided, there is no such a restriction and a portion that is weak against the influence of inter-circuit signal wiring (such a portion is an internal circuit to which a relatively high power supply voltage is supplied. The fourth active element is provided as many as possible on the receiving side of the inter-circuit signal wiring in (i.e., where the input element is typical).

As a result, in a place where the influence of the inter-circuit signal wiring is weak, the protection by the fourth active element that positively disperses the influence of the inter-circuit signal wiring is preferentially applied, in which the peak of the potential difference is detected. It will be even lower. Therefore, according to the present invention, it is possible to realize a semiconductor integrated circuit device that is stronger against electrostatic breakdown and is suitable for automatic design and the like.

[Ninth Solving Means] A semiconductor integrated circuit device according to the ninth solving means (as described in claim 9 at the beginning of the application) is the semiconductor integrated circuit device according to the above second to eighth solving means. The active element corresponding to any one of the second, third, and fourth active elements or an active element corresponding thereto (that is, provided in the vicinity of the first active element and connected to the power supply line of the corresponding internal circuit). Even if the protection element which is not connected to the signal wiring in the corresponding internal circuit) is arranged so as to sandwich (enclose or directly) the first active element or the active element corresponding thereto, or A plurality of the same types are provided repeatedly (or mixedly in different types).

In the semiconductor integrated circuit device of the ninth solving means, the surge noise is detoured or dispersed at a plurality of locations on both sides or the periphery of the first active element. With the feeling of balancing, the relaxation will be fairly even. As a result, the protection for the first active element is enhanced as compared with the case where one protection element is provided or only one side of the first active element. Therefore, according to the present invention, it is possible to realize a semiconductor integrated circuit device that is more resistant to electrostatic breakdown and is suitable for automatic design and the like.

[0048]

BEST MODE FOR CARRYING OUT THE INVENTION Specific modes for carrying out the semiconductor integrated circuit device of the present invention achieved by the above solving means will be described with reference to the following first to sixth examples. The first embodiment shown in FIG.
The second and ninth solutions are embodied, and the second embodiment of FIG. 2 is an implementation of the above-described first, third, and ninth solutions, and the second embodiment of FIG. The third embodiment embodies the above-mentioned first, fourth, and ninth solving means.
The fourth embodiment of FIG. 4 embodies the above-mentioned first, fifth, sixth and ninth solving means, and the fifth embodiment of FIG. The fifth, seventh, and ninth solving means are embodied, and the sixth embodiment of FIG. 6 embodies the above-described first, eighth, and ninth solving means. It should be noted that what has already been described in the section of the background art is the same for each of the embodiments, so the repetitive description will be omitted, and the following description will be focused on the differences from the related art.

[0049]

First Embodiment A specific configuration of a first embodiment of a semiconductor integrated circuit device of the present invention will be described with reference to the drawings. 1A is a detailed circuit diagram of a main part, FIG. 1B is a layout diagram of a corresponding region, and FIG. 1C is a vertical cross-sectional perspective view of a semiconductor region and a gate which are basic units.

This semiconductor integrated circuit device has a power supply line 8
Internal circuit 4A having A and 9A and power supply lines 8B and 9
Internal circuit 4B having B, a plurality of internal circuits having different power supply lines, inter-circuit signal wiring 12 provided over the internal circuits 4A and 4B, and inter-circuit signal wiring 12 signal in the internal circuit 4A. Output element 12A connected to the sending side
And an input element 12B connected to the signal receiving side of the inter-circuit signal wiring 12 in the internal circuit 4B, and four pMOS transistors 12AP, 12BP and nMOS transistors 12AN, 12BN are used as the first active elements. This is the same as the semiconductor integrated circuit device 1 described above in terms of points, but is different in that the following is added in the vicinity of the first active element.

That is, regarding the basic cell to which the first active element 12AP is allocated, p is assigned to the basic cell on the left side of the basic cell.
The MOS transistor 21 is assigned, and the pMOS transistor 23 is also assigned to the right basic cell. Further, regarding the basic cell to which the first active element 12AN is allocated, the basic cell on the left side of the basic cell is nMO.
The S-transistor 22 is assigned and the nMOS transistor 24 is also assigned to the right basic cell. Similarly, with respect to the basic cell to which the first active element 12BP is assigned, the pMOS transistor 25 is assigned to the left basic cell, the pMOS transistor 27 is assigned to the right basic cell, and the basic cell to which the first active element 12BN is assigned. As for the basic cell on the left side, the nMOS transistor 26 is allocated and the basic cell on the right side is also allocated the nMOS transistor 28.

Of these transistors, the pMOS transistors 21 and 23 have sources and gates connected to the power supply line 8A and drains connected to the power supply line 9A. The sources and gates of the nMOS transistors 22 and 24 are connected to the power supply line 9A, and the drains are connected to the power supply line 8A. Similarly, the pMOS transistors 25 and 27 have a source and a gate connected to the power supply line 8B, a drain connected to the power supply line 9B, and an nMO.
The sources and gates of the S transistors 26 and 28 are connected to the power supply line 9B, and the drains are connected to the power supply line 8B.

A plurality of such MOS transistors 21
.. to 28 are provided in the vicinity of the first active element in a state of sandwiching the first active element from the left and right, and have the same pMOS / nMOS structure as the first active element, and have the same internal circuits 4A and 4B. Although only connected to the power supply lines 8A, 9A, 9B, 9B, they are not connected to the inter-circuit signal wiring 12 or other signal wiring, and the second active for protecting the first active element from the surroundings. It is an element. In addition, the layout and wiring pattern are added to the design tool for automatic wiring by adding a local library cell and
It is easily and automatically processed by designating each active element or automatically designating according to generation of inter-circuit signal wiring.

The operation of the semiconductor integrated circuit device according to the first embodiment during use will be described.

The MOS transistors 21 to 28 are connected between the power supply line pair 8A + 9A and 8B + 9B.
Since the source and the gate are connected, there is no conduction in the normal operating state, and not only the power supply voltage but also the inter-circuit signal wiring 12, the output element 12A, and the input element 1
It does not affect the operation of 2B.

However, since it is an active element, the active region such as a pn junction has a minute but parasitic capacitance, and instantaneous noise or the like can be bidirectionally flowed to some extent. . Furthermore, in the case of an active element provided in the basic cell of this example (for example, nMO of FIG.
(See S-transistor 22), a parasitic diode (2 that starts conducting when the drain tries to swing abnormally to the negative side).
2d), and the existence of a parasitic transistor (22t) that conducts and works when the drain bounces to the positive side abnormally large is also recognized.

Then, surge noise is introduced into the internal circuit 4B, which first propagates through the power supply line 8B and the input element 12
However, if the source of the pMOS transistor 12BP is connected to the power supply line 8B, the gate of the pMOS transistor 12BP is connected to the power supply line 8B, and the gate of the pMOS transistor 12BP is connected to the internal circuit 4A side without noise. Since it is regulated to the potential of, the pMOS transistor 12BP
The potential difference is concentrated between the source and the gate, and the gate oxide film there is exposed to the risk of electrostatic breakdown.

However, the surge noise on the power supply line 8B reaches the source of the pMOS transistor 12BP at almost the same time as it reaches the source of the pMOS transistor 12BP.
Reach ~ 28. Then, via these parasitic capacitances, and further depending on the noise state, they are more positively released to the power supply line 9B via the parasitic diode 22d and the parasitic transistor 22t. Thus pM
The surge current flowing into the source of the OS transistor 12BP is dispersed and slightly reduced.

The surge noise flowing to the power supply line 9B is
Since it is immediately transmitted to the source of the nMOS transistor 12BN, a potential difference appears between the source and the gate of the nMOS transistor 12BN, whereby the charge existing in the inter-circuit signal wiring 12 near the input element 12B is transferred to the transistor 12BP. , 12BN gate. In this way, the fear of electrostatic damage to the gate oxide film is further alleviated instantaneously.

Further, due to the surge current flowing into the MOS transistors 25 to 28, the potentials of the back gates and the like (that is, the region of the corresponding range in the substrate and the well) in their installation range are also raised or lowered. Therefore, accordingly, the potentials of the drains of the transistors 12BP and 12BN are also changed to some extent in the same direction as the sources. Then, also by this, the charges in the inter-circuit signal wiring 12 which are about to be biased to the source side in each of the transistors 12BP and 12BN are also dispersed to the drain side.

In this way, the surge noise that quickly reaches the input element 12B via the power supply line 8B is generated by the surrounding MOS.
By the transistors 25 to 28, they are quickly dispersed in the vicinity. Then, in the meantime, the surge noise also reaches from the power supply line 9B, and the regulation performed via the inter-circuit signal wiring 12 is also supplemented from the internal circuit 4A side. , Because the peak has collapsed on the way,
Since the possibility of electrostatically destroying the gate oxide film is relatively low, the electrostatic breakdown of the input element 12B can be more reliably prevented by dispersing / relaxing the surge noise that arrives first.
Will be deterred.

Although the detailed description which will be repeated is omitted, the surge noise propagating first on the other power supply lines 9B, 8A and 9A is almost similar to the input element 12B and the output element 12A. The electrostatic breakdown of will be more reliably prevented and suppressed.

[0063]

Second Embodiment A specific configuration of a second embodiment of the semiconductor integrated circuit device of the present invention will be described with reference to the drawings. 2A is a detailed circuit diagram of a main part, and FIG. 2B is a layout diagram of a corresponding region.

This semiconductor integrated circuit device differs from that of the first embodiment described above in that in the internal circuit 4A, the MOS transistors 21 to 24 are omitted from the periphery of the output element 12A, and in the internal circuit 4B. Is the power line 8 connected to the drains of the nMOS transistors 26 and 28.
The point is that the inter-circuit signal wiring 12 is replaced by B.

As a result, the pMOS transistor 25,
27 is the second active element that protects the first active element 12BP from the left and right, while the nMOS transistor 2
Reference numerals 6 and 28 are provided in the vicinity of the first active element 12BN so as to sandwich the first active element 12BN from the left and right.
Of the same nMOS structure as the corresponding internal circuit 4
Although it is connected to the power supply lines 8B and 9B of B and the signal wiring 12 between circuits, it is not connected to the other signal wirings, and is connected to the third active element for protecting the first active element 12BN from the surroundings. Has become.

In this case, the nMOS transistors 26, 2
8 shows that although the rise and fall of the signal on the inter-circuit signal wiring 12 may be slightly dull, the inter-circuit signal wiring 1
Unless the voltage of 2 and the voltage of the power supply line 9B are reversed or abnormally separated, there is no conduction, so that proper operation of the internal circuits 4A and 4B is not impaired.

When the surge noise reaches the input element 12B through the power line 8B before the power line 9B, the surge noise is generated by the pMOS transistors 25 and 27 in the same manner as described above. 9B, etc., but in this case, in addition to this, the third active elements 26, 28 act as diodes when the potential difference between the power supply line 9B and the inter-circuit signal wiring 12 is reversed or abnormally separated. Conducting by a punch-through operation, the surge noise is released from the power supply line 9B to the inter-circuit signal wiring 12 along with the actual current.

Thus, the potential difference between the inter-circuit signal wiring 12 and the power supply lines 9B and 8B is suppressed more positively than in the first embodiment, and the first active elements 12BP and 12BP.
Since the peak of the potential difference between the gate and the source and the drain in BN is strongly suppressed, the fear of electrostatic breakdown of the gate oxide film of the input element 12B is sufficiently mitigated.

The influence of surge noise flowing into the inter-circuit signal wiring 12 is caused by the first active element 12A of the internal circuit 4A.
Although it extends to P and 12AN, in addition to connecting the inter-circuit signal wiring 12 to the drain instead of the gate to the first active element, surge noise is collapsed due to the parasitic inductance of the inter-circuit signal wiring 12. Therefore, the possibility that the output element 12A is electrostatically destroyed is low. From this point of view, the MOS transistors 21 to 24 are omitted, and a trade-off between protection efficiency and an increase in the number of elements is achieved.

[0070]

[Third Embodiment] A specific configuration of a third embodiment of the semiconductor integrated circuit device of the present invention will be described with reference to the drawings. FIG. 3 is a detailed circuit diagram of a main part.

This semiconductor integrated circuit device differs from that of the second embodiment described above in that the signal transmission / reception direction is the inter-circuit signal wiring 12
The inter-circuit signal wiring 13, which is the opposite of the above, is explicitly provided, and a similar protection measure is also taken for this inter-circuit signal wiring 13.

That is, with respect to the inter-circuit signal wiring 12, a protective element is not added to the output element 12A on the sending side, and a second active element is provided as a protective element around the input element 12B corresponding to the receiving side of the inter-circuit signal wiring 12. 25 and 27 and the third active elements 26 and 28 are provided in a mixed manner, the inter-circuit signal wiring 13 does not have a protective element added to the output element 13B on the sending side thereof. There are four MOS elements as protection elements around the input element 13A that is the receiving side of
Transistors 31 to 34 are arranged.

Among them, the transistors 31, 33
Is a pMOS transistor having the same structure as the first active element 13AP and is provided separately on the right and left sides of the first active element 13AP. Further, the transistors 32 and 34 are nMOS transistors having the same structure as the first active element 13AN and are provided separately on the left and right sides of the first active element 13AN. Further, these transistors 31 to 34 are
In each case, the source and gate are connected to the power supply line 8A of the relevant internal circuit 4A, and the drain is connected to the inter-circuit signal wiring 13, but not connected to other signal wirings, and the first active element 13AP , 13AN is a third active element for protecting the surroundings. As a result, in this semiconductor integrated circuit device, there is no second active element in the vicinity of the first active element 13A on the receiving side of the inter-circuit signal wiring 13,
Only a plurality of active elements are provided.

In this case, the inter-circuit signal wiring 12 is protected in the same manner as described above. Further, regarding the inter-circuit signal wiring 13, the nMOS transistors 32 and 3 are also included.
Similar to the nMOS transistors 26 and 28 described above, 4 does not conduct unless the voltage of the inter-circuit signal wiring 13 and the voltage of the power supply line 9A are reversed or abnormally separated. Also, in the pMOS transistors 31 and 33, in the normal state, the voltage of the power supply line 8A is the power supply line 8B.
Since it is higher than the maximum voltage of the inter-circuit signal wiring 13 due to the driving of the circuit, the voltage of the inter-circuit signal wiring 13 and the power supply line 8A It does not conduct unless the voltage of is reversed or abnormally separated. Therefore, also in this case, the proper operation of the internal circuits 4A and 4B is maintained.

Regarding the inter-circuit signal wiring 13,
Input element 13A has four surrounding additional transistors 3
Since it is positively protected by 1 to 34, stronger protection than that of the inter-circuit signal wiring 12 can be obtained. In this way, it is possible to appropriately prevent the electrostatic breakdown due to the surge noise and the like in the situation shown in FIG. 9C while suppressing the increase in the circuit scale as much as possible.

[0076]

Fourth Embodiment A specific configuration of a fourth embodiment of the semiconductor integrated circuit device of the present invention will be described with reference to the drawings. FIG. 4A is a detailed circuit diagram of a main part, and FIG. 4B is a layout diagram of the corresponding region.

This semiconductor integrated circuit device differs from the second embodiment shown in FIG. 2 in that the inter-circuit auxiliary wiring 29 is introduced. The inter-circuit auxiliary wiring 29 is provided for each inter-circuit signal wiring 12, and is drawn in a state in which a portion parallel to the inter-circuit signal wiring 12 increases so as to match the transmission states such as propagation delay time as much as possible. Being turned,
It is arranged in parallel with the inter-circuit signal wiring 12.

One end of the inter-circuit signal wiring 13 is directly connected to the source of the pMOS transistor 12AP in the internal circuit 4A (see FIG. 4B). This source region is a partial region of the first active element to which the inter-circuit signal wiring 12 is connected and which is connected to the power supply line 8A of the relevant internal circuit 4A in the active element 12AP on the transmission side. It can be said to be a static location near the location.

With the introduction of the inter-circuit auxiliary wiring 29, the connection destinations of the drains of the nMOS transistors 26 and 28 are changed from the inter-circuit signal wiring 12 to the inter-circuit auxiliary wiring 29. That is, the other end of the inter-circuit signal wiring 13 is connected to the transistors 26 and 28 in the internal circuit 4B. As a result, the transistors 26 and 28 have the same structure as or a structure similar to that of the receiving side of the first active element 12BN and are provided in the vicinity thereof, and are separated from the signal wiring other than the inter-circuit auxiliary wiring 29. It is the fourth active element and can be said to be a static part.

Further, with the introduction of the inter-circuit auxiliary wiring 29, the p described in the first embodiment of FIG. 1 is provided in the internal circuit 4A.
MOS transistor 21 and nMOS transistor 22
Has been revived. These are connected in the same manner as in the first embodiment and are second active elements provided near the input element 12B.

In this case, the inter-circuit auxiliary wiring 29 and the nMO
Each of the S transistors 26 and 28 has an internal circuit 4A,
It is not connected to the signal wiring in 4B, and the nMOS
The transistors 26 and 28 do not become conductive unless the voltage of the power supply line 8A and the voltage of the power supply line 9B are reversed or abnormally separated. Therefore, by introducing the inter-circuit auxiliary wiring 29, the internal circuits 4A and 4B are not connected. Proper operation is not impaired. Also, from the inter-circuit signal wiring 12 to nM
Since the OS transistors 26, 28 and the like are separated, the signal on the inter-circuit signal wiring 12 does not become blunt, which is preferable in terms of performance and is easy even when high-speed operation is required for the application. Can be applied to.

Then, as described above, the power supply line 8B,
The second active elements 25 and 27 disperse and mitigate the surge noise having a slow speed at 9B, and the surge noise dispersed in the vicinity of the input element 12B and the entire input element 12B in the internal circuit 4B have a potential. If there is a surge noise that changes, the inter-circuit auxiliary wiring 29 or the like acts on it in the following manner.

That is, the first active element 1 that has changed abnormally
The potential in the vicinity of 2BN is transmitted to the source of the first active element 12AP in the internal circuit 4A via the fourth active elements 26, 28 and the inter-circuit auxiliary wiring 29, and is also propagated to its drain by its parasitic capacitance and the like. . Then, since the inter-circuit signal wiring 12 is connected to the drain, the potential fluctuation returns to the gates of the first active elements 12BN and 12BP while being attenuated. In this way, the potential difference between the gate and the source of the input element 12B due to the surge noise is reduced or alleviated.

In addition, the second active element 2 in the internal circuit 4A
In addition to mitigating surge noise directly on the internal circuit 4A side in the same manner as the second active elements 25 and 27, the first and second circuits 22 and 22 are provided with the first inter-circuit auxiliary wiring 29 as described above.
Even with respect to the secondary potential fluctuation caused by the source of the active element 12AP, it is dispersed in the vicinity of the output element 12A to directly protect the output element 12A and indirectly to the input element. The element 12B is also protected.

It should be noted that the more second active elements provided in the vicinity of the first active element 12A in the internal circuit 4A, the better it is from the viewpoint of protection capability, but it does not directly contribute to the application, so an increase in circuit scale is required. In order to make a trade-off with the viewpoint of suppression, the number is only two. Thus, not only FIG. 9 (c) but also FIG. 9 (a),
Even with respect to the surge noise in the situation shown in (b), it is possible to appropriately prevent electrostatic breakdown due to them while suppressing an increase in circuit scale as much as possible.

[0086]

Fifth Embodiment A specific configuration of the fifth embodiment of the semiconductor integrated circuit device of the present invention will be described with reference to the drawings. FIG. 5A is a detailed circuit diagram of a main part, and FIG. 5B is a layout diagram of the corresponding region. This semiconductor integrated circuit device is different from the fourth embodiment shown in FIG. 4 in that the end portion of the inter-circuit auxiliary wiring 29 on the input element 12B side is the first active element 12.
That is, the source of the AP is replaced with the power supply line 8A.

However, the connection point is the power line 8
In A, first, the upper layer portion of the source region of the pMOS transistor 12AP which is the first active element is selected (see FIG. 5).
(B)), if that is not possible, any part of the upper layer portion of the region occupied by the pMOS transistor 12AP is selected, and if that is also impossible, p
Any part of the upper layer portion of the basic cell region to which the MOS transistor 12AP is allocated is selected. The connection location of the inter-circuit auxiliary wiring 29 selected in this manner is settled in the neighboring area that overlaps or is close to the source area (partial area) in the corresponding power supply line 8A.

In this case, the pMOS transistor 12AP
Source is also connected to the power line 8A, and
In most cases, since the source region of the pMOS transistor 12AP and the power supply line 8A are connected at a position where they overlap or are extremely close to each other, regarding the propagation of surge noise between the inter-circuit auxiliary wiring 29 and the first active element 12AP, etc. Also, the inter-circuit auxiliary wiring 29 is almost the same as the case of the fourth embodiment in which the source of the first active element 12AP is directly connected.

[0089]

[Sixth Embodiment] The specific configuration of a sixth embodiment of the semiconductor integrated circuit device of the present invention will be described with reference to the drawings. FIG. 6 is a detailed circuit diagram of a main part.

This semiconductor integrated circuit device differs from that of the fifth embodiment described above in that the signal transmission / reception direction is the inter-circuit signal wiring 12
The inter-circuit signal wiring 13 opposite to the above is explicitly provided, and the inter-circuit auxiliary wiring 39 is also provided in this inter-circuit signal wiring 13.
The similar protection measures are adopted.

That is, the inter-circuit auxiliary wiring 39 is arranged along the inter-circuit signal wiring 13 from the source of the first active element 13BP in the output element 13B in the internal circuit 4B corresponding to the transmission side of the inter-circuit signal wiring 13. It extends to 4A. In addition, in the internal circuit 4B, the first active element 13B
In the vicinity of P and 13BN, the above-mentioned protection transistor 2
Similar to 1 and 22, the pMOS transistor 35 and the nMOS transistor 3 are connected as the second active element.
6 is provided. On the other hand, in the internal circuit 4A, in the vicinity of the first active element 13A corresponding to the receiving side of the inter-circuit signal wiring 13, four MOS transistors 31 as protection elements are provided.
~ 34 are provided.

Among them, the transistors 31, 33
Is a pMOS transistor having the same structure as the first active element 13AP and is provided separately on the right and left sides of the first active element 13AP. Further, the transistors 32 and 34 are nMOS transistors having the same structure as the first active element 13AN and are provided separately on the left and right sides of the first active element 13AN. Further, these transistors 31 to 34 are
In both cases, the source and gate are connected to the power supply line 8A of the corresponding internal circuit 4A, and the drain is connected to the inter-circuit auxiliary wiring 39, but not connected to other signal wirings, and the first active element 13AP , 13AN is a fourth active element for protecting the surroundings. As a result, in this semiconductor integrated circuit device, there is no second active element in the vicinity of the first active element 13A on the receiving side of the inter-circuit signal wiring 13,
Only a plurality of active elements are provided. It should be noted that, in the vicinity of the first active element 12B on the receiving side of the inter-circuit signal wiring 12, the second active element and the fourth active element are mixed, as in the above example.

In this case, the inter-circuit signal wiring 12 and the inter-circuit auxiliary wiring 29 are protected in the same manner as described above. Also regarding the inter-circuit signal wiring 13 and the inter-circuit auxiliary wiring 39, the nMOS transistors 32 and 34 are
Similar to the nMOS transistors 26 and 28 described above, there is no conduction unless the voltage of the power supply line 8B and the voltage of the power supply line 9A are reversed or abnormally separated. Similarly, the pMOS transistors 31 and 33 do not become conductive unless the voltage of the power supply line 8B and the voltage of the power supply line 8A are reversed or abnormally separated. Therefore, by introducing the inter-circuit auxiliary wiring 39, the internal circuit 4
The proper operation of A and 4B is not impaired. Also,
Since all of these transistors 31 to 36 are separated from the inter-circuit signal wiring 13,
The signal above is not dulled.

Regarding the inter-circuit signal wiring 13,
Input element 13A has four surrounding additional transistors 3
Since it is positively protected by 1 to 34, stronger protection than that of the inter-circuit signal wiring 12 can be obtained. In this way, it is possible to appropriately prevent electrostatic damage caused by surge noises and the like in all situations shown in FIGS. 9A to 9C while suppressing an increase in circuit scale as much as possible.

[0095]

[Others] In each of the above embodiments, the internal circuit is CM.
I mentioned the case of OS, but this is just an example.
The present invention can be applied even if it is composed of an FET such as OS, nMOS, and MNOS. Further, it may include a bipolar transistor, and may be a digital circuit or an analog circuit.

The number of internal circuits is not limited to two,
The number may be three or more, and the arrangement thereof is not limited to the left and right and is arbitrary. The power supply line is not limited to the above-mentioned pair for positive voltage application and ground, and for example, a pair of positive and negative, a pair of positive and negative and ground, a high voltage, a low voltage and other There can be various combinations such as a combination with a reference voltage.

Further, in the drawings of the above-mentioned embodiments and the like, only the 2nd row, 1st column to the 2nd row, 3rd column is shown as the active elements in the internal circuit, but this is only a part, and more active elements than that are shown. Arrangement of multiple rows and multiple columns arranged in general is common. The inter-circuit signal wiring may be only the inter-circuit signal wiring 12 or only the inter-circuit signal wiring 13, and the number is not limited to one, but a plurality of wirings may be provided, and the number of the wirings prevents the application of the present invention. There is no.

In addition, although the p-type substrate is mentioned in the above-mentioned embodiments and the like, the substrate is not limited to the p-type substrate, and the n-type substrate may be used.
It may be of a mold type or an insulating type, and not only silicon but also gallium arsenide (AsP) or the like may be used. The basic cell is also described as a set of two transistors, but the number is not limited to this, and may be one transistor or more transistors.

Further, since the present invention is neither exclusive nor presupposed of the conventional input protection circuit and inter-block protection circuit, these protection circuits may be omitted before application. You may make it apply, making a circuit coexist.

[0100]

As is apparent from the above description, in the semiconductor integrated circuit device according to the first solution of the present invention, potential fluctuations due to surge noise are swiftly generated near the first active element. It is evenly dispersed and the peak is suppressed, and the newly introduced protection element is embodied in the same procedure as the first active element etc., so it is resistant to electrostatic breakdown and is also suitable for automatic design etc. Also, there is an advantageous effect that a suitable semiconductor integrated circuit device can be realized.

In the semiconductor integrated circuit device according to the second solving means of the present invention, potential fluctuations due to surge noise are quickly dispersed near the first active element to suppress the peak, and newly added. The introduced second active element is the first
A semiconductor integrated circuit device that is resistant to electrostatic damage and is suitable for automatic design and the like is realized by the same procedure as that for active elements and the like, and acts as a protection element regardless of the level of the power supply voltage. The advantageous effect that it was able to be achieved is produced.

Furthermore, in the semiconductor integrated circuit device of the third means for solving the problems of the present invention, a third active element for positively dispersing the influence of the inter-circuit signal wiring is also introduced, and the third active element is also used. By embodying in the same procedure as that of the two active elements, there is an advantageous effect that a semiconductor integrated circuit device that is more resistant to electrostatic breakdown and suitable for automatic design and the like can be realized.

Further, in the semiconductor integrated circuit device of the fourth solution of the present invention, the influence of the inter-circuit signal wiring is positively distributed to the receiving side which is weak against the influence of the inter-circuit signal wiring. By using the third active element a lot,
An advantageous effect that a semiconductor integrated circuit device that is stronger against electrostatic breakdown and suitable for automatic design and the like can be realized.

Further, in the semiconductor integrated circuit device of the fifth solving means of the present invention, the local potential fluctuation caused by the inter-circuit signal wiring and the inter-circuit auxiliary wiring is overlapped to make the first active. A semiconductor integrated circuit that is resistant to electrostatic damage and is also suitable for automatic design, etc., because the peak of the potential difference generated in the element can be suppressed to a low level and a new protection circuit can be introduced by additional modification of the wiring pattern. There is an advantageous effect that the device could be realized.

Further, in the semiconductor integrated circuit device according to the sixth solution of the present invention, the influence of the inter-circuit signal wiring generated in the relatively weak receiving side is relatively strong in the transmitting side. By making it dispersed, there is an advantageous effect that it is possible to realize a semiconductor integrated circuit device that is more resistant to electrostatic breakdown and is suitable for automatic design and the like.

Further, in the semiconductor integrated circuit device of the seventh means of solving the problems of the present invention, since the restriction on the connection point of the inter-circuit auxiliary wiring is relaxed, it is more resistant to electrostatic breakdown. Also, there is an advantageous effect that a semiconductor integrated circuit device that is more suitable for automatic design and the like can be realized.

In the semiconductor integrated circuit device according to the eighth solution of the present invention, the influence of the inter-circuit signal wiring is positively distributed to the receiving side which is weak against the influence of the inter-circuit signal wiring. By making heavy use of the fourth active element,
An advantageous effect that a semiconductor integrated circuit device that is stronger against electrostatic breakdown and suitable for automatic design and the like can be realized.

Further, in the semiconductor integrated circuit device of the ninth solving means of the present invention, potential fluctuations due to surge noise are rapidly and uniformly dispersed in the vicinity of the first active element to suppress the peak. By doing so, the advantageous effect that the protection for the first active element is strengthened, and the semiconductor integrated circuit device that is stronger against electrostatic breakdown and is suitable for automatic design and the like can be realized. There is.

[Brief description of drawings]

FIG. 1A is a detailed circuit diagram of an essential part of a semiconductor integrated circuit device according to a first embodiment of the present invention, FIG. 1B is a layout diagram of a corresponding region, and FIG. FIG. 3 is a vertical cross-sectional perspective view of a gate.

2A is a detailed circuit diagram of a main part of the semiconductor integrated circuit device according to the second embodiment of the present invention, and FIG. 2B is a layout diagram of a corresponding region.

FIG. 3 is a detailed circuit diagram of essential parts of a third embodiment of the semiconductor integrated circuit device of the present invention.

FIG. 4A is a detailed circuit diagram of a main part of a semiconductor integrated circuit device according to a fourth embodiment of the present invention, and FIG. 4B is a layout diagram of a corresponding region.

FIG. 5A is a detailed circuit diagram of a main part of a semiconductor integrated circuit device according to a fifth embodiment of the present invention, and FIG. 5B is a layout diagram of a corresponding region.

FIG. 6 is a detailed circuit diagram of essential parts of a sixth embodiment of the semiconductor integrated circuit device of the present invention.

FIG. 7 shows a general structure of a semiconductor integrated circuit device having a plurality of internal circuits having different power supply lines, (a) is a schematic layout diagram of the entire chip, and (b) is a circuit diagram of a main part.

8A and 8B show, at an element level, a portion for transmitting and receiving a signal between the internal circuits, FIG. 8A is a detailed circuit diagram, FIG. 8B is a layout diagram of a semiconductor region, and FIG. 8C is a pattern of gates and power supply lines. A layout diagram of the formed portion, (d) is a layout diagram of further formed signal wiring pattern, and (e) is a longitudinal sectional perspective view of a semiconductor region and a gate which are basic units.

FIG. 9 is an image diagram showing the influence of surge noise.

[Explanation of symbols]

1 semiconductor integrated circuit device (one-chip IC, LSI) 2 external connection terminal (pad, bump, ball, land, electrode) 3A external signal input / output circuit (I / O unit to which relatively high power supply voltage is supplied) 3AA Input protection circuit (protection circuit between external signal input line and power supply line) 3B External signal input / output circuit (I / O unit supplied with relatively low power supply voltage) 3BB Input protection circuit (external signal input line and power supply line) 4A internal circuit (high-density integrated circuit section supplied with relatively high power supply voltage) 4B internal circuit (high-density integrated circuit section supplied with relatively low power supply voltage) 4c inter-block protection circuit (Protection circuit between internal circuits 4A and 4B) 5A High power supply terminal (one of the external connection terminal pair that supplies higher power supply voltage) 5B Low power supply terminal (Lower power supply voltage is supplied) 6A Grounding terminal (the other of the external connecting terminal pair that supplies the higher power supply voltage) 6B Grounding terminal (the other of the external connecting terminal pair that supplies the lower power supply voltage) 7A Input / output Terminal (external connection terminal connected to internal circuit on high voltage receiving side) 7B input / output terminal (external connection terminal connected to internal circuit on low voltage receiving side) 8A power supply line (power supply line for high voltage supply) One side of the pair, 5V voltage line) 8B power line (one side of the power line for low voltage supply, one side of the 3V voltage line) 9A power line (other side of the power line pair for high voltage supply, 5V ground line) 9B power line ( The other side of the power supply line pair for low voltage supply, 3V ground line) 11A internal element (circuit element in internal circuit on high voltage receiving side) 11B internal element (circuit in internal circuit on low voltage receiving side) 12) Output element (element that sends a signal from a higher power supply voltage to a lower internal circuit) 12AP 1st active element (sending in an internal circuit on the high voltage side) Side pMOS) 12AN 1st active element (nMOS on the sending side in the internal circuit on the high voltage side) 12B Input element (an element that receives a signal sent from a higher power supply voltage) 12BP 1st active element (low voltage) PMOS on the receiving side in the internal circuit on the side) 12BN First active element (nMOS on the receiving side in the internal circuit on the low voltage side) 13 Inter-circuit signal wiring (pattern wiring reaching other internal circuits) 13A Input element (supply voltage Element receiving the signal sent from the lower side) 13AP First active element (pMOS on the receiving side in the internal circuit on the high voltage side) 13AN First active element (NMOS on the receiving side in the internal circuit on the high voltage side) 13B output element (an element that sends a signal from the lower power source voltage to the internal circuit on the higher side) 13BP First active element (pMOS on the transmitting side in the internal circuit on the low voltage side) 13BN 1st active element (nMOS of sending side in internal circuit of low voltage side) 21-28 active element (2nd, 3rd and 4th active element, other active elements in the vicinity) 22d parasitic diode 22t parasitic transistor 29 circuit Inter-wiring (Pattern wiring that runs parallel to other internal circuits) 31-36 Active elements (second, third, fourth active elements, other active elements in the vicinity) 39 Inter-wiring auxiliary wiring (runs in parallel) Pattern wiring to other internal circuits) SA internal signal wiring (signal line in high voltage side internal circuit) SB internal signal wiring (signal line in low voltage side internal circuit)

─────────────────────────────────────────────────── ─── Continuation of the front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) H01L 21/822 H01L 21/82 H01L 27/04

Claims (7)

(57) [Claims] 1. A semiconductor integrated circuit device comprising a plurality of internal circuits having different power supply voltages, and an inter-circuit signal wiring provided over the internal circuits, wherein a first inter-circuit signal wiring is connected. An active element and a first active element in the vicinity of the first active element, which has the same structure as or a similar structure to the first active element and is connected to a power supply line of a corresponding internal circuit and separated from the inter-circuit signal wiring and other signal wiring ; A second active element for protecting the first active element; and a second active element in the vicinity of the first active element, which has the same structure as or a structure similar to that of the second active element and which is connected to the power supply line of the corresponding internal circuit and the inter-circuit signal wiring A semiconductor integrated circuit device comprising a plurality of third active elements, which are separated from the signal wiring and protect the first active element, for any one pair of the plurality of internal circuits,
A plurality of the inter-circuit signal wirings having different transmission and reception directions are provided, and the second active circuit is provided in the vicinity of the first active element on the receiving side of the inter-circuit signal wiring in one of the pair of internal circuits. An element and the third active element are provided, and the second active element is not provided in the vicinity of the first active element on the receiving side of the inter-circuit signal wiring in the other circuit of the pair of internal circuits. A semiconductor integrated circuit device, wherein the third active element is provided in the. 2. A region corresponding to any one of the second and third active elements or a formation region of an active element corresponding thereto,
2. The semiconductor integrated circuit device according to claim 1, wherein a plurality of the semiconductor integrated circuit devices are provided in such a state that the formation region of the first active element or an active element corresponding thereto is sandwiched or surrounded. 3. A semiconductor integrated circuit device comprising a plurality of internal circuits having different power supply voltages and an inter-circuit signal wiring provided over the internal circuits, in the vicinity of a connection point of the inter-circuit signal wiring. A semiconductor integrated circuit device, characterized in that auxiliary wiring between circuits connected to a static portion is provided. 4. A partial region of the first active element connected to the inter-circuit signal wiring, which is connected to the power supply line of the corresponding internal circuit, in the static portion, and the first active element. detached from the receiver side and what the same structure or be similar structure signal lines other than provided the circuit between the auxiliary lines in the vicinity of the first active element of the receiving side of the device, the first active 4. The semiconductor integrated circuit device according to claim 3, further comprising a fourth active element for protecting the element. 5. The inter-circuit auxiliary wiring is connected to, in place of the partial area, a neighboring area which overlaps or is close to the partial area in a corresponding power supply line connected thereto. The semiconductor integrated circuit device according to claim 4, wherein the semiconductor integrated circuit device is a semiconductor integrated circuit device. 6. A plurality of the inter-circuit signal wirings having different transmission and reception directions are provided for any one pair of the plurality of internal circuits, and the one of the pair of internal circuits is provided with the inter-circuit signal wiring. In the vicinity of the first active element on the receiving side of the inter-circuit signal wiring, in addition to the fourth active element, one having the same structure as or a structure similar to that of the fourth active element and connected to the power supply line of the corresponding internal circuit, A second active element for protecting the first active element, which is separated from the wiring or other signal wiring and the inter-circuit auxiliary wiring, is also provided, and the inter-circuit signal in the other circuit of the pair of internal circuits is also provided. in the vicinity of the first active device of the reception side of the wiring, the fourth active element but is provided to the power supply line of the corresponding internal circuit be of or similar structure of the fourth active element of the same structure Connected said circuit The second active element is not provided, separated from the signal lines other signal line and the circuit between the auxiliary lines, a semiconductor integrated circuit device according to claim 4 or claim 5, characterized in that. 7. A region corresponding to any one of the second and fourth active elements or a formation region of an active element corresponding thereto,
7. The semiconductor integrated device according to claim 4, wherein a plurality of the first active elements or active elements corresponding to the first active elements are provided so as to sandwich or surround the formation area. Circuit device.