JP3471237B2 - Data processing method and apparatus, pattern forming method and apparatus, information storage medium - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processing method and apparatus for generating image data necessary for forming a circuit pattern from circuit data in which various circuit elements of an integrated circuit are expressed in a hierarchical structure, and this data processing. Pattern forming method and apparatus for forming a circuit pattern on a circuit material with image data generated by the method and apparatus, and information in which a program for causing a computer to execute a processing operation for generating image data from the circuit data is stored as software. A storage medium.

[0002]

2. Description of the Related Art Recently, LSI (Large Scale Integrated)
Circuit) is widely used for various purposes, and it is desired to mass-produce such an integrated circuit device with good productivity. When manufacturing an integrated circuit device, circuit data in which various circuit elements of the integrated circuit are expressed in a hierarchical structure is created, and this circuit data is converted into image data corresponding to a circuit pattern of an actual integrated circuit.

For example, a manufactured integrated circuit device is a RAM (R
In the case of an andom access memory), a large number of memory cells having the same structure are arranged as circuit elements. Therefore, in the circuit data of the RAM, only one memory cell is defined and the data capacity is reduced by combining the area data indicating the existing area. However, in the image data, this is actually the circuit pattern of many memory cells. The image data is obtained by repeating.

FIG. 1 shows this data processing method as a conventional example.
This will be described below with reference to FIGS. Note that FIG.
0 is a schematic diagram showing a hierarchical structure of a circuit pattern of an integrated circuit device, FIG. 12 is a schematic diagram showing a data structure of circuit data, FIG. 11 is a schematic diagram showing an internal structure of a circuit cell which is one circuit element, and FIG. Is a schematic diagram showing a conventional data processing method,
Is.

Generally, an integrated circuit device is composed of a plurality of circuit elements. As shown in FIGS. 10 and 11, such circuit elements include circuit cells "AE ..." and element elements "x, y".
, X, Y .... That is, the circuit element is a general term for circuit cells and element elements, and the mutual relation of the circuit elements in the integrated circuit device can be expressed by a hierarchical structure.

For example, in the integrated circuit device illustrated here, as shown in FIG. 10, two circuit cells "A, B" are included in the entire area "TOP", and the circuit cell "A" is included.
Contains two circuit cells "C, D". The circuit cell "D" includes the lowermost circuit cell "E". As shown in FIG. 11, the lowermost circuit cell "E" is included.
Contains a plurality of element elements "x, y ..., X, Y ...".

In the case of the present example, the origin coordinates of the circuit cells "A, B ..." Are "[0,0] =
(Ax, Ay), [0,0] = (Bx, By) ... ”, and the origin coordinates of the element elements“ x, y ..., X, Y ... ”are“ (a, b) ”. , (C, d) ..., (A, B), (C, D) ... ”.

Therefore, in the circuit data in which various elements of such an integrated circuit are expressed in a hierarchical structure, as shown in FIG. 12, the relationship with the lower circuit cell is defined for each circuit cell, and the circuit cell Area data indicating the existing area is set individually for each. However, since the area data of this circuit cell is expressed by the relative coordinates in the upper circuit cell, it is necessary to convert it into the absolute coordinates in the entire area when actually forming the circuit pattern.

For example, as shown in FIG. 11, there are three transistor elements in the lowest circuit cell "E", and the element coordinates of the diffusion layer "x, y, z" which are the element elements are "( a, b), (c, d), (e, f) ", and the element coordinates of the gate layer" X, Y, Z "which are the element elements are" (A, B),
In the case of (C, D), (E, F) ", these are circuit cells" E "
Since it is a relative coordinate from the cell coordinate (0,0) of, the origin coordinate (0,0) of the whole area "TOP" is formed when the circuit pattern is formed.
Need to be converted to absolute coordinates from.

Therefore, in the data processing method of the conventional data processing apparatus, as shown in FIG. 13, circuit data in which various circuit elements are expressed in a hierarchical structure as described above is acquired.
(Step S1), the hierarchical structure and definition information are read from the acquired circuit data (Steps S2 and S3), the hierarchical structure of the circuit data is expanded, and expanded data is generated.
(Steps S4 and S5).

This is an existing process for expanding the hierarchical structure of the circuit data to generate intermediate data corresponding to the image data of the circuit pattern of the integrated circuit.
No. 257072, Japanese Patent Application Laid-Open No. 4-267323, Japanese Patent Application Laid-Open No. 4-302451 and the like.

The expanded data generated as described above corresponds to the image data of the circuit pattern, but the expanded data at this stage has data contents arranged in order for each circuit cell. Therefore, the pattern forming device EB (Elect
In the case of actually forming an integrated circuit or a photomask with an exposure device, a mask manufacturing device, or the like, the circuit pattern is sequentially scanned in absolute coordinates in the xy directions.

In a general EB exposure apparatus, since the distortion of the circuit pattern to be formed is set to a predetermined reference or less, the unit area in which the circuit pattern is formed at once is limited to a predetermined range. Therefore, when the EB exposure apparatus forms a large circuit pattern, it is necessary to divide the entire area of the image data into a plurality of unit areas and sequentially form the circuit pattern for each unit area.

Therefore, when supplying image data of a large circuit pattern to the EB exposure apparatus, it is preferable to divide the image data into a plurality of unit areas and then supply the image data in order. Furthermore, if the relative coordinates of the circuit elements are converted into the absolute coordinates of the image data, the EB exposure apparatus can efficiently form the circuit pattern by sequential scanning.

Therefore, in the conventional data processing method of the data processing device, the expanded data expanded in the entire area is stored and then the sorting process is executed (steps S6 and S7). In this sort process, the circuit elements are converted into the absolute coordinate order based on the element coordinates, so that sort data corresponding to the sequential scanning of the circuit pattern is generated (step S8).

The sorting process will be described in detail below with reference to the lowest-order circuit cell "E" illustrated in FIG.
First, since it is necessary to divide the element elements into layers for each manufacturing process, in the case of the transistor element of the circuit cell "E", the diffusion layer "x, y, z" and the gate layer "X, Y, Z" are formed. It is divided into layers.

The element elements hierarchically divided in this way are sorted in ascending order by the numerical value of the y coordinate of the element coordinates, and when the numerical values of the y coordinate are the same, they are sorted by the numerical value of the x coordinate in ascending order. When the sorting process is executed by the transistor elements of the circuit cell "E", the order of the diffusion layers "x, y, z" is "y (c, d), z (e, f), x (a, b". ) ”, And the order of the gate layers“ X, Y, Z ”is“ Y (C, D), Z (E,
F), X (A, B) ".

When sort data is generated by the sort processing as described above, the sort data is stored as image data of a predetermined format, divided into predetermined unit areas, and supplied to an EB exposure device or the like (step). S9, S10). The EB exposure apparatus can manufacture an integrated circuit or a photomask by forming a circuit pattern on a silicon wafer or a mask substrate, which is a circuit material, by progressive scanning corresponding to image data input externally for each unit area.

[0019]

In the data processing method of the data processing apparatus described above, image data is generated from circuit data having a hierarchical structure, so that a circuit pattern can be formed by sequential scanning corresponding to this image data. .

However, when the image data is generated from the circuit data, the expanded data in the entire area in which the hierarchical structure of the circuit data is expanded is collectively sorted. Therefore, it is necessary to temporarily store a large amount of expanded data. The data capacity of sort processing is huge and the processing load is excessive.

Generally, when the data capacity becomes "N" times, the time required for the sorting process becomes "N.multidot.logN" times, so that the circuit scale is too large and the number of elements is enormous, which is the current high integration ULS.
In the case of I (Ultra LSI) or the like, if the circuit data is expanded into expanded data and then sorted, a lot of time is required for the processing.

Further, as described above, the conventional data processing apparatus requires a large-capacity work memory to process the large-capacity expanded data, and it is necessary to read and write the large-capacity expanded data in this work memory. Therefore, the efficiency of generating the image data from the circuit data is reduced. For example, it may be possible to use a data processing device having a high processing speed in order to shorten the processing time, but this is not preferable because the burden of capital investment is large.

The present invention has been made in view of the above problems, and a data processing method and apparatus capable of efficiently generating image data from circuit data having a hierarchical structure and not requiring a large-capacity data memory, A pattern forming method and apparatus capable of efficiently forming a circuit pattern based on hierarchically structured circuit data without requiring a large-capacity data memory, and causing a computer to efficiently execute a processing operation of generating image data from the circuit data. An information storage medium in which a program for is stored as software,
The purpose is to provide.

[0024]

A first data processing device of the present invention is a data processing device for developing image data by expanding circuit data in which various circuit elements of an integrated circuit are expressed in a hierarchical structure. And area dividing means for dividing the circuit data into a plurality of divided areas, and data for individually expanding the circuit data of the plurality of divided areas divided by the area dividing means to generate expanded data. Expanding means, data sorting means for individually processing expanded data of a plurality of divided areas generated by the data expanding means to generate a plurality of sort data, and individually sorting
Merge processing of the sorted data of multiple divided areas that have been processed
Data to generate image data for one whole area
The data merging means.
Before merging the sort data, the data source
It is characterized in that the sorting process is performed by a printing means.

A second data processing device of the present invention detects a whole area of an integrated circuit of the circuit data acquired by the structure acquisition means and the structure acquisition means for acquiring the circuit data, and divides into a plurality of parts. Area dividing means, element detecting means for detecting the circuit element existing in each of the plurality of divided areas generated by the area dividing means, and a plurality of circuit data of the circuit element detected by the element detecting means. A data expanding unit that expands each divided area to generate expanded data, a data sorting unit that sorts the expanded data generated by the data expanding unit into a plurality of divided areas, and a plurality of individually sorted objects Divided area saw
Image data of one whole area
Has and a data merge unit that generates over data, before
The sort data is merged by the data merge means.
Before performing the sorting process with the data sorting means
Is characterized by.

In the data processing apparatus as described above, in the circuit data, area data indicating an existing area is individually set in each of various circuit elements expressed in a hierarchical structure, and the element detecting means is It is also possible to detect the circuit element existing in each of the plurality of divided areas based on the area data.

[0027]

In the data processing device as described above, the image data is used for forming a circuit pattern for each predetermined unit area in the pattern forming device,
The area dividing means can also divide the circuit data into divided areas corresponding to the unit areas of the pattern forming apparatus.

A first pattern forming apparatus of the present invention develops image data by expanding circuit data in which various circuit elements of an integrated circuit are expressed in a hierarchical structure, and uses this image data to form a circuit on a circuit material. A pattern forming apparatus for forming a pattern, comprising: an area dividing means for dividing the circuit data into a plurality of divided areas; and circuit data of a plurality of divided areas divided by the area dividing means. Data expansion means for generating expanded data by
Data sorting means for individually sorting the developed data of the plurality of divided areas generated by the data developing means to generate a plurality of sorted data, and individually sorted processing
Merge the sort data of multiple divided areas into a single
Data merging means for generating image data of the entire area
And sorting by the data merging means
Before merging the data, the data sort means
It is characterized by performing sort processing.

A second pattern forming apparatus of the present invention detects a whole area of the integrated circuit of the circuit data acquired by the structure acquiring means and the circuit data acquired by the structure acquiring means, and divides into a plurality of parts. Area dividing means, element detecting means for detecting the circuit element existing in each of the plurality of divided areas generated by the area dividing means, and a plurality of circuit data of the circuit element detected by the element detecting means. A data expanding unit that expands each divided area to generate expanded data, a data sorting unit that sorts the expanded data generated by the data expanding unit into a plurality of divided areas, and a plurality of individually sorted objects Of divided areas
Image of one whole area by merging the batch data
And a data merging means for generating data ,
Merge processing of the sort data by the data merge means
Before doing so, sort the data with the data sorting means.
It is characterized by.

In the pattern forming apparatus as described above,
In the circuit data, area data indicating an existing area is individually set in each of various circuit elements expressed in a hierarchical structure, and the element detection unit exists in each of the plurality of divided areas by the area data. It is also possible to do so.

In the pattern forming apparatus as described above,
It is also possible that further includes a pattern forming means for forming a circuit pattern on the circuit element in the generated single image data was by the data merge unit.

In the pattern forming apparatus as described above,
The pattern forming means executes formation of the circuit pattern for each predetermined unit area of the image data, and the area dividing means divides the circuit data into divided areas corresponding to the unit areas of the pattern forming means. It is also possible.

The first information storage medium of the present invention is an information storage medium in which computer-readable software is stored, and acquires circuit data in which various circuit elements of an integrated circuit are expressed in a hierarchical structure. A step of dividing the obtained circuit data into a plurality of divided areas, a step of individually developing the divided circuit data of the plurality of divided areas to generate expanded data, and a step of generating the expanded data. A step of individually sorting the expanded data of the plurality of divided areas that have been sorted to generate a plurality of sorted data, and a step of
Merge the sorted data and image one whole area.
And a program for causing the computer to execute a merge processing step for generating data .
When executing the program, the merge processing
Before the sorting process step is executed.
It has a feature.

The second information storage medium of the present invention comprises a step of obtaining circuit data in which various circuit elements of the integrated circuit are expressed in a hierarchical structure, and an entire area of the integrated circuit of the obtained circuit data. And dividing into a plurality of divided regions, detecting the circuit elements present in each of the generated divided regions, and detecting the circuit data of the detected circuit components for each of the divided regions. The step of developing the expanded data to generate expanded data, the step of sorting the generated expanded data into a plurality of divided areas, and the step of individually dividing the plurality of divided areas.
Image of one whole area by merging the batch data
A program for causing the computer to execute a merge processing step for generating data is stored ,
When executing the program, the merge processing step
Characterized in that the sorting step is performed before
I am trying.

In the information storage medium as described above, as the circuit data, area data indicating an existing area is individually set in each of various circuit elements expressed in a hierarchical structure, and a plurality of area data are set by the area data. It is also possible to store a program for causing the computer to execute the step of detecting the circuit element existing in each of the divided areas.

[0037]

In the information storage medium as described above, the image data is used for forming a circuit pattern for each predetermined unit area in the pattern forming apparatus, and the divided area is the unit area of the pattern forming apparatus. It is also possible to correspond to.

Since the data processing apparatus of the present invention has the above-mentioned configuration, in the data processing method, when the structure acquisition means acquires the circuit data of the hierarchical structure, the entire area of the integrated circuit of the circuit data is acquired. The area dividing means detects and divides into a plurality of pieces. The element detecting means detects the circuit element existing in each of the plurality of divided areas by the area data, and the data expanding means expands the circuit data of the detected circuit element for each of the plurality of divided areas to obtain the expanded data. To generate. The expanded data generated in this way is sorted by the data sorting means for each of a plurality of divided areas, and the sorted data of the plurality of divided areas thus sorted is merged by the data merging means to obtain an image of one entire area. Generate data. As a result, image data reflecting the actual circuit pattern of the integrated circuit is generated from the circuit data representing various circuit elements in a hierarchical structure. However, in the data processing method of the data processing device of the present invention, unlike the prior art, the circuit data is divided into a plurality of areas and then individually developed and sorted. For example, even if the data capacity is "N" times as large as the standard, if the data is divided into "N" pieces and sorted in order, the time required for each of the plurality of sort processes is equal to the reference, and the total time required is approximately "reference". Only N times.

In the pattern forming method by the pattern forming apparatus of the present invention, when the structure obtaining means obtains the circuit data of the hierarchical structure, the area dividing means detects the entire area of the integrated circuit of this circuit data and divides it into a plurality of pieces. To do. The element detecting means detects the circuit element existing in each of the plurality of divided areas by the area data, and the data expanding means expands the circuit data of the detected circuit element for each of the plurality of divided areas to obtain the expanded data. To generate. The expanded data generated in this way is sorted by the data sorting means for each of a plurality of divided areas, and the sorted data of the plurality of divided areas thus sorted is merged by the data merging means to obtain an image of one entire area. Generate data. Since the pattern forming means forms a circuit pattern on the circuit material by using one piece of image data thus generated, the circuit pattern of the integrated circuit is formed on the circuit material based on the circuit data representing various circuit elements in a hierarchical structure. To be done. However, unlike the prior art, in the pattern forming method by the pattern forming apparatus of the present invention, the circuit data is divided into a plurality of regions, and then individually developed and sorted. For example,
Even if the data capacity is "N" times the standard, if the data is divided into "N" pieces and sorted in order, the time required for each of the plurality of sort processes is equal to the reference, and the total time required is approximately "N". It only doubles.

The various means referred to in the present invention may be formed so as to realize the functions thereof. For example, dedicated hardware, a computer to which appropriate functions are given by a program, or a computer by an appropriate program. Allows the functions, combinations, etc. realized inside the.

The acquisition of circuit data in the present invention means that the circuit data can be handled. For example, reading of circuit data registered in the memory device and I / F (Interface). Acceptance of circuit data externally input from, acceptance of circuit data input by a keyboard, and the like are permitted.

When the computer reads the program stored in the information storage medium of the present invention and executes the corresponding processing operation, the computer acquires the circuit data of the hierarchical structure and the whole area of the integrated circuit. Is detected and divided into a plurality of regions. The circuit element existing in each of the plurality of divided areas is detected from the area data, and the circuit data of the detected circuit element is expanded for each of the plurality of divided areas to generate expanded data. The expanded data generated in this way is sorted into a plurality of divided areas to generate sorted data, and the sorted data of the divided areas thus sorted is merged to generate image data of one entire area. To generate. In this way, image data that reflects the actual circuit pattern of the integrated circuit is generated from the circuit data that represents various circuit elements in a hierarchical structure. However, in the processing operation of the computer by the program stored in the information storage medium of the present invention, unlike the prior art, the circuit data is divided into a plurality of areas, and then individually expanded and sorted. For example, even if the data capacity is "N" times as large as the standard, if the data is divided into "N" pieces and sorted in order, the time required for each of the plurality of sort processes is equal to the reference, and the total time required is approximately "reference". N "
It only doubles.

The information storage medium referred to in the present invention may be any information storage medium in which programs for causing a computer to execute various processes are stored in advance as software. For example, the information storage medium is fixed to a device including a computer. ROM (Read Only Memory) and HDD (Hard Disc D)
rive), CD (Compact Disc) -ROM or FD (Floppy Di
sc), etc. are allowed.

The computer referred to in the present invention may be any device capable of reading a program consisting of software and executing a corresponding processing operation, for example, a CPU.
(Central Processing Unit)
A device in which various devices such as M, RAM, and I / F are connected as necessary is allowed. Note that causing the computer to execute various operations corresponding to software in the present invention also allows the computer to control the operation of various devices.

[0046]

BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of the present invention will be described below with reference to FIGS. However, the same parts as those of the conventional example described above with respect to the present embodiment use the same names, and detailed description thereof will be omitted.

FIG. 1 is a schematic diagram showing the logical structure of an electronic drawing system which is the pattern forming apparatus of this embodiment.
2 is a schematic vertical sectional front view showing the internal structure of an electronic drawing unit which is a pattern forming device and a pattern forming means, FIG. 3 is a block diagram showing the physical structure of a computer unit which is a data processing device, and FIG. 5 is a schematic diagram showing a detailed logical structure of the drawing system, FIG. 5 is a schematic diagram showing a relationship between hierarchical circuit data and area division, and FIG. 6 is a relationship between circuit data expanded to the lowest order and one division area. FIG. 7 is a schematic diagram showing a state in which circuit data of circuit cells is temporarily stored for each divided area, FIG. 8 is a flowchart showing a main routine of data processing of a computer unit, and FIG. 9 is a circuit element detection process. 4 is a flowchart showing a subroutine of.

As shown in FIGS. 1 and 2, the electronic drawing system 1 of the present embodiment comprises a computer unit 100 which is a data processing device and an electronic drawing unit 200 which is a pattern forming device and a pattern forming means. The units 100 and 200 are connected by a communication cable 400.

As shown in FIG. 2, the electronic drawing unit 200 is provided with a vertically long main body housing 201 which is a closed container, and an electron gun 202 is arranged above the main body housing 201. Below the electron gun 202, a first aperture 203, a shaping deflector 204, a second aperture 205, a reduction lens 206, an objective lens 2
07, a main deflector 208, a sub deflector 209, and the like are arranged, and an xy stage 210, which is a material holding means, is arranged at a position facing the electron gun 202 from below via these.

The xy stage 210 holds a silicon wafer 401, which is a circuit material, movably in horizontal xy directions, and the electron gun 202 uses an energy beam on the surface of the silicon wafer 401 held in this manner. Irradiate an electron beam. Main / sub deflector 208, 209
Scans the electron beam according to the image data externally input from the computer unit 100, so that the circuit pattern is electronically drawn on the surface of the silicon wafer 401.

As shown in FIG. 3, the computer unit 100 is provided with a CPU 101 as a main hardware of a computer, and the CPU 101 is provided with a bus line 102 for ROM 103 and RAM 1.
04, HDD105, FD106 is loaded into FDD (F
D drive) 107, CD loaded with CD-ROM 108
The drive 109, keyboard 110, mouse 111, display 112, communication I / F 113, etc. are connected, and the electronic drawing unit 200 is connected to this communication I / F 113 by a communication cable 400.

In the computer unit 100 of the electronic drawing system 1 of this embodiment, the ROM 103 and the RAM 1
04, HDD105, FD106, CD-ROM108
Etc. correspond to an information storage medium, and programs and data necessary for various operations are stored as software in these.

For example, the control program for causing the CPU 101 to execute various processing operations is the FD 106 or CD-RO.
It is stored in advance in M108. Such software is pre-installed on the HDD 105,
When the electronic drawing system 1 is started, it is copied to the RAM 104 and read by the CPU 101.

In this way, the CPU 101 reads an appropriate program and executes various processing operations,
In the computer unit 100, as shown in FIG.
Structure acquisition means 121, area division means 122, element detection means 123, data expansion means 124, data sorting means 1
25, data merging means 126, etc. are logically provided.

The structure acquisition means 121 is, for example, RAM1.
The CPU 101 operating in accordance with the control program installed in 04 reads out the registration data of the HDD 105 to acquire the circuit data. In this circuit data, various circuit elements of the integrated circuit are expressed in a hierarchical structure as described above, and area data indicating an existing area is individually set in each of such circuit elements.

The area dividing means 122 performs the data processing of the CPU 101 corresponding to the control program installed in the RAM 104, and as shown in FIG.
The whole area of the integrated circuit of the circuit data acquired by 21 is detected and divided into a plurality of areas .

Similarly, by the data processing of the CPU 101 corresponding to the control program installed in the RAM 104, the element detecting means 123 causes the area dividing means 122 to generate a plurality of divisions as shown in FIGS. Circuit elements existing in each of the areas are detected by the area data.

The data expanding means 124 is the element detecting means 1
The circuit data of the circuit element detected by 23 is expanded to generate expanded data for each of the plurality of divided areas, and the data sorting unit 125 uses the expanded data generated by the data expanding unit 124 for each of the divided areas. Sorting is performed to generate sort data.

The data merging means 126 merges the sort data of the plurality of divided areas sorted by the data sorting means 125 in the order of absolute coordinates to generate image data of one whole area, and the image data Data is output from the communication I / F 113 to the electronic drawing unit 200 in a predetermined format by data processing of the CPU 101.

Various means 121-126 for executing various processes as described above are logically connected to various means for temporarily storing various data during the process and as a result of the process. Therefore, the logical structure of the computer unit 100 will be described below with reference to FIG. 4 by clearly showing various means for temporarily storing the various data.

First, the structure analysis means 130 is connected to the structure acquisition means 121 by a logical link, and the storage means 131 to 133 of the cell region, the cell hierarchy, and the element element are connected to the structure analysis means 130. It is connected. The cell area storage means 131 is connected to the area division means 122, and the area division means 122 is also connected to the block size storage means 134 and the area data storage means 135.

The various storage means 131 to 133, 135 are connected to the element detection means 123, and the element detection means 123 is connected to the division element storage means 136 and the division hierarchy storage means 137. These storage means 13
6, 137 are connected to the data expansion means 137 together with the cell area storage means 131.
A development data storage unit 138 is connected to the unit 24.

The expanded data storage means 138 is connected to the data sort means 125, and the data sort means 125 is connected to the data merge means 126 via the sort data storage means 139. The various storage means 131 to 139 described above are, for example, the RAM 104 or the HDD.
A predetermined storage area of an information storage medium such as 105,
Various data are read and written by being specified by the CPU 101.

The structure analysis means 130 is the structure acquisition means 12
The circuit data acquired in 1 is analyzed to extract hierarchical structure data indicating the hierarchical structure of the circuit cells, area data for each circuit cell, and element element data indicating the element element of the circuit cell in the lowermost layer. Therefore, the cell area storage means 131 temporarily stores the area data for each circuit cell, the cell hierarchy storage means 132 temporarily stores the hierarchical structure data, and the element element storage means 133 temporarily stores the element element data.

A block size corresponding to a unit area in which the electronic drawing unit 200 forms a circuit pattern at a time is previously registered in the block size storage means 134 as data, and this block size is divided into area division means 122. Provide data as.

The area dividing means 122 detects the whole area of the integrated circuit of the circuit data from the area data for each circuit cell provided from the cell area storing means 131, and the data is provided from the block size storing means 134. The divided area is divided into a plurality of divided areas, and the area data storage unit 135 temporarily stores the divided area data of the divided areas.

The element detection means 123 includes the area data for each circuit cell temporarily stored in the cell area storage means 131, the hierarchical structure data temporarily stored in the cell hierarchy storage means 132, and the element temporarily stored in the element element storage means 133. The circuit element existing in each of the plurality of divided areas is detected by referring to the element data and the area data of the divided area temporarily stored in the area data storage unit 135.

That is, the area data of the plurality of divided areas and the area data of each circuit cell are made to correspond to each other, and the hierarchical structure data and the element element data are detected for each of the plurality of divided areas.
The divided element storage unit 136 temporarily stores the element element data detected for each of the plurality of divided areas, and the divided hierarchical storage unit 137 temporarily stores the hierarchical structure data of the circuit element detected for each of the plurality of divided areas. .

The data expansion means 124 is area data for each circuit cell temporarily stored in the cell area storage means 131,
With reference to the element element data for each of the plurality of divided areas temporarily stored in the divided element storage unit 136 and the hierarchical structure data for each of the plurality of divided areas temporarily stored in the divided layer storage unit 137, for each of the plurality of divided areas Generate expanded data.

The expanded data storage means 138 temporarily stores the expanded data for each of the plurality of divided areas, and the data sorting means 125 sorts the expanded data for each of the plurality of divided areas to generate sort data. Storage means 1
39 temporarily stores sort data for each of the plurality of divided areas.

The various means as described above are realized by using the hardware such as the communication I / F 113 if necessary, but the main body of the hardware corresponds to the software stored in the information storage medium such as the RAM 104. It is realized by the operation of the CPU 101, which is a computer including ware.

Such software, for example, acquires circuit data having a hierarchical structure, detects the entire area of the integrated circuit of the acquired circuit data, and divides it into a plurality of parts. Detecting circuit elements existing in each of the divided areas by area data, developing circuit data of the detected circuit elements for each of a plurality of divided areas to generate expanded data, and generating the expanded data. Sorting the data into a plurality of divided areas, merging the sorted sorted data of the divided areas to generate image data of one entire area, and outputting the image data in a predetermined format to an external device. It is stored in the information storage medium of the RAM 104 as a control program for causing the CPU 101 to execute processing operations such as outputting. It is.

In the electronic drawing system 1 of the present embodiment having the above-described structure, the image data of the integrated circuit is generated from the circuit data of the hierarchical structure by the computer unit 100 as in the conventional apparatus, and this image data is generated. With the electronic drawing unit 200, the silicon wafer 40
1 to electronically draw a circuit pattern to manufacture an integrated circuit.

In this case, as a data processing method of the computer unit 100, as shown in FIG.
The circuit data of the hierarchical structure is acquired by the CPU 101 reading the registration data of 05 (step T1), and the entire area of the integrated circuit of the circuit data thus acquired is detected and divided into a plurality of parts (step T2). ).

An unprocessed one is selected from the plurality of divided areas (step T3), and the circuit element existing in the selected divided area is detected from the area data (step T3).
4). More specifically, when detecting a circuit element existing in the thus selected divided area, as shown in FIG.
The area data X of the selected divided area is detected (step E1), and the processing hierarchy is initially set to the highest level (step E2).

Next, the area data of the circuit cell existing in the set processing hierarchy is compared with the area data X, and the circuit cell Y containing the area data X in the processing hierarchy is detected.
(Step E3). When the detection of this circuit cell is completed (step E4), it is confirmed that the processing hierarchy is not the lowest (step E5), and if this is confirmed, the processing hierarchy is lowered by one step (step E6).

When the circuit cells Y including the area data X are detected for all the layers as described above, finally, the element element including the area data X is detected from the lowest circuit cell Y (step E7). ), Data of this element element is acquired together with the hierarchical structure (step E8).

Since the circuit data of the circuit element existing in the selected divided area is detected, the circuit data of this circuit element is expanded for each of the divided areas as shown in FIG. To generate expanded data (Step T
5) Then, the expanded data thus generated is sorted for each of a plurality of divided areas (step T6).

When the processing operations as described above are sequentially executed in the plurality of divided areas and the expansion processing and the sorting processing are completed in all of the plurality of divided areas (step T7), the plurality of divided areas subjected to the sorting processing. The sort data of 1 is merged to generate image data of one entire area (step T8).

Since one piece of image data generated in this way is externally output from the computer unit 100 to the electronic drawing unit 200 (step T9), this electronic drawing unit 200 uses the externally input image data as the silicon wafer 401. A circuit pattern is formed on.

In the electronic drawing system 1 of the present embodiment,
When an integrated circuit device is manufactured by electronically drawing the circuit pattern of the integrated circuit on the silicon wafer 401 based on the circuit data expressing various circuit elements in a hierarchical structure as described above, the circuit data is divided into a plurality of areas. After processing, they are individually expanded and sorted.

Therefore, since it is not necessary to collectively sort the entire large-capacity circuit data, the processing load can be reduced and the processing speed can be improved, and the RAM 104 and the HDD 105 for temporarily storing the expanded data. It is also possible to save the capacity of the data memory such as.

In the electronic drawing system 1 of this embodiment,
The circuit data is divided into a plurality of divided areas, and the circuit data is sorted in order for each of the divided areas. For example, when data having a capacity of “N” times the standard is divided into “N” pieces and sorted in order, the time required for each of the plurality of sort processes is equal to the reference, and the total time required is omitted from the reference. Only "N" times.

When the data having the capacity of “N” times the standard is collectively sorted by the conventional method, the required time is “N · lo”.
Since it becomes gN "times, the electronic drawing system 1 according to the present embodiment can complete the sorting process in a time required for the conventional" logN ". The dividing process and the merging process are actually added. Therefore, the processing time is not simply divided by 1 of the conventional "logN", but if the divided area is proper, the processing time can be certainly shortened as compared with the conventional case.

For example, when the present inventor actually prototyped the computer unit 100 as described above and conducted an experiment with appropriate circuit data, the time required from division to merging was found to be one half of the conventional sorting processing. It has been confirmed that it is about one-third, and the used capacity of the RAM 104 and the HDD 105 is about one-half to one-fourth that of the conventional one.

The circuit data from the HDD 105 is RA
When copying to the work area of M104 and executing various processes and temporarily storing the image data generated by this and erasing the circuit data, the HDD105 and RA
Although the used capacity with the M104 has a relation of barter, for example, by properly setting the divided areas, the HDD 105 and the R
It is also possible to reduce the used capacity of both the AM 104 and the conventional one to a fraction.

The present invention is not limited to the above embodiment, and various modifications are allowed without departing from the scope of the invention. For example, in the above embodiment, the image data is generated from the circuit data to form the circuit pattern, but such image data can be used for verification instead of forming the circuit pattern.

In the above embodiment, the electronic drawing unit 200 electronically draws a circuit pattern on the silicon wafer 401 with the image data generated from the circuit data by the computer unit 100 to directly form an integrated circuit. However, it is also possible to form such a circuit pattern on a mask substrate that is a circuit material to manufacture a photomask instead of an integrated circuit, and it is also possible to form the circuit pattern by optical scanning instead of electronic drawing. Is.

Further, in the above embodiment, the FD 106 and the CD-ROM 108 are exemplified as the information storage medium which can be attached to and detached from the computer unit 100. However, for example, a large amount of image data is transferred from the computer unit 100 to the electronic drawing unit 200 offline. In such a case, a large-capacity removable and rewritable information storage medium such as MT (Magnetic Tape) can be used.

Further, in the above embodiment, the computer unit 100 exemplifies that the sort data generated for each of a plurality of divided areas from one circuit data is merged into one and then transferred to the electronic drawing unit 200. However, if the electronic drawing unit 200 sets the divided area data in the computer unit 100 corresponding to the unit area in which the circuit pattern is formed at one time, the computer unit 100 can obtain the sort data for each of the divided areas. It is possible to sequentially supply the electronic drawing units 200 without merging.

Further, in the above embodiment, various means are logically realized as various functions of the computer unit 100 by operating the CPU 101 according to the control program stored in the RAM 104 or the like as software. However, each of these various functions can be formed as unique hardware, and a part of the functions can be stored as software in the RAM 104 or the like and a part of the functions can be formed as hardware.

In the above embodiment, the software preinstalled in the HDD 105 from the CD-ROM 108 or the like is RA when the computer unit 100 is started.
It is assumed that the CPU 101 reads the software copied in the M104 and stored in the RAM 104 in this way, but the CPU 101 may use the software stored in the HDD 105 or the ROM 10 may be used.
It is also possible to store fixedly in No. 3 in advance.

Further, the software is stored in the FD 106 or the CD-ROM 108, which is an information storage medium that can be handled as a single unit, and is stored in the HDD 105 or R from the FD 106 or the like.
The software can be installed in the AM 104, but the CPU 101 can directly read the software from the FD 106 or the like and execute the processing operation without executing such installation.

That is, when various means of the computer unit 100 are implemented by software, the software may be in a state in which the CPU 101 can read the software and execute the corresponding operation. Further, it is possible to form a control program that realizes various means as described above by combining a plurality of software. In that case, in order to realize the computer unit 100 in the information storage medium that is a single product. You only need to store the minimum required software of.

For example, a CD is installed in a computer unit 100 in which an existing operating system is installed.
-When the application software is provided by an information storage medium such as the ROM 108, the software that realizes the above-mentioned various means is realized by a combination of the application software and the operating system.
The software that depends on the operating system can be omitted from the application software of the information storage medium.

The method of supplying the software described in the information storage medium to the CPU 101 is not limited to loading the information storage medium directly into the computer unit 100. For example, it is also possible to store the software as described above in the information storage medium of the host computer, connect the host computer to the terminal computer through the communication network, and supply the software from the host computer to the terminal computer by data communication. is there.

In the case as described above, it is possible for the terminal computer to execute the stand-alone processing operation in the state where the software is downloaded to the information storage medium of its own, but it is possible to execute the stand-alone processing operation with the host computer without downloading the software. It is also possible to execute the processing operation by data communication. In this case, the entire system in which the host computer and the terminal computer are connected by the communication network corresponds to the data processing device of the present invention.

[0098]

Since the present invention is constructed as described above, it has the following effects.

In the data processing method by the data processing device of the present invention, the structure obtaining means obtains the circuit data of the hierarchical structure, and the area dividing means detects the entire area of the integrated circuit of the circuit data and divides it into a plurality of pieces. Then, the element detecting means detects the circuit element existing in each of the plurality of divided areas by the area data, and the data expanding means expands the circuit data of the detected circuit element for each of the plurality of divided areas. Data is generated, the expanded data generated in this way is sorted by the data sorting means for each of a plurality of divided areas, and the sorted data of the plurality of divided areas thus sorted is merged by the data merging means. By generating the image data of one whole area, the image data can be generated from the circuit data of the hierarchical structure as before. Since the time required for sorting expanded data and the data capacity required for temporary storage can be reduced to a fraction of the conventional value, a large amount of data memory is not required The image data can be quickly generated from the circuit data.

In the pattern forming method by the pattern forming apparatus of the present invention, the structure obtaining means obtains the circuit data of the hierarchical structure, and the area dividing means detects the entire area of the integrated circuit of this circuit data and divides it into a plurality of pieces. Then, the element detecting means detects the circuit element existing in each of the plurality of divided areas by the area data, and the data expanding means expands the circuit data of the detected circuit element for each of the plurality of divided areas. Data is generated, the expanded data generated in this way is sorted by the data sorting means for each of a plurality of divided areas, and the sorted data of the plurality of divided areas thus sorted is merged by the data merging means. Image data of one whole area is generated, and the pattern forming means forms a circuit pattern on the circuit material with one image data thus generated. By doing so, it is possible to generate image data from circuit data having a hierarchical structure in the same manner as in the past to form a circuit pattern. However, in the processing process, the time required for sorting the expanded data and temporary storage Since the data capacity can be reduced to a fraction of the conventional one, there is no need for a huge amount of data memory,
Image data can be quickly generated from a large amount of circuit data.

When the computer reads the program stored in the information storage medium of the present invention and executes the corresponding processing operation, the computer acquires the circuit data of the hierarchical structure, and the entire area of the integrated circuit. Is detected and divided into a plurality of divided areas, the circuit element existing in each of the divided areas is detected by the area data, and the circuit data of the detected circuit element is expanded and expanded for each of the divided areas. Data is generated, the expanded data generated in this way is sorted for each of a plurality of divided areas to generate sort data, and the sorted data of the plurality of divided areas subjected to the sort processing is merged to form one whole. By generating the image data of the area, it is possible to generate the image data from the circuit data of the hierarchical structure as in the conventional method. Since the time required for sorting open data and the data capacity required for temporary storage can be reduced to a fraction of the conventional one, a large-capacity circuit can be realized without the need for a huge amount of data memory. Image data can be quickly generated from the data.

[Brief description of drawings]

FIG. 1 is a schematic diagram showing a logical structure of an electronic drawing system which is an embodiment of a pattern forming apparatus of the present invention.

FIG. 2 is a schematic vertical sectional front view showing an internal structure of an electronic drawing unit that is a pattern forming apparatus and a pattern forming unit.

FIG. 3 is a block diagram showing a physical structure of a computer unit which is a data processing device.

FIG. 4 is a schematic diagram showing a logical structure of a more detailed electronic drawing system.

FIG. 5 is a schematic diagram showing a relationship between circuit data having a hierarchical structure and area division.

FIG. 6 is a schematic diagram showing the relationship between the circuit data expanded to the lowest order and one divided area.

FIG. 7 is a schematic diagram showing a state in which circuit data of a circuit cell is temporarily stored for each divided area.

FIG. 8 is a flowchart showing a main routine of data processing of a computer unit.

FIG. 9 is a flowchart showing a subroutine showing a circuit element detection process subroutine.

FIG. 10 is a schematic diagram showing a circuit pattern of an integrated circuit device.

FIG. 11 is a schematic diagram showing the internal structure of one circuit element.

FIG. 12 is a schematic diagram showing a data structure of circuit data.

FIG. 13 is a schematic diagram showing a conventional data processing method.

[Explanation of symbols]

1 Electronic drawing system 100 which is an electronic drawing device Computer unit 101 which is a data processing device CPU 103 which is a computer ROM 104 which is an information storage medium RAM 105 which is an information storage medium HDD 106 which is an information storage medium FD which is an information storage medium 108 CD-ROM as information storage medium 121 Structure acquisition means 122 Area dividing means 123 Element detecting means 124 Data expanding means 125 Data sorting means 126 Data merging means 200 Electronic drawing unit 401 which is a pattern forming device and a pattern forming means 401 Circuit material Is a silicon wafer

─────────────────────────────────────────────────── ─── Continuation of the front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) G06F 17/50 G03F 1/08 H01L 21/027-21/033

Claims (22)

(57) [Claims] 1. Various circuit elements of an integrated circuit have a hierarchical structure.
The image data is processed by expanding the circuit data that is expressed.
A data processing method for generating data Dividing the circuit data into a plurality of divided areasDivision
Processing step, The circuit data of a plurality of divided areas that have been subjected to this division processing are individually
To generate the expanded dataDeployment processing step
When, The expanded data of the generated divided areas are individually
Process to generate multiple sort dataSort process
Steps, Sort data of multiple divided areas that are individually sorted
Image data of one whole area by merging
And a merge processing step to Before the merge processing step, the sort processing step
Is characterized by having Data processing method. 2. Various circuit elements of an integrated circuit have a hierarchical structure.
The image data is processed by expanding the circuit data that is expressed.
A data processing method for generating data Get the circuit dataData acquisition step to The entire area of this acquired circuit data is detected and
Divided intoDivision processing step to Before existing in each of the plurality of divided regions
Detect circuit elementsDetection step to The circuit data of the detected circuit element is divided into a plurality of divided areas.
Generate expansion data by performing expansion processing for eachExpansion processing
And The expanded data of the generated divided areas are individually
Process to generate multiple sort dataSort process
With steps,Sort data of multiple divided areas that are individually sorted
Image data of one whole area by merging
And a merge processing step to There is a sort processing step before the merge processing step.
Characterized by Data processing method. 3. The circuit data is individually set with area data indicating an existing area in each of various circuit elements expressed in a hierarchical structure, and in the detection step, a plurality of divisions are made by the area data. this detecting the circuit elements present in each of the regions
The data processing method according to claim 2, wherein 4. The image data is a pattern forming device.
It is used to form a circuit pattern for each predetermined unit area in
The divided area corresponds to the unit area of the pattern forming apparatus.
Data processing according to any one of claims 1 to 3,
Method. 5. Various circuit elements of an integrated circuit have a hierarchical structure.
The image data is processed by expanding the circuit data that is expressed.
A data processing device for generating data, which is for a region for dividing the circuit data into a plurality of divided regions
A split unit, a plurality of divided processed by the region dividing means divided areas
Expand the circuit data individually to generate expanded data
Data expansion means and a plurality of divided areas generated by the data expansion means
Open data can be sorted individually to obtain multiple sort data.
Data sort means to generate and sort data of multiple divided areas that have been individually sorted
Image data of one whole area by merging
And a data merging means for generating the merged data, and the data merging means merges the sort data.
Before doing so, sort the data with the data sorting means.
And a data processing device. 6. Various circuit elements of an integrated circuit have a hierarchical structure.
The image data is processed by expanding the circuit data that is expressed.
A data processing device for generating data, the structure acquiring means for acquiring the circuit data, and an integrated circuit of the circuit data acquired by the structure acquiring means.
Area dividing method that detects the entire area of the
And a plurality of divided areas generated by the area dividing means
Element detecting means for detecting the circuit element existing in the, and circuit data of the circuit element detected by the element detecting means
Expanded data for each divided area to generate expanded data
Data expansion means and a plurality of expansion data generated by the data expansion means.
Data sorting means for sorting processing for each divided area, and sorting data for a plurality of divided areas that have been individually sorted
Image data of one whole area by merging
And a data merging means for generating the merged data, and the data merging means merges the sort data.
Before doing so, sort the data with the data sorting means.
And a data processing device. 7. The circuit data is expressed in a hierarchical structure.
Area data indicating the existence area of each of the various circuit elements
The individual element is set individually, and the element detecting means uses a plurality of divided areas according to the area data.
7. The circuit element present in each of the
Data processing equipment. 8. The image data is a pattern forming device.
It is used to form a circuit pattern for each predetermined unit area in
The area dividing means is a unit area of the pattern forming apparatus.
A method of dividing circuit data into divided areas corresponding to
5. The data processing device according to any one of 5 to 7. 9. Various circuit elements of an integrated circuit have a hierarchical structure.
The image data is processed by expanding the circuit data that is expressed.
Circuit pattern, and create a circuit pattern on the circuit material with this image data.
A pattern forming method for forming a pattern, wherein the circuit data is divided into a plurality of divided areas.
Processing step and the circuit data of the plurality of divided areas that have been divided.
Expansion processing step to generate expansion data by performing expansion processing
And the expanded data of the generated divided areas are individually
Sorting process to generate multiple sort data
Sort data of steps and multiple divided areas that are individually sorted
Image data of one whole area by merging
A merge processing step to perform the sort processing step before the merge processing step.
Patterning how to, comprising a. 10.Hierarchical structure of various circuit elements of integrated circuit
The circuit data represented by
Circuit data, and use this image data to
It is a pattern forming method that forms turns.
hand, A data acquisition step of acquiring the circuit data, The entire area of this acquired circuit data is detected and
A division processing step for performing division processing into Before existing in each of the plurality of divided regions
A detection step of detecting the circuit elements, The circuit data of the detected circuit element is divided into a plurality of divided areas.
The expansion process step that generates expansion data for each
And The expanded data of the generated divided areas are individually
Sorting process to generate multiple sort data
Steps, Sort data of multiple divided areas that are individually sorted
Image data of one whole area by merging
And a merge processing step to Before the merge processing step, the sort processing step
A method for forming a pattern, comprising: 11. The circuit data is expressed in a hierarchical structure.
The area data indicating the existing area of each of the various circuit elements
Data is set individually, and a plurality of
Of the circuit elements present in each of the divided areas of
11. The pattern forming method according to claim 10, wherein: 12. Generated in the merge processing step
A circuit pattern is formed on the circuit material with the image data
12. The method according to any one of claims 9 to 11, characterized in that
Pattern forming method. 13. The circuit pattern is formed by the image formation.
13. The divided area is executed for each predetermined unit area, and the divided area corresponds to the unit area.
The described pattern forming method. 14. A hierarchical structure of various circuit elements of an integrated circuit.
The circuit data represented by
Circuit data, and use this image data to
A pattern forming device for forming a turn, for an area for dividing the circuit data into a plurality of divided areas.
A split unit, a plurality of divided processed by the region dividing means divided areas
Expand the circuit data individually to generate expanded data
Data expansion means and a plurality of divided areas generated by the data expansion means
Open data can be sorted individually to obtain multiple sort data.
Data sort means to generate and sort data of multiple divided areas that have been individually sorted
Image data of one whole area by merging
Comprising a data merge means for forming, and merging the sorted data in said data merging means
Before doing so, sort the data with the data sorting means.
And a pattern forming device. 15. A hierarchical structure of various circuit elements of an integrated circuit.
The circuit data represented by
Circuit data, and use this image data to
A pattern forming apparatus for forming a turn, comprising: a structure acquisition unit for acquiring the circuit data; and an integrated circuit of the circuit data acquired by the structure acquisition unit.
Area dividing method that detects the entire area of the
And a plurality of divided areas generated by the area dividing means
Element detecting means for detecting the circuit element existing in the, and circuit data of the circuit element detected by the element detecting means
Expanded data for each divided area to generate expanded data
Data expansion means and a plurality of expansion data generated by the data expansion means.
Data sorting means for sorting processing for each divided area, and sorting data for a plurality of divided areas that have been individually sorted
Image data of one whole area by merging
And a data merging means for generating the merged data, and the data merging means merges the sort data.
Before you, the child that is responsible for sort processing by the Detaso over door means
And a pattern forming device. 16. The circuit data is expressed in a hierarchical structure.
The area data indicating the existing area of each of the various circuit elements
Data is set individually, and the element detecting means is configured to divide the area data into a plurality of divided areas.
16. The circuit element according to claim 15, wherein the circuit element present in each of
Pattern forming device. 17. The data merging means
A circuit pattern is formed on the circuit material with one image data
It is characterized by further comprising pattern forming means
The putter according to any one of claims 14 to 16, which is used as a signature.
Forming device. 18. The pattern forming means is the circuit pattern.
A turn is formed for each predetermined unit area of the image data.
And the area dividing means is a unit area of the pattern forming means.
A method of dividing circuit data into divided areas corresponding to
17. The pattern forming apparatus according to item 17. 19.Computer-readable software
In the information storage medium where a is stored, Various circuit elements of an integrated circuit are represented in a hierarchical structure
A data acquisition step of acquiring circuit data, The acquired circuit data is divided into multiple divided areas.
Division processing step to The circuit data of a plurality of divided areas that have been subjected to this division processing are individually
Expansion processing step to generate expansion data by performing expansion processing
When, The expanded data of the generated divided areas are individually
Sorting process to generate multiple sort data
Steps, Sort data of multiple divided areas that are individually sorted
Image data of one whole area by merging
The merge processing step to be performed on the computer
The program for When executing the program, the merge processing step
Characterized in that the sorting step is performed before
Information storage medium. 20.Computer-readable software
In the information storage medium where a is stored, Various circuit elements of an integrated circuit are represented in a hierarchical structure
A data acquisition step of acquiring circuit data, The entire area of the integrated circuit of this acquired circuit data is detected.
A division processing step of outputting and dividing into a plurality of pieces, The number of times existing in each of the generated plurality of divided areas
A detection step of detecting a road element, The circuit data of the detected circuit element is divided into a plurality of divided areas.
The expansion process step that generates expansion data for each
And The generated expanded data is sorted for each of the divided areas.
Sort processing step for Sort data of multiple divided areas that are individually sorted
Image data of one whole area by merging
The merge processing step to be performed on the computer
The program for When executing the program, the merge processing step
Characterized in that the sorting step is performed before
Information storage medium. 21. The circuit data is expressed in a hierarchical structure.
The area data indicating the existing area of each of the various circuit elements
Data is set individually, and it exists in each of a plurality of divided areas by this area data.
A step of detecting the circuit element in the computer;
The program for executing the program is also stored.
0 information storage medium. 22. The image data is a pattern forming device.
Used to form a circuit pattern for each predetermined unit area
The divided area corresponds to the unit area of the pattern forming apparatus.
The information record according to any one of claims 19 to 21
Storage medium.