JP3468762B2 - Data loading method and apparatus - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data loading method suitable for loading a cache memory in a control device having a cache memory.

[0002]

2. Description of the Related Art A magnetic disk device or the like used as an external storage device has an advantage that a large storage capacity can be realized at a relatively low cost. However, there is a limit to the improvement of the access speed in recording and reproducing data due to the waiting of rotation of the magnetic disk as a storage medium and the seek operation of the head.

For this reason, an electronic computer system having a magnetic disk device or the like as an external storage device is as follows. A cache memory including a semiconductor memory or the like that can be accessed faster than the magnetic disk device is provided in the magnetic disk control device or the like that is interposed between the central processing unit and the magnetic disk device and controls the exchange of data between them. . Then, by storing a part of the data stored in the magnetic disk device in this cache memory and responding to the access from the central processing unit, a large difference in operating speed between the magnetic disk device and the central processing unit is achieved. Alleviate. In this way, it is general to improve the efficiency of data exchange between the magnetic disk device and the central processing unit.

In that case, the probability that the target data accessed from the central processing unit exists in the cache memory,
That is, it is important to increase the hit rate as much as possible from the viewpoint of making the cache memory function more effectively. Therefore, various techniques such as the following have been conventionally proposed.

For example, in "Electronic Information and Communication Handbook" (1988) published by Ohmsha, data loading to a cache memory is performed in track units.

[0006] Further, for example, JP-A-55-15464
The technique disclosed in Japanese Patent No. 8 is as follows. The storage area of the magnetic disk device is divided into a plurality of areas. Different operation modes are preset in accordance with the respective divided storage areas. The operation mode is switched to a storage area designated by an input / output command from the central processing unit. As described above, it is intended to improve the hit rate.

Further, for example, Japanese Patent Laid-Open No. 60-14360.
The technique described in the publication is as follows. Statistical data such as hits / misses is collected by the disk controller. Transfer the collected statistical data to the central processing unit. Based on these statistical data, the operator or system administrator determines whether or not the current usage state of the cache memory is optimum. Based on the determination result, the range of data loaded from the magnetic disk device onto the cache memory, that is, the cache target range is appropriately controlled. In this way, the data transfer efficiency between the central processing unit and the magnetic disk drive is improved.

Furthermore, IPSJ, 29th National Convention, pp. In 169-170, the disk controller recognizes the sequential access, and after the sequential access to a track is completed,
A method has been proposed in which this track is treated as data that is most easily erased from the cache memory.

[0009]

However, the above
In the "Electronic Information and Communication Handbook", this does not matter if the overhead of loading is large and the probability that the access target data exists in the cache is high, but if the existence probability is low, the performance will deteriorate rather by the introduction of the cache. There was a possibility.

To address this, a method of loading only the record to be accessed into the cache is conceivable. Generally, however, the record length within a track is variable, and the management on a track-by-track basis is the basis. A different loading method is required.

Further, in Japanese Patent Laid-Open No. 55-154648, the disk control unit instructs the access characteristic from the central processing unit and selects the loading method (operation mode) according to the access characteristic. Therefore, a burden is placed on the central processing unit. Further, when the central processing unit cannot fully recognize the access characteristics, it is impossible to select an appropriate loading method for the cache memory.

Further, since the operation mode is fixed with respect to each of the divided storage areas, if the access pattern from the central processing unit to the disk device in the same storage area changes with time, the cache memory may be changed. There is a problem that the utilization efficiency cannot be optimally maintained.

That is, it becomes difficult to handle files provided in the same storage area, for example, when random access is mainly used for online processing and sequential access is mainly used for batch processing.

In Japanese Patent Laid-Open No. 60-14360, it is an operator or system administrator who judges the statistical information obtained in the magnetic disk controller. Therefore,
When the access pattern from the central processing unit to the magnetic disk unit differs depending on the business, the cache target range (the range of data to be loaded in the cache memory) can be optimally controlled momentarily according to the business to be executed. The problem is that it is virtually impossible.

Further, in the paper of the Information Processing Society of Japan, the sequential access, which is a typical access pattern to the disk device, is recognized. As a result of the recognition, the accessed track is controlled to be most easily ejected from the cache, and the loading method is not particularly selected.

An object of the present invention is to provide a loading method capable of reducing the loading overhead based on a track-unit management method when the records constituting the tracks of the magnetic disk have a variable length. is there.

Another object of the present invention is to provide a loading method in a disk control device for grasping the access characteristics of each I / O request and, as a result, improving the hit rate and reducing the loading overhead. It is in.

[0018]

The object of the present invention is achieved as follows. The disk control device is connected to the disk device and the central processing unit, and has a cache memory having a physical area on the disk device as a cache management unit (cache memory management unit). When the data in the cache management unit including the area to be accessed from the central processing unit does not exist in the cache memory at all, only the data in the area to be accessed from the central processing unit is loaded into the cache memory. Perform initial loading. After that, when data other than the data already stored in the cache memory is accessed in the data in this cache management unit, data other than the data stored in the cache memory in this cache management unit is accessed. This is achieved by a data loading method characterized by additionally loading data into the cache memory.

Further, another object of the present invention is achieved as follows.

I / O requests are classified into sequential access and other I / O requests. With sequential access, it is easy to understand the access characteristics and it is easy to determine an efficient loading method.

When the sequential access is recognized, a plurality of tracks are prefetched and loaded from the currently accessed track.

When it is recognized that the I / O request is not a sequential access, a portion to be accessed from the central processing unit while the cache management unit (usually a track) containing the data to be accessed by this input / output request stays in the cache memory. Prediction is performed based on the statistical information, and only this part is loaded, so that the hit rate and the reduction of the loading are balanced.

[0023]

BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a conceptual diagram for explaining the operation of an example of a cache control method which is an embodiment of the present invention. Figure 2
FIG. 3 is a block diagram showing a configuration of an example of an information processing system to which this cache control method is applied.

First, the outline of the configuration of the information processing system in this embodiment will be described with reference to FIG.

For example, a central processing unit (Central Processes) forming a part of a general-purpose electronic computer or the like.
disk unit 3 (control unit) that controls the exchange of data and commands between the Sing Unit 1 (sometimes called a host system) and the magnetic disk unit 2 as an external storage device. Is provided.

Although one disk device 2 is shown in FIG. 2, generally one disk controller is connected.

The central processing unit 1 is provided with a channel device 11 for controlling the exchange of data and commands between the central processing unit 1 and the outside.

On the other hand, the disk controller 3 is provided with a channel interface controller 31 and a device interface controller 32, which exchanges data and commands between the channel device 11 and the disk controller 3, respectively. Disk controller 3
Is in charge of exchanging data between the disk and the magnetic disk device 2.

Further, between the channel interface control unit 31 and the device interface control unit 32, a processor 33 for controlling them and a control memory 34 in which a control program of the processor 33 and the like are stored are provided. .

Further, the channel interface controller 3
1 and the device interface control unit 32 are connected by a data path 35.

A cache memory 36 made up of a semiconductor memory which operates at a much higher speed than that of the magnetic disk device 2, for example, is provided in a part of the data path 35.

Then, of the data stored in the magnetic disk device 2, data which is highly likely to be accessed from the central processing unit 1 via the upper channel device 11 is copied in advance, and this cache memory 36 is used. By responding to an access request from the upper-level central processing unit 1 side by the data stored in the high-speed channel unit 11
The efficiency of data transmission / reception between the disk side and the slow-moving magnetic disk device 2 is improved.

Further, in the data path 35, a data buffer 37 is provided on the side closer to the device interface control unit 32 than the cache memory 36, and the device interface control unit 32, the cache memory 36 and the channel interface control are provided. The data exchanged with the unit 31 and the like is temporarily stored.

The operations of the cache memory 36 and the data buffer 37 are controlled by the microprocessor 33.

On the other hand, in the magnetic disk device 2, as shown in FIG. 4, a plurality of tracks 22 are provided concentrically on both sides of each of a plurality of magnetic disks 21 which are storage media, and each track 22 is provided. As shown in FIG. 3, the track 22 stores a plurality of records, which is a kind of data recording unit.

Further, on both surfaces of each magnetic disk 21, the magnetic disks 21 are simultaneously moved in the same radial direction in the same direction with the distances from the center of rotation of the magnetic disks 21 being equal to each other, and onto the target track. A plurality of heads (not shown) for performing the positioning operation, that is, the seek operation are arranged to face each other, and the recording / reproducing operation of the data such as the record on an arbitrary track 22 is performed via the heads (not shown).

Furthermore, without displacing the plurality of heads in the radial direction of the magnetic disk 21, that is, at the same distance from the center of rotation, the seek operation is performed at a high speed without performing a seek operation that takes a long time. A cylinder 23 is composed of a group of tracks 22 that can be continuously accessed.

The access to any record from the side of the upper central processing unit 1 is performed by designating the number of the cylinder 23, the head number (track number) (not shown) and the record number. is there.

In this case, as shown in FIG. 1, the cache memory 36 is provided with a plurality of track slots 361 to 367, which respectively correspond to arbitrary some of the plurality of tracks 22 in the magnetic disk device 2. There is. The data such as the record R stored in any track 22 of the magnetic disk device 2 is copied (loaded) into these track slots 361 to 367 at any time in a recording format equivalent to the case where the data is stored in that track 22. .

As a result, the channel device 11 can perform high-speed access when the target data exists in the cache memory 36 at the time of the access.

Further, these plural track slots 361 to 367 ... Inside the cache memory 36.
Are managed by the cache memory management table 4.

The cache management table 4 is provided with a plurality of entries 41 corresponding to individual track slots. In each entry 41, storage position information (cylinder number, track number, etc.) not shown in the magnetic disk 21 of the track 22 from which the data stored in each track slot is copied, and the track slot information in the cache memory 36 are stored. A pointer (not shown) indicating the storage position is recorded.

Further, each entry 41, that is, each track slot belonging to each entry 41 is stored in the cache management table 4 by the LRU method (Least method).
It is managed by "Recently Used low".

That is, when there is a request from the central processing unit 1 to access predetermined data in the magnetic disk unit 2 via the channel unit 11, first, the cache management table 4 is searched and stored in the cache memory 36. It is checked whether or not the target data is available. When the target data exists (hereinafter referred to as a hit), high-speed access using the data in the cache memory 36 becomes possible. On the other hand, when the target data does not exist (hereinafter referred to as a mistake), the magnetic disk device 2 is directly accessed.

In the case of this miss, for example, the data read from the magnetic disk device 2 to the channel device 11 is simultaneously copied to the cache memory 36 to prepare for the next access. During this copying, the track slot to be released is selected. A plurality of track slots 361 to 3 provided in the cache memory 36
Of 67, the one accessed at the oldest time, that is, the one corresponding to the entry 41 having the lowest rank (OUT side) in the LRU management of the cache management table 4 is selected. An operation is performed to position the entry 41 corresponding to the copied track slot at the highest level (IN side) of LRU management.

That is, since recently accessed data is highly likely to be accessed next, it is held in the cache memory 36 as long as possible. The track slot in which the data accessed at the oldest point in time is stored is opened for copying new data. In this way, the hit rate is improved.

In this embodiment, there are at least the following two types of cache operation modes that define the method of loading desired data from the magnetic disk device 2 to the cache memory 36 in the case of a mistake as described above. It is provided. There are loading mode and record mode.

As shown in FIG. 3, when an arbitrary record R _n among a plurality of records stored in an arbitrary track 22 in the magnetic disk drive 2 is accessed, the record R _n is recorded after the record R _n ( It is considered that there is a high probability of access to records stored in (not necessarily consecutive). All the records from the record R _{n to} the end of the track are copied to a predetermined track slot of the cache memory 36. This is the loading mode. The record mode is a mode in which only the relevant record R _p that has been accessed is copied from the viewpoint of minimizing the required time for copying, the occupied time of the data path 35, and the like.

Each of the plurality of entries 41 of the cache management table 4 described above is constructed as follows. As shown in FIG. 1, a counter 41a that is incremented according to a predetermined condition to be described later when accessing a track slot belonging to the entry 41 and mode identification information 41b that identifies the current cache operation mode in the track slot. Each entry 41 is configured to be recorded.

Further, in the case of the present embodiment, the above-mentioned cylinder 23 including a group of tracks 22 (track slots) equidistant from the center of rotation in the magnetic disk 21.
A cylinder statistical information table 5 having a plurality of entries 51 corresponding to each of the above is provided. The cache operation mode in each track slot is managed in this cylinder unit.

That is, in each entry 51 of the cylinder statistical information table 5, the mode identification information 51a for recording the current cache operation mode of the cylinder 23 corresponding to the entry 51 and the total number of accesses to the cylinder 23 are stored. Recorded access count recording unit 51
b, a loading mode counter 51c that is incremented by +1 based on a value of the counter 41a in the cache management table 4, and the like, and a record mode counter 51d.

In the present embodiment, the above-described cache operation is performed at any time in units of individual cylinders 23 depending on the ratio of the value of the access count recording section 51b and the loading mode counter 51c or the record mode counter 51d. The operation of switching the mode is automatically performed.

An example of the operation of the cache control method of this embodiment will be described below with reference to FIG.

The central processing unit 1 instructs the disk control unit 3 via the channel unit 11 the cylinder number, head number (track number), record number, etc., and requests access to the magnetic disk unit 2. In response to this request, the processing of FIG. 5 starts.

The disk controller 3 increments the access count recording section 51b of the corresponding cylinder number CYL # in the cylinder statistical information table 5 by 1 (step 60). next,
The cache operation mode of this cylinder is determined (step 61).

The case of the loading mode will be described. The cache memory 36 is searched by the designated cylinder number, track number, etc., and a target record is searched (step 62). When the target record is not found (step 63), the following processing is performed.

The track slot for loading the target record is released (step 64). The release of the track slot will be described later. The subsequent record R _{m + 1} , R _{m + 2} following the target record R _m requested by the central processing unit 1 is loaded (step 6).
6). This loading is realized by loading from the track 22 of the corresponding cylinder number and track number of the magnetic disk device 2 into a predetermined track slot 362 managed by the LRU method. At the same time as this loading or after storing in the track slot, the requested record R _m is sent to the channel device 11
(Step 67). The mode identification information 41b of the corresponding entry 41 of the cache management table 4 indicates the loading mode (step 68). Cache management table 4 corresponding to the track slot
The initial value 1 is set in the counter 41a of the corresponding entry 41 (step 69).

Then, thereafter, the track slot 36 concerned
If there is a request for access to subsequent records R _{m + 1} and R _{m + 2} in ₂ , the records R _{m + 1} and R _{m + 2} can be accessed at high speed because they are held in the cache (step 70). In this case, the disk controller 3
Is the counter 41a of the entry 41 corresponding to the track slot 362 in the cache management table 4.
Is incremented by 1 (step 71).

Therefore, the track slot 362 currently in the loading mode is once in the leading record R _m that triggered the loading and 1 in the trailing record R _{m + 2} .
The value of the counter 41a of the cache management table 4 becomes 2 because the access has been made twice in total.

That is, it is possible to know how many times the corresponding track slot in the current loading mode is accessed by the counter 41a.

That is, when access is made only once
(Only when loading), the counter remains at the initial value 1.
is there. For example a truck in the same loading mode
The value of the counter 41a of the slot 365 is 1, so
Leading R that triggered the game _nOnly accessed
I understand that

The track slot 365 currently in the loading mode is released from the cache memory 36 (except when the track slot 365 is accessed) when the new data is loaded into the cache next time. is there. That is, it is assumed that the entry 41 of the cache management table 4 corresponding to the track slot 365 has the lowest rank in the LRU method.

At this time, in this embodiment, when the track slot 365 in the loading mode is released (step 64), the entry 4 corresponding to the track slot 365 in the cache management table 4 is released.
If the counter 41a of 1 is equal to or less than the specified value (1 in the case of the present embodiment), the cylinder statistical information table 5
At, the loading mode counter 51c in the entry 51 of the cylinder 23 to which the track slot 365 belongs is incremented by 1 (step 65).

That is, the value of the loading mode counter 51c in the cylinder statistic information table 5 is once stored in the records other than the first record of the track slot that triggered the loading after loading in the cache memory 36 in the loading mode. It indicates how many track slots are opened in the cylinder 23 without being accessed.

[0066] Then, the disk control unit 3 determines the ratio _{X L} with respect to the value of the access count record unit 51b of the value of the loading mode counter 51c each time comes access to the cylinder 23 (step 72).

[0067] Then, if it exceeds the prescribed percentage of where this ratio _{X L} (K) (in the present example K = 0.8) (step 73), when loaded from the magnetic disk device 2 to the cache memory 36 It is judged that it is useless to copy a plurality of records in the same track by the loading mode, and the cache operation mode is switched from the current loading mode to the record mode (step 74).

At the same time, the access count recording section 51b and the loading mode counter 51c of the entry 51 corresponding to the cylinder 23 in the cylinder statistical information table 5 are stored.
Is cleared (step 75).

For example, in the cylinder statistical information table 5 of FIG. 1, in the entry 51 having the cylinder number CYL # of 248, the values of the access count recording section 51b and the loading mode counter 51c are 14 respectively.
And 12, and X _L = 12 / 14≈0.85. Change of the operation mode because X _L exceeds 0.8 prescribed is determined to be necessary.

Therefore, the disk controller 3 will
Loading from the group of tracks 22 belonging to the cylinder 23 having the cylinder number CYL # of 248 to the cache memory 36 is performed in the record mode until it is determined that the record mode is inappropriate.

On the other hand, when the cylinder 23 for which an access request has been issued from the higher-level central processing unit 1 is currently in the record mode (step 61), first, the cache memory is determined by the designated cylinder number, track number, record number, etc. 36 is searched for the target record (step 76).

Here, in the track slot 367 currently in the record mode, the track slot 36 concerned
Subsequent record R in track 22 corresponding to 7
_In the case of access to _{p + 2} , the cache memory 36
There is no target record R _{p + 2} above (step 7
7), the track 22 of the magnetic disk device 2 must be loaded into the cache memory 36 (step 78). Then, the record is output to the channel device 11 (step 79).

At this time, the disk controller 3 of the present embodiment
Increments the record mode counter 51d of the entry 51 corresponding to the cylinder 23 to which the track belongs in the cylinder statistical information table 5 (step 80).

That is, the record mode counter 51d of the entry 51 corresponding to an arbitrary cylinder 23 loads only a single record into the cache memory 36 from an arbitrary one of the group of tracks 23 belonging to the cylinder according to the record mode. Indicates that the succeeding record on the same track as the record has been accessed, and the number of times the loading in the record mode was insufficient.

[0075] Then, a ratio _{X R} for the values of the access count record unit 51b of the value of the record mode counter 51d each time comes access to the cylinder (step 81). If this ratio X _R exceeds a certain prescribed value (L) (L = 0.6 in the case of this example) (step 8
2) The cache operation mode is automatically switched from the current record mode to the loading mode (step 83).

The access count recording section 5 of the entry 51 corresponding to the cylinder 23 in the cylinder statistical information table 5
1b and the record mode counter 51d are cleared (step 84).

For example, in the cylinder statistical information table 5 of FIG. 1, the entry 51 having the cylinder number CYL # of 249 is used.
, The current access count recording unit 51b and record mode counter 51d have values 13 and 8, respectively, and X _R = 8 / 13≈0.62. Since X _R exceeds the specified value of 0.6, it is necessary to change the cache operation mode.

Therefore, the disk control device 3 thereafter loads the track 23 belonging to the cylinder 23 having the cylinder number CYL # of 249 into the cache memory 36 in the loading mode until it is determined that the loading mode is inappropriate.

If there is a target record in the cache memory 36 in the record mode, the record is output to the channel device (step 85).

As described above, in this embodiment, the counter 41a and the mode information section 41b provided in each entry 41 of the cache management table 4 and each entry 51 of the cylinder statistical information table 5 are provided. According to the operating status of each cache operation mode, which is grasped by the statistical information based on the access count recording unit 51b, the loading mode counter 51c, the record mode counter 51d, etc., the disk control device 3 flexibly selects the cylinder 23 and the like. As a unit, it has a learning function for automatically switching the cache operation mode between the loading mode and the record mode.

Therefore, even if the access pattern from the central processing unit 1 to the data stored in the magnetic disk unit 2 changes from moment to moment due to various circumstances,
It is possible to always maintain the optimum cache operation mode without human intervention.

As a result, the cache memory 36 can always be utilized to the maximum extent.

Further, in the information processing system including the central processing unit 1, the magnetic disk unit 2, the disk control unit 3, etc., the efficiency of data transfer between the central processing unit 1 and the magnetic disk unit 2 is greatly improved. .

Although the invention made by the present invention has been specifically described based on the embodiments, the present invention is not limited to the embodiments and various modifications can be made without departing from the scope of the invention. Needless to say.

For example, in the above embodiment, the case where the magnetic disk device is controlled by one disk control device has been described, but the present invention is not limited to this, and it may be controlled by a plurality of magnetic disk control devices. . In that case, the statistical information is shared between the disk control devices.

Further, in the above embodiment, the magnetic disk subsystem including the magnetic disk device and the disk controller is connected to one central processing unit, but it should be shared by a plurality of central processing units. It goes without saying that it is okay.

Furthermore, in the above-mentioned embodiment, the case where the cache operation mode and the statistical information are managed in cylinder units has been described, but the present invention is not limited to this, and may be managed in volume or data set units.

Needless to say, the cache operation mode is not limited to the one exemplified in the above embodiment.

According to the cache control method of the present invention, in the control device provided with the cache memory interposed between the central processing unit and the external recording device and storing a part of the data of the external storage device, A cache operation mode is provided, and a learning function for automatically switching the cache operation mode according to the operating status of each cache operation mode is provided. By monitoring whether or not the value of statistical information obtained as a ratio between the number of accesses from the central processing unit and the number of times the currently selected cache operation mode has been activated or deactivated exceeds a specified threshold value. The suitability of the operating status of the current cache operation mode can be determined. It is possible to automatically switch to another more suitable cache operating mode as needed.

As a result, even if the access pattern from the central processing unit changes from moment to moment, there is an effect that the optimum cache operation mode can always be maintained and the cache memory can be effectively utilized.

Further, in the information processing system of the present invention, the central processing unit, the external storage unit, and the central processing unit and the external storage unit are interposed to store a part of the data of the external storage unit. An information processing system including a control device having a cache memory, which has a plurality of cache operation modes, and a learning function for automatically switching the cache operation modes according to the operating status of each cache operation mode. is doing. By monitoring whether or not the value of statistical information obtained as a ratio between the number of accesses from the central processing unit and the number of times the currently selected cache operation mode has been activated or deactivated exceeds a specified threshold value. The suitability of the operating status of the current cache operation mode can be determined. It can automatically switch to other, more suitable cache operating modes as needed.

As a result, even if the access pattern from the central processing unit changes momentarily,
It is said that it is possible to maintain the optimum cache operation mode at all times and effectively operate the cache memory, and improve the efficiency of information transfer between the central processing unit and the external storage device in which the cache memory is interposed. effective.

Next, similar to the above-mentioned embodiment, another embodiment for improving the information transfer efficiency between the central processing unit and the external storage device by the disk controller having the cache memory will be described. In this embodiment, a method for improving the hit rate and reducing the loading overhead will be described.

FIG. 6 shows the structure of the cache memory 36. The cache memory 36 is divided into fixed-length segments 30. It is assumed that one or more certain constant number of segments 30 are required to store one track of the magnetic disk device 2.

First, the case where one track is stored in a plurality of segments 30 will be described. The number of segments is n. The empty segment pointer 38 is
Points to a pointer in the set of free segments 30. Each segment 30 has a pointer and segment 3
When 0 is free, it points to the next free segment.
However, the pointer of the last empty segment 30 is null.
And

FIG. 7 shows the structure of the cache management table 6. The cache management table 6 is the same as that shown in FIG. 1, but only the parts necessary for explaining the present embodiment are shown. The cache management table 6 is composed of a cache management block 40. The cache management block 40 uses the cache memory 36 described above.
Allocate one or more of the segments 30 in the track corresponding to the assigned track. The empty block pointer 42 is a pointer to the leading cache management block 40 in the set of empty cache management blocks 40.

FIG. 8 shows the cache management block 40.
It shows the configuration of. The device ID 58, the cylinder ID 59, and the track ID 52 are identifiers for the disk device 2, cylinder, and track of the track on the disk device 2 corresponding to this cache management block.
The segment pointers (a) 53 to (n) 54 are n
A pointer to each segment 30 is shown. Of these pointers, only the number of segments storing the part stored in the cache memory 36 in the corresponding track is valid, and the rest is in the null state. A valid pointer becomes a pointer to the corresponding segment 30.

The storage start record identifier 55 is the identifier of the record that has started to be stored in the cache memory 36. For example, the storage start position of the track on the disk device 2 of this record and the storage end record identifier 56 are the cache memory. 36 shows the identifier of the record last stored in 36. That is, the cache memory 36
A record group in the range indicated by the storage start record identifier 55 and the storage end record identifier 56 is stored therein. The next pointer 57 becomes a pointer to the next cache management block 40 when the cache management block 40 is free. However, when there is no other free cache management block 40, the null value is set.

FIG. 9 shows a processing flow of the processor 33. FIG. 9 is a processing flow diagram when the processor 33 receives an input / output request from the central processing unit 1. Here, only the processing relating to one of the main points of the present invention will be described. In step 90, the storage status of the input / output target track in the cache memory 36 is checked. next,
If the entire track that is the target of the received I / O request does not exist in the cache memory 36, the central processing unit 1
The positioning request is issued to the disk device 2 in accordance with the positioning request (instruction to the disk device 2 for making necessary data read) received from (step 91). At this time, a sufficient number of segments 30 to store one track are secured.

Although a part of the track to be the input / output request is stored in the cache memory 36, the record to be accessed is the part after the track from the record group stored in the cache memory 36. If there is, process as follows. If there is a record to be accessed in a portion subsequent to the storage end record identifier 56, as shown in step 92, the records from the record next to the record indicated by the storage end record identifier 56 to the last record in the track are stored. Therefore, a positioning request is issued to the disk device 2. At this time, there is enough segment 3 to store the last record of this track.
Reserve a number of zeros.

When the record to be accessed is the part before the record group existing in the cache memory 36, the following processing is performed. Storage end record identifier 5
If there is a record to be accessed in the portion before 6, the load is performed from the record next to the record indicated by the storage end record identifier 56 to the last record in the track as shown in step 93. In order to store from the first record to the record before the record indicated by the storage start record identifier 55, a positioning request is issued to the disk device 2. In this case, when the last record of this track has been stored, loading is started from the first part of the track. In addition, at this time, the number of segments 30 required for the load processing is secured.

Next, the processing flow of the processor 33 when the positioning completion report is received from the disk device 2 will be described.
This will be described with reference to FIGS.

First, the case where the record in the track to be accessed from the central processing unit 1 does not exist in the cache memory 36 will be described. FIG. 10 Step 94
As shown in, the input / output processing is performed in accordance with the input / output request from the central processing unit 1. At this time, when a record is read from the disk device 2, this record is loaded into the cache memory 36. The record received from the central processing unit 1 is written to the disk device 2 as well as to the disk device 2 at the same time as it is written to the cache memory 36. After that, the storage start record identifier 55 and the storage end record identifier 56 are set. In this case, the records to be accessed from the central processing unit 1 (records to be written to the disk device 2) are a continuous record group.

FIG. 13 shows the data storage format at this time. As shown, the first record to be accessed is stored from the beginning of the segment 30. As a result, if the number of records to be accessed is small, not only the loading overhead can be reduced but also the used capacity of the cache memory 36 can be reduced.

FIG. 11 shows a case in which a positioning completion request for the process of loading the records from the record indicated by the storage end record identifier 56 to the last record of this track in the cache memory 36 is received. is there. In this case, as shown in step 95, a process of loading the record next to the record indicated by the storage end identifier 56 to the last record is executed. Further, the storage end record identifier 56 is set as the end point position of the track.

FIG. 14 shows the data storage format at this time. Thereafter, in step 96, the CPU is logically reconnected to the central processing unit 1 to start the input / output processing with the central processing unit 1. At this time, the newly loaded record will be added after the previously loaded record.

In FIG. 12, the next record indicated by the storage end record identifier 56 to the last record of this track are loaded into the cache memory 36, and then the storage start record identifier is read from the top record of the track. This is a process when the positioning completion process is received from the disk device 2 in order to execute the process of loading the records up to the record before 55 in the cache 21. This processing is executed in step 95. However, when the last record of the track has already been loaded, loading is started from the first record of the track. At this time, the storage start record identifier 56 is set to the record before the storage start record identifier 55.

FIG. 15 shows this storage format. Thereafter, in step 96, input / output processing with the central processing unit 1 is started. At this time, after the record group stored in the cache memory 36 so far, the record group up to the last record of the track is stored, and then the record group from the head of the track is stored.

In the above embodiment, when an access request is made to a record located behind the record group loaded in the cache memory 36, as shown in FIG.
Although an example is shown in which the record next to the record group loaded in the cache memory 36 is loaded, as shown in FIG. 12, all the records other than the record group loaded in the cache memory 36 are loaded. Alternatively, it may be loaded into the cache memory 36.

The above is the case of allocating a plurality of segments 30 for storing tracks. In this case, the capacity can be saved as compared with the case where the segments 30 are assigned to the tracks one-to-one when the entire tracks are not stored in the cache memory 36.

Next, an embodiment will be described in which one segment 30 is assigned to one track. In this case, the cache management block 40 shown in FIG. 8 has a different format, and the cache management block 40 shown in FIG.
The format is a. The difference from FIG. 8 is that only one segment pointer 150 is required.

As shown in FIG. 13, the storage format in the segment 30 may be such that the record first accessed by the central processing unit 1 is stored from the beginning of the segment 30, but the following method is used. You can take That is, as shown in FIG. 17, the record position is determined according to the relative position from the beginning of the track. In this case, the top record in the track is stored at the top of the segment 30.

The processing of the processor 33 may basically have the contents shown in the processing flows of FIGS. However, the timing for allocating the segment may be only when the record of this track is accessed in the cache memory 36, that is, only at the portion corresponding to step 91 in FIG. Further, in the case of the storage format shown in FIG. 17, when the record at the position before the record indicated by the storage start record identifier 55 is accessed, the record indicated by the storage start record identifier 55 from the head of the track is accessed. Up to the previous record may be stored.

In the above-described embodiment, the number of processors 33 in the control unit 3 is one, but a plurality of processors 33 are provided and an input / output path from the central processing unit and an input / output path from the disk unit 2 are provided. You may provide more than one. Further, the data transfer process between the central processing unit 1 and the cache memory 36 and the data transfer process between the disk device 2 and the cache memory 36 may be executed in parallel. Essentially, in this embodiment, the cache memory 36 is provided in the control device 3.
The other components are not essential.

As described above, according to this embodiment, the record to be loaded into the cache memory based on the existence state of the record in the track to be accessed by the input / output request from the central processing unit in the cache memory. Since the group is determined, it is possible to realize a data loading method capable of reducing the loading overhead based on the track-based management method even when the records making up the track have a variable length. It is effective.

Further, another embodiment for reducing the loading overhead to the cache memory and improving the hit rate will be shown.

FIG. 18 shows the configuration of the control memory 34.
The control memory 34 stores each module for realizing the function of the processor 33. Here, the part related to the present embodiment will be described. The access characteristic check unit 7 checks the access characteristic of the input / output request and stores information on the access pattern. The loading selection unit 8 determines the loading pattern according to the information collected by the access characteristic check unit. The loading execution unit 9 has a function of performing loading execution control according to the loading pattern selected by the loading selection unit 8.

FIG. 19 shows a different structure of the cache management table 4. Cache management table 10
Shows parts related to the present embodiment. The cache management block 40b is provided corresponding to a track to which one or more segments 30 in the cache memory 36 are allocated (meaning that a part of the track is stored in the cache). Each cache management block 40b
Is M by the forward pointer 48 and the backward pointer 47.
They are chained in the order of RU (Most Recently Used). The MRU pointer 42 points to the cache management block 40b of the track which was the most recent input / output target. LRU (Least Recent)
y Used) The pointer 43 indicates the cache memory 36.
In the set of tracks stored in, the cache management block 40b of the track that has not been the input / output target for the longest time is referred to. Therefore, a miss (data to be accessed does not exist in the cache memory 36).
Occurs, it becomes necessary to allocate a new segment 30, and when there is no free segment, the segment 30 storing the track corresponding to the cache management block 40b indicated by the LRU pointer 43 and this cache management block 40b. Will be released. The access time 44 is the cache management block 40b.
Stores the time when the track corresponding to was most recently input / output target. (Therefore, when the forward pointer 48 is traced from the MRU pointer 42, the access time 44 in each cache management block 40b becomes slower.) A free cache management without allocating a track. The block 40b starts from the free block pointer 45
0b is pointed to, and each cache management block 40b
Is pointed by the forward pointer 48 and the backward pointer 47.

The access characteristic information 46 stores the information obtained by the access characteristic check unit 7 for each input / output request in cache management units, that is, in the present embodiment, track units. In this embodiment, the access characteristic information 4 is associated with all tracks of the disk device 2.
6 is provided. A part of these pieces of information may be provided in the cache management block 40b to reduce the required storage capacity.

FIG. 20 shows the structure of the access characteristic information 46. In this embodiment, the received I / O request recognizes whether sequential access is performed. When the sequential access is recognized, a plurality of tracks that can be accessed thereafter are loaded. Hereinafter, this is simply referred to as multi-track loading.

When it is recognized that the access is not sequential access, the data of the track is stored in the cache memory 36.
From the state in which the central processing unit 1 does not exist at all, until a part or the whole is loaded into the cache memory 36 and the entire data of the track is expelled from the cache memory 36, the part actually accessed by the central processing unit 1 is read. Understand and select a loading method based on this.

First, information necessary for recognition of sequential access will be described. sequential·
The checking flag 100 is a flag indicating that it is being checked whether the data in this track is sequentially accessed. Specifically, this flag is turned on when the head record of the track corresponding to this access characteristic information is accessed. After that, if the access after the first record is not performed sequentially, and if the access is completed up to the last record of this track sequentially (when recognizing that this track has been accessed sequentially), Turn off the flag. The sequential identification address 101 indicates the position from the beginning of the track in which the record to be accessed is stored when the next access is performed sequentially. The sequential recognition flag 102 is turned on when the first record of this track is sequentially accessed. The timing to turn it off is when the input / output request is accepted for the next track.

For non-sequential accesses, when an input / output request is received, the record of the track to be accessed does not exist in the cache 21 (hereinafter referred to as a track miss), this track. Based on the idea that the central processing unit 1 wants to access the part to be loaded during the period until the data of is deleted from the cache memory 36.
The loading method shall be determined.

Next, the information for recognizing the portion actually accessed by the central processing unit in the track is shown.
One way of thinking is that a unit of a certain fixed length (P bytes in FIG. 21) is 1 bit, and a track is represented by a track bit pattern 108 of a plurality of bits as shown in FIG. 21, and when a certain record is accessed, The bit corresponding to the area where this record is stored on the track is turned on (in FIG. 21, record 1 and record m are accessed, and record 2 is not accessed. In the cache memory 36, only the area in which the bit is on is loaded. However, at the time of a track miss, if all the tracks are not loaded, then when this track becomes an input / output target, some data of this track exists in the cache memory 36, but the record to be accessed is May not exist in the cache memory 36. In this case, the record to be accessed is newly loaded into the cache memory 36. However, since the disk device 2 is a rotating body, the loading time itself is not shortened when there is a gap in the set of bits that are turned on. Therefore, in this embodiment, the case where the central processing unit recognizes the accessed portion according to the concept shown in FIG. 22 will be described in detail below.

In FIG. 22, the truck is divided into the upper access section 110, the front section 109, and the rear section 111. The upper access unit 110 is a group of records that the central processing unit 1 has made an access target when an input / output request for the track is accepted and a track error occurs. Front part 1
Reference numeral 09 denotes a record group at a position in front of the upper access unit 110, and rear portion 111 a record group at a rear position.

In this embodiment, for the accesses other than the sequential access, the following patterns are provided as the loading patterns at the time of track miss. (The present invention is effective even if it has a loading pattern other than these.) (A) Track loading: The entire track is loaded. (B) Upper access + rear loading ... Loading the upper access + rear. (C) Upper access part / loading: Only the upper access part is loaded.

Even when the above loading pattern is prepared, (b) the upper access section + rear section loading is executed, and when the record exists in the cache memory 36, the record of the front section 109 of the track concerned. There is a mistake when you access. This is called a front miss. (C) Upper access part-When loading is executed, a mistake occurs even when a record in the rear part 111 is accessed. This is called a rear miss. The processing when a front mistake or rear mistake occurs is shown below. (1) Front miss: All records in the track that have not been loaded in the cache memory 36 are loaded in the cache memory 36. (2) Rear miss: Only the rear part 111 is loaded into the cache.

In the case of loading as described above, from the occurrence of a track miss (front miss, rear miss) until the entire track is ejected from the cache memory 36, the upper access section 110, the front section 109,
The part of the rear part 111 that the central processing unit 1 actually accessed is grasped and stored. Statistical information on this accessed portion is collected, and at the time of a track miss, the loading method judged appropriate is selected. In this embodiment, the most frequent loading pattern of the past q times is selected.

For example, when the rear part 111 is accessed most often, (b) upper access part + rear part loading is selected.

Information that should be held in the access characteristic information 46 as information to be acquired in order to realize the above method will be described below.

The start / end address 103 is the track
At the time of a miss, the start / end address on the track of the upper access unit 110 accessed by the central processing unit 1 is shown.

The front part access flag 104 and the rear part access flag 105 are information indicating whether the central processing unit 1 has accessed the front part 109 and the rear part 111 after a track miss. The access unit checking flag 106 is a flag indicating that the front unit 109 and the rear unit 111 are being checked for access.

The statistical information 107 is information indicating whether the front portion or the rear portion has been accessed while the entire track has been expelled from the cache memory 36 after a track miss has occurred, that is, the front portion access flag 104, Information of the rear part access flag 105 is past r
It has been accumulated twice.

However, in order to save the storage capacity, the statistical information 107 may be in a unit larger than the track, for example, in each cylinder.

Hereinafter, a processing flow chart of the access characteristic check unit 7 and the loading selection unit 8 will be described. The loading execution unit 9 only loads in accordance with the instruction of the loading selection unit 8.

First, the processing flow of the access characteristic check unit 7 will be described. The access characteristic check unit 7 includes
There is recognition of sequential access and recognition of other access characteristics. First, the part related to recognition of sequential access will be described.

FIG. 23 shows the processing when the top record of the track is accessed. In step 120, the sequential checking flag 100 is turned on, and the processing is ended.

FIG. 24 shows a process executed when the process for the input / output request is accepted and the sequential checking flag 50 of the track is ON. First, in step 121, it is checked whether or not the position from the beginning of the track of the record targeted for access by the received input / output request matches the sequential discrimination address 101. If they match, it means that the records are accessed sequentially, and no processing is performed. If they do not match, in step 122, the sequential checking flag 100 is turned off.

FIG. 25 shows a process executed when the sequential check flag 100 of the track is ON when the process for the input / output request is completed. In step 123, it is checked whether the input / output processing has been completed up to the final record of the track. If not completed, in step 124, the relative address from the beginning of the track of the record next to the record processed by this input / output request is stored in the sequential determination address 101.

When completed, the records of this track have been accessed sequentially, so
In step 125, the sequential recognition flag 1
02 is turned on and the sequential check flag 1
Turn off 01.

FIG. 26 shows the processing when the sequential recognition flag 102 of the track is turned on when the input / output request is received. In this case, in step 126, the sequential recognition flag 102 is turned off.

Next, a process for an access recognized as not a sequential access will be shown.

FIG. 27 shows a process executed after loading other than multi-track loading at the time of a track miss. (Multiple track loading is performed when it is recognized as sequential access.) In step 127, the central processing unit 1 is a group of records that are actually the access target of the input / output request in the track. That is, the start position and the end position from the beginning of the track of the upper access unit 110 in FIG. 22 are set in the start / end address 103. Further, in step 128, the access unit checking flag 106 is turned on.

FIG. 28 shows the access part checking flag 1
This is the process when an input / output request is received for the track when 06 is on. In step 129, the record to be accessed by the received input / output request is shown in FIG.
The positions of the front part 109, the upper access part 110, and the rear part 111 shown in FIG.

If the higher-level access unit 110 is the access target, nothing is done and the process ends.

When the front part 109 is the access target, the front part access flag 10 is determined in step 130.
If 4 is off, it is turned on (there is no processing when it is on). In step 131, when the entire track is not loaded in the cache memory 36, the loading execution unit 9 is instructed to load the unloaded portion.

If the rear portion 111 is the access target, the rear portion access flag 10 is determined in step 132.
If 5 is off, it is turned on (there is no processing when it is on). In step 133, the rear unit 111 instructs the loading execution unit 9 to load the rear unit 111 that is not loaded in the cache memory 36.

FIG. 29 shows a process executed when the relevant track is being ejected from the cache memory 36 and the front / rear part checking flag 106 is ON.

First, in step 134, the access section checking flag 106 is turned off. Then, step 135
In the past r times, the front access flag 10
4. Of the statistical information of the rear access flag 105,
Current front access flag 1 excluding oldest information
04, the contents of the rear part access flag 105 are stored. Thereafter, in step 136, the front access flag 104 and the rear access flag 105 are turned off.

Next, FIG. 30 shows a processing flow of the loading selection section 9. FIG. 30 is executed when a track miss occurs.

First, at step 137, it is checked whether this input / output request is an access to the head record of the track. Otherwise, jump to step 140. In the case of access to the first record, in step 138, it is checked whether the sequential recognition flag 102 of the access characteristic information 46 of the two tracks before the access target track is on. In the case of the present embodiment, two tracks are checked, but the present invention is effective even if the number of tracks is not two. If it is not on, the process jumps to step 140.

If it is on, it is judged that this access is a sequential access, and in step 139, the loading execution section 9 is instructed to load a plurality of tracks, and the processing is terminated.

The process starting from step 140 is a process of selecting the loading method when it is determined that the access is not sequential access. In step 140, based on the statistical information 107, the access pattern of the past q times is a pattern in which neither the front part 109 nor the rear part 111 is accessed, a pattern in which only the rear part 111 is accessed, and a pattern other than the above two patterns. Classify into three. As a result, when the pattern in which the front part 109 and the rear part 111 are not accessed is the most, the upper access part loading is instructed to the loading execution part in step 141.

If only the rear part 111 is accessed the most, the loading execution part 9 loads the upper part access part + the rear part in step 142.
Instruct.

If the other patterns are the most,
In step 143, the loading execution unit 9 is instructed to perform track loading.

Here, when loading is selected,
Although only the statistical information 107 of the track is referred to, the statistical information 107 other than the track may be referred to.

In the above-mentioned embodiment, since the sequential access is recognized, only one sequential identification address 101 is provided to check whether the records in the track are continuously accessed. For this reason, when a relatively frequently executed process of sequentially updating the record for which sequential reading has been performed, it cannot be recognized as a sequential access. Therefore, this problem is solved by recognizing the sequential access of the read processing and the write processing. In this case, the structure of the access characteristic information 46 is as shown in FIG. 31 instead of FIG. The difference from FIG. 20 is that the sequential check flag 100, the sequential identification address 101, and the sequential recognition flag 102 in FIG. 20 are for reading and writing. Which information to handle is
It depends on whether the received I / O request is a read request or a write request.
This is similar to the embodiment described above.

Further, when recognizing the sequential access, the condition that the position from the beginning of the track of the record which has the access effect of the input / output request for reception is exactly the same as the sequential identification address 101 is used. However, it may be recognized as a sequential access even if it has a certain width.

In the embodiment described above, the loading patterns when a track miss occurs for accesses other than sequential access are: upper access part loading (upper access part + rear part), loading, and track loading. Was this 3
It is possible to add a pattern without loading to one pattern. This is because the entire track is cache memory 36 after loading at the time of a track miss.
This is effective when there is no access to the track from the time it is ejected.

In this case, it is necessary for the central processing unit 1 to monitor not only the front part 109 and the rear part 111 but also the upper access part 110 after the loading at the time of a track miss, in order to monitor the part to be the access effect. .

Furthermore, when the pattern without loading is executed, it is necessary to perform the recognition described below. That is, when a track miss occurs, this track
Whether the error occurred because the loading was not performed at the time of the previous track miss, or whether the track miss occurred due to a long access time interval for the track even if loading was performed There is a need to. In the former case, there was no need for loading. However, in the latter case, if the access at this time is to the higher-order access unit 110, it means that it was necessary to load the higher-order access unit at the previous track miss. Similarly, when the access at this time is to the rear part 111, it is necessary to execute the loading of (upper access part + rear part). If it was for the front section 109, then it would have had to perform track loading. Therefore, it is necessary to make these distinctions, store the loading method that should have been selected at the time of the previous track miss in the statistical information 107, and reflect it in the subsequent selection of the loading method. At this time, the statistical information 107 indicates that the contents stored in the statistical information 107 indicate that the upper access unit 110, the front unit 109, and the rear unit 111 were not accessed when loading was not required at the previous track miss. Will be remembered in. If it is necessary to perform some loading at the previous track miss, if the access at this time is (a) to the upper access unit 110, the upper access unit 11
0 is accessed, (b) the rear part 111 is accessed if it is for the rear part 111, and (c) the front part 109 is accessed if it is for the front part 109. Will be remembered in.

In order to determine whether any loading was required when the previous track miss occurred, the access characteristic information 46a stores the time when the track miss occurred. Then, when a track miss occurs, this time is compared with the access time 44 in the cache management block 40b pointed by the LRU pointer 43. In the case where the method of eviction from the cache memory 36 is the LRU method, if this time is later than the access time, even if the loading was performed at the previous track miss, the cache memory 3 has already been loaded.
It means that you have been kicked out of 6. Otherwise,
It still depends on the cache memory 36, and the loading was necessary.

FIG. 32 shows the structure of the access characteristic information 46b when the pattern without loading is provided. Similarly, FIG. 33 shows a configuration 46c in the case where a pattern without loading is considered in the access characteristic information 46a of FIG.

The newly provided information will be described below. The upper access flag 170 is a flag for checking access to the upper access unit 110. The track miss occurrence time 171 is provided to store the track miss occurrence time. The purpose of using the upper access flag 170 and the track miss occurrence time 171 is as described above.

The difference between the statistical information A 172 and the statistical information 107 is that the statistical information 107 is the past information of the front access flag 104 and the rear access flag 105.
The statistical information A172 is obtained by adding the past information of the upper access flag to this. The relationship between the contents of the statistical information A172 and the loading method to be selected when a track miss occurs is shown below. (A) Upper access part 110, front part 109, rear part 1
When there are the most access patterns for all 11 ...
… No loading. (B) When the pattern in which only the upper-level access unit 110 is accessed is the most ... High-level access unit loading. (C) Rear part 111 or upper access part 110
+ When the pattern that only the rear part 111 is accessed is the most ... upper access 2 parts + rear part loading. (D) Other than the above three cases ... Track loading.

The basic idea when the pattern without loading is provided, the purpose of using the newly provided information, and the method of determining the loading to be selected at the time of a track miss have been described above. The processing flow is omitted because it is not so different from the pattern without loading and the pattern without the loading.

In the above embodiments, as the grasping of the access characteristics for accesses other than the sequential and the access, the case where the host computer system grasps the area actually targeted for access has been described. As for other contents,
There is a track hit rate (the rate at which a record to be accessed exists in the cache memory 36). At this time, when the hit rate becomes equal to or less than a certain value, it is conceivable that the track is not targeted for loading into the cache memory 36.
In some cases, the access characteristics may change, and it may be better to use it as a loading target. However, the cache memory 36
Hit rate can be measured if it is targeted for loading, but if it is not targeted for loading,
It is difficult to measure the hit rate. Therefore, the approximate value of the hit rate is grasped by some information. FIG. 34
FIG. 35 shows the data structure of the access characteristic information section 46c in this case, and FIG. 35 shows the processing flow. 34 shows a structure corresponding to FIG. 20 (a diagram corresponding to FIG. 31 is omitted). The records other than the sequential access will be described below. The track-miss occurrence time 171 is the same as the track-miss occurrence time 171, as shown in FIG. 32. The time at which the track-miss occurs but it is decided not to load this track on the cache memory 36 is recorded. . How to use the miss function 192 and the hit function 191 will be described in the description of the processing flow of FIG. However, in FIG.
In the processing flow of (1), since the track determines not to load the cache memory 36, all the I / O requests are track misses. In step 144, when this track is an access target, this track miss occurrence time 171 is compared with the access time 44 of the cache management block 40b indicated by the LRU pointer 43. Track miss occurrence time 17
If 1 is the older time, even if loading was done at the time of the previous track miss, it will be a mistake,
In step 145, the miss function 191 of FIG.
increase. Otherwise, in step 146, the hit function 192 is increased and the track miss occurrence time 18
Update 1. Hit function 192 and miss function 191
When the sum of the above values exceeds a certain value and the hit rate {hit function 1921 (hit function 191 + miss function 191)} exceeds a certain value from these two values, it becomes possible to load the cache 21 again. .

[0168]

As described above, according to the present invention, the record group to be loaded in the cache is determined based on the existence state in the cache of the record in the access target track of the input / output request from the host system. As a result, even if the records making up a track have a variable length, a remarkable effect that a data loading method capable of reducing the loading overhead based on the track-by-track management method can be realized can be achieved. be able to.

Further, according to the present invention, the reduction of the loading overhead to the disk cache and the improvement of the hit rate can be realized in a balanced manner.

[Brief description of drawings]

FIG. 1 is a conceptual diagram illustrating the operation of an example of a cache control method that is an embodiment of the present invention.

FIG. 2 is a block diagram showing the configuration of an example of an information processing system to which a cache control method is applied.

FIG. 3 is a conceptual diagram illustrating a cache operation mode in a cache control method that is an embodiment of the present invention.

FIG. 4 is a conceptual diagram showing an example of a configuration of an external storage device.

FIG. 5 is a flowchart showing the operation of a cache control method according to an embodiment of the present invention.

FIG. 6 is a diagram showing a configuration example of a cache memory.

FIG. 7 is a diagram showing a configuration of a cache management table.

FIG. 8 is a diagram showing a configuration of a cache management block.

FIG. 9 is a processing flowchart of the processor according to the embodiment of the present invention.

FIG. 10 is a processing flowchart of a processor according to another embodiment of the present invention.

FIG. 11 is a processing flowchart of a processor according to another embodiment of the present invention.

FIG. 12 is a processing flowchart of a processor according to another embodiment of the present invention.

FIG. 13 is a diagram showing a data storage format in the embodiment of the present invention.

FIG. 14 is a diagram showing a data storage format in the embodiment of the present invention.

FIG. 15 is a diagram showing a data storage format in the embodiment of the present invention.

FIG. 16 is a diagram showing another embodiment of the cache management block.

FIG. 17 is a diagram showing a data storage format in the embodiment of the present invention.

FIG. 18 is a diagram showing a program configuration example for executing main functions of the present invention.

FIG. 19 is a diagram showing a configuration of a cache management table.

FIG. 20 is a diagram showing a structure of access characteristic information.

FIG. 21 is a diagram showing an example of a method of recognizing a portion accessed by a CPU in a track.

FIG. 22 is a diagram showing another example of a method for recognizing a portion accessed by a CPU in a track.

FIG. 23 is a processing flow diagram when the top record of a track is accessed.

FIG. 24 is a processing flow chart executed when the in-sequential check flag of the track to be accessed by the received input / output request is ON.

FIG. 25 is a processing flow chart executed when the processing for the input / output request is completed and the sequential checking flag of the track is ON.

FIG. 26 is a process flow chart executed when an input / output request is accepted and the sequential recognition flag of the track is ON.

FIG. 27 is a process flow chart executed after loading other than multi-track loading at the time of a track miss.

FIG. 28 is a process flow chart executed when an input / output request is received for the track when the access unit checking flag is ON.

FIG. 29 is a process flow chart executed when the access unit checking flag is turned on when the track is ejected from the cache memory.

FIG. 30 is a processing flowchart of a loading selection unit.

FIG. 31 is a configuration diagram of access characteristic information when sequential access recognition is performed independently for read and write.

FIG. 32 is a configuration diagram of access characteristic information when a pattern without loading is prepared.

FIG. 33 is a configuration diagram of access characteristic information when recognition of sequential access is performed independently for read and write and a pattern without loading is prepared.

FIG. 34 is a configuration diagram of access characteristic information when grasping an approximate value of a hit rate.

FIG. 35 is a processing flow chart when grasping an approximate value of a hit rate.

─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Toshiaki Tsuboi 5-22-1 Kamimizuhoncho, Kodaira-shi, Tokyo Hitachi Ultra LSI Systems Inc. (72) Inventor Shigeo Honma Odawara, Kanagawa Kozu 2880 Address Hitachi Co., Ltd.Odawara Plant (72) Inventor Katsunori Nakamura 2880 Kozu, Odawara City, Kanagawa Prefecture Incorporated Hitachi Ltd. Inside the Odawara Factory (72) Hiroyuki Kitajima, Hiroyuki Kitajima 1099 Ozenji, Aso-ku, Kawasaki, Kanagawa Hitachi, Ltd. System Development Laboratory (72) Inventor Akira Kurano 2880, Kozu, Odawara-shi, Kanagawa Hitachi Ltd. ) Inventor Masafumi Nozawa Country of Odawara City, Kanagawa Prefecture Tsu 2880 Address, Hitachi, Ltd. Odawara factory (56) Reference JP 57-211657 (JP, A) JP 61-273644 (JP, A) JP 63-4356 (JP, A) JP 64-23355 (JP, A) JP 63-204448 (JP, A) JP 59-123952 (JP, A) JP 58-76957 (JP, A) JP 57-209555 (JP , A) (58) Fields investigated (Int.Cl. ⁷ , DB name) G06F 12/08 G06F 3/06

Claims (12)

(57) [Claims] 1.Storage device having a plurality of storage areas and processing device
A controller connected to the storage device is stored in the storage device.
Data for transferring stored data to the processing device
A loading method, The storage device has, based on a request from the processing device.
The first record stored in the first storage area is read
When issued, The second record stored in the first storage area
Is stored in the cache memory of the control device.
, The first record and the first record
The first record and the first record stored in the memory area.
Records other than the second record are stored in the cache memory.
Transfer to The record stored in the first storage area is the key
If it is not stored in the cache memory,
Of the records in the cache memory.
Data loading method to collect. 2.Storage device having a plurality of storage areas and processing device
Memory that controls the transfer of data to and from the storage
A data loading method in a controller having
I mean The first storage device has the first reception from the processing device.
Access to the first record stored in the storage area of
According to the request, copy the first record to the cash memo.
Transfer to The first record exists in the cache memory
The first memory received from the processing device during
Request to access the second record stored in the area
According to the second record in the cache memory
Data stored in the first storage area.
A code, the first record and the second record.
Transfer records other than code to the cache memory
A data loading method comprising: 3. A record stored in the first storage area
Are numbered respectively and assigned to the first record
Number is smaller than the number assigned to the second record.
The data loader according to claim 2, wherein
How to go. 4. The data transferred to the cache memory,
Records other than the first record and the second record
Is a number greater than the number assigned to the first record
Claims characterized in that the record is assigned a number
Item 3. The data loading method according to Item 3. 5. The data transferred to the cache memory,
Records other than the first record and the second record
Except for the second record, the first record
Is the record numbered after the number assigned to?
The highest number in the first storage area
4. A record up to and including a record.
Data loading method. 6. A record stored in the first storage area
Each is numbered and assigned to the first record
The number is greater than the number given in the second record above.
Data loading according to claim 2, characterized in that
Method. 7. The data transferred to the cache memory,
Records other than the first record and the second record
Is a number smaller than the number assigned to the first record.
Claims characterized in that the record is assigned a number
Item 7. The data loading method according to Item 6. 8. The data transferred to the cache memory,
Records other than the first record and the second record
Is in the first storage area except for the second record
From the record with the smallest number in
A record with a number immediately before the number given to the code
7. The device according to claim 6, further comprising a code.
Data loading method. 9. A plurality of storage areas included in the storage device are
The track on the magnetic disk of the storage device
Any one of claims 1 to 8 characterized in that
Data loading method described in Section 1. 10.A processor having a storage device and a plurality of storage areas.
Connected to the storage device, based on the request of the processing device,
Processing the data stored in the plurality of storage areas
A control device for transferring to the device, A first interface system for connecting to the storage device
With the department A second interface system for connecting to the processing device
With the department From the storage device via the first interface control unit
Cache memo that temporarily stores the received data
Have a Received via the second interface controller,
Based on the first access request from the processing device,
The first record from the first storage area of the storage device
Transfer to the cache memory, The first record exists in the cache memory
While receiving the
Received from the processing device in the first storage area.
According to the second access request for the second record, before
Transfer the second record to the cache memory,
A record stored in the first storage area,
Records other than the first record and the second record
Mode is also transferred to the cache memory.
Control device. 11. Each of the plurality of storage areas is the storage device.
Characterized by being a track on a magnetic disk
The storage device according to claim 10. 12. The method according to claim 12,Based on the request from the processor, the storage device
The data stored in the storage is transferred to the processing device.
Control connected to the storage device and the processing device, if
The device caches the data stored in the storage device.
It is a method of temporarily storing in the memory, The storage is performed based on an access request from the processing device.
Multiple notes that the device has For each storage area,
Information indicating the access characteristics of multiple records in the memory area
Collect information, A first storage area included in the storage device from the processing device
Received a first access request to the first record of
The access based on the information indicating the access characteristics.
Whether the access request is a sequential access request
Judge, The first access request is a sequential access request.
If so, it is based on the information indicating the access characteristics.
And the first storage area and the storage device have
Store the record of the second storage area in the cache memory
Then The first access request is a sequential access request.
If it is determined that the access characteristic is not
Based on the information shown, a plurality of the first storage area has
Of the records, should be stored in the cache memory
Select a record and select the first record and the selected record.
Characterized by storing code and cache memory
How to do.