JP3465975B2 - Image synthesis device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a device for synthesizing an image by texture mapping, and more particularly, by providing a method of configuring a memory for storing data required for image synthesizing, it is possible to reduce the cost due to a small memory capacity. The present invention relates to an image synthesizing device configured to enable high-speed processing with various configurations.

[0002]

2. Description of the Related Art As one of so-called three-dimensional computer graphics (CG) methods for synthesizing a two-dimensional image from a three-dimensional structure of an object using a computer,
There is a technique called texture mapping.

According to this texture mapping, since each pixel value of the composite image data is obtained from the pixel value of the original image data, a natural image can be composed. However, on the other hand, since the amount of calculation required for image composition and the memory access are both large, a so-called multiprocessor composition device having a plurality of processors is used for image composition by texture mapping. Many.

An image synthesizing apparatus having a conventional multiprocessor structure for synthesizing images by texture mapping will be described below with reference to FIG.

As shown in FIG. 10, a plurality of processors 1
00a, 100b, ... (Hereinafter collectively referred to as 100) are buses 101a, 101b ,.
(Hereinafter collectively referred to as 101), the local memories 102a, 102b, ... (hereinafter collectively referred to as 102), and the frame memories 103a, 103b ,.
(Hereinafter collectively referred to as 103), and the frame memories 103 are connected together by the image path 104.

In the conventional image synthesizing apparatus having such a configuration, each processor 100 performs processing by distributing the load depending on the area of the synthesized image data to be processed. Each processor 100 stores original image data and drawing data required for image composition in the local memory 102, respectively, and processes them to generate composite image data of the allocated area. The composite image data generated by each processor 100 corresponds to the corresponding frame memory 103.
Stored in. The frame memory 103 is composed of a memory having two ports such as VRAM. The composite image data generated by being divided by each of the plurality of processors 100 are combined into one by the image path 104 and output.

Generally, in a device having a multiprocessor configuration, the performance depends on how small the contention of the memory access which occurs when the data shared by the processors is accessed. In the above-mentioned conventional image synthesizing device, the original image data and the drawing data are stored in the local memory, and the synthetic image data is stored in the frame memory for each divided area, so that the performance degradation due to the memory access competition from a plurality of processors is prevented. It avoids it and realizes high-speed image composition.

[0008]

However, in the conventional image synthesizing device, the generated synthetic image data (or the image data in the process of synthesizing) is used as the original image as in the image synthesizing including the processing such as the transparency and the reflection. If the data needs to be reused, the synthetic image data generated by another processor must be accessed. However, there is a problem in that such images cannot be combined at high speed because the number of processors that can access the combined image data is limited.

Further, it is necessary for a plurality of processors to reserve the memory areas for the original image data and the drawing data in the local memory in an overlapping manner, and a large memory capacity is required, so that the apparatus becomes expensive. There was also a problem.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide an inexpensive and high-speed image synthesizing apparatus by configuring a memory that can be simultaneously accessed by a plurality of processors. That is.

[0011]

An image synthesizing apparatus according to the present invention includes model data including information defining a three-dimensional structure of an object having a plurality of surfaces, and an original representing values of pixels belonging to the plurality of surfaces. An image synthesizing apparatus for synthesizing an image using image data and rendering data for converting a three-dimensional image synthesized using the original image data and the model data into a two-dimensional image, Memory means divided into a plurality of memory blocks on an address basis, the memory means storing the model data, the original image data, the rendering data, and combined image data representing a combined two-dimensional image; An arbiter unit having an address space, consecutive addresses in the address space are assigned to different memory blocks,
Thereby, there are provided an arbiter unit in which addresses of the plurality of memory blocks are interleaved, and a plurality of processor units for respectively synthesizing images of different surfaces of the plurality of surfaces of the object, Each of the parts accesses the memory means via the arbiter part and corresponds to a part of the model data corresponding to a specific surface of the plurality of surfaces and a specific surface of the original image data. And a plurality of processor means for synthesizing an image of the specific surface based on a portion of the rendering data corresponding to the specific surface, the original image data and the synthetic image data. Each is divided into a plurality of rectangular areas in the two-dimensional coordinate space, and the plurality of rectangular areas are respectively allocated to the plurality of memory blocks. Ri to achieve the above purpose.

The information defining the three-dimensional structure is a one-dimensional array of information defining the plurality of surfaces, and the plurality of processors are arranged in the plurality of processors in the order in which the information defining the plurality of surfaces are arranged. Images of the same number of surfaces of the plurality of planes are combined at the same time, and the image composition device combines the images of the original image data at the same time. It is determined whether or not a portion corresponding to the surface to be combined is stored in the same memory block, and when a portion corresponding to the surface to be simultaneously synthesized is stored in the same memory block, the plurality of surfaces It may further include means for changing the arrangement of the information defining the.

The plurality of processors simultaneously combine images of the same number of planes as the number of the plurality of planes of the plurality of planes, and the plurality of rectangular areas are arranged at a distance uλ in the first direction. Alternatively, the image synthesizing device is assigned to the same memory block for each distance vλ in the second direction, and the image synthesizing apparatus determines the size in the first direction of a portion of the original image data corresponding to any one surface. Is smaller than uλ and the size in the second direction is sufficiently smaller than vλ, and means for changing the configuration of the original image data before the original image data is stored in the memory unit. And a means for selecting the surfaces to be simultaneously combined so that the portions of the original image data corresponding to the surfaces to be simultaneously combined exist in different memory blocks.

The memory means has a DRAM,
Each of the plurality of memory blocks is one memory cell array of the DRAM, and each of the plurality of rectangular areas is further divided into a plurality of small rectangular areas,
The plurality of small rectangular areas may be assigned to a plurality of column addresses in the memory cell array.

The memory means has a DRAM,
Each of the plurality of memory blocks is one memory cell array of the DRAM, and each of the plurality of rectangular areas is further divided into a plurality of small rectangular areas,
Each of the plurality of small rectangular areas may be allocated to one column address in the memory cell array, and adjacent small rectangular areas may be allocated to different memory cell arrays.

A portion of the model data corresponding to the specific surface may be stored in the same memory block as a portion of the original image data corresponding to the specific surface.

The memory means and the arbiter unit may be mounted by a single LSI.

[0018]

According to the present invention, with the above configuration, the original image data, the combined image data, etc. are stored in the memory section which can be simultaneously accessed by a plurality of processors. Therefore, it is possible to simultaneously access the composite image data again as original image data from a plurality of processors. As a result, it is possible to eliminate the need to duplicately secure the original image data or the combined image data in the local memories of a plurality of processors as in the related art, and to realize a high-speed and inexpensive image combining device with a small memory capacity. You can

Further, the original image data and the composite image data are divided into a plurality of rectangular areas in the two-dimensional coordinate space, and each rectangular area is assigned to one memory block. As a result, it is possible to reduce the number of memory blocks accessed by one processor when synthesizing images of one surface. Further, by controlling the method of selecting the planes that are simultaneously processed by a plurality of processors, the frequency of memory access contention can be reduced.

Further, by dividing each rectangular area into smaller rectangular areas and allocating each small rectangular area to the same column in the memory cell array, it is possible to prevent a decrease in the image synthesizing speed due to the column address change. Further speeding up can be realized.

[0021]

【Example】

(Embodiment 1) Hereinafter, Embodiment 1 of the image synthesizing apparatus of the present invention will be described with reference to the drawings.

FIG. 1 shows a first embodiment of the image synthesizing apparatus of the present invention.
It is a figure which shows schematic structure of. The processor unit 10 has a plurality of processors 10a, 10b, ..., Each processor is connected to the arbiter unit 12 by a processor bus 13. The memory unit 11 is the memory bus 1
4 has a plurality of memory blocks 11a, 11b, ... Connected to the arbiter unit 12 respectively. The plurality of processors 10a, 10b, ... Are connected to the plurality of memory blocks 11a, 11 via the arbiter unit 12.
b, ... is accessed.

In FIG. 2, the arbiter unit 12 is the processor unit 1.
16 high-order 8 bits and low-order 8 bits viewed from 0
An example of address interleaving in the case of having an address space of bits, that is, an example showing a relationship between an address of the arbiter unit 12 and a plurality of memory blocks 11a, 11b, ... is there. In this example, the continuous address space of the arbiter unit 12 is assigned to different memory blocks 11a, 11b, ... By address interleaving.
For example, the address 0x000 seen from the processor unit 10
1 and 0x0002 are the memory blocks 11 respectively.
It is assigned to the address 0x00 of b and the address 0x00 of the memory block 11c, so that they can be simultaneously accessed.

When a plurality of processors simultaneously access a plurality of addresses of the arbiter unit 12 assigned to the same memory block, that is, when a memory access conflict occurs, one access is immediately processed. And a latency occurs for the rest of the accesses. This causes a decrease in the processing capability of the processor unit 10 having a plurality of processors. However, the frequency of memory access contention can be reduced by devising the method of allocating processing to multiple processors, and also by increasing the number of memory blocks with respect to the number of accesses. be able to.

FIG. 3 shows the data stored in the memory section 11. The memory unit 11 stores original image data 30, model data 31, rendering data 32, and combined image data 33. The original image data 30 and the composite image data 33 are data composed of a two-dimensional array of pixel values belonging to a plurality of surfaces of the object. The model data 31 is data including information defining a three-dimensional structure of an object having a plurality of surfaces and information on a correspondence relationship between the structure information and the original image data 30. The rendering data 32 is data including information such as a viewpoint and a projection surface at the time of combining, which is necessary for projecting an image combined using the original image data 30 and the model data 31 in a two-dimensional coordinate space. The composite image data 33 is data of an image generated using the original image data 30, the model data 31, and the rendering data 32.

FIG. 4 shows an example of the model data 31 stored in the memory section 11 as shown in FIG. The model data 31 includes original image data reference information that refers to the original image data 30, model configuration information that indicates that an object is composed of the faces p0, p1, ... It includes the configuration information, the two-dimensional coordinates of each vertex on the original image, and the vertex configuration information indicating the corresponding three-dimensional coordinates. The original image data reference information is sequentially referred to in the order in which the surfaces are arranged in the model configuration information. For example, when synthesizing a cube as shown in FIG. 3, the object has six faces, each face is composed of four vertices, and there are eight vertices in total.
Each vertex exists corresponding to the original image.

The operation of the image synthesizing apparatus having the above configuration will be described.

A plurality of processors 10a, 10b, ...
Of each of the plurality of planes p0, p1, ... Control of assigning a surface to be processed to each processor is performed by a control unit (not shown). Note that any one of the plurality of processors 10a, 10b, ... Can also serve as the control unit. Each processor accesses the memory unit 11 via the arbiter unit 12 and reads the part of the model data 31, the original image data 30, and the rendering data 32 corresponding to the surface assigned to each of them. Here, in the texture mapping processing by the plurality of processors 10a, 10b, ..., Most of the memory access is access to the original image data 30 and the composite image data 33.
When each processor generates the combined image data 33 of the surfaces assigned by the texture mapping processing based on the read data, the combined image data 33
Is written in the memory unit 11. This completes the image composition processing.

In the above-mentioned operation, the control for allocating the surface to be processed to each processor is performed as follows. First, the plurality of processors 10a, 10b, ...
Accesses the memory unit 11 in the order determined by the control unit and refers to the model data 31. Model data 3
In addition to structural information such as faces and vertices, an unprocessed flag indicating whether or not the image synthesis of each face is unprocessed is 1 for each face.
Each one is equipped. These unprocessed flags are all set to 0 before the image synthesizing process is started by each processor. Multiple processors 10a, 10b, ...
Refers to the unprocessed flags in the order in which the surfaces are arranged in the model configuration information, selects the surface whose unprocessed flag is 0, sets the unprocessed flag of the selected surface to 1, and then starts image synthesis. At this time, the control unit controls each processor so that another processor cannot refer to the model data while the unprocessed flag of the surface selected by one processor is being rewritten from 0 to 1. In this way, the plurality of processors 10a, 10b, ... Can perform image processing on different surfaces. By such control, a plurality of processors 10 among the plurality of planes p0, p1, ... Arranged in the model configuration information.
The image synthesizing processing of continuous planes is performed at the same time by a number equal to the total number of a, 10b, ....

As described above, in the image synthesizing apparatus of this embodiment, the plurality of processors 10a, 10b, ... Perform image synthesizing on different planes. Most of the memory accesses from the plurality of processors 10a, 10b, ... Simultaneously performed are accesses to different addresses of the original image data 30 and the composite image data 33. Therefore, access from the plurality of processors 10a, 10b, ... To the plurality of memory blocks 11a, 11b, ... Can be processed simultaneously in many cases, and as a result, high-speed image composition can be realized. You can

Further, according to the present embodiment, the generated composite image data is written in the memory space equivalent to the memory space in which the original image data 30 exists, as seen from the processor section 10. Therefore, as shown in FIG. 5, even when it is necessary to use the generated combined image data 33a as original image data to generate another combined image data 33b, it can be accessed from any processor, and the conventional It is possible to perform image synthesizing faster than the image synthesizing device having the multiprocessor configuration. Also, the original image data 3
0, the model data 31, the rendering data 32, and the multiple copies of the composite image data 33a and 33b do not need to be stored in duplicate, so that an image composition apparatus having a memory unit 11 with a small memory capacity can be realized. You can

(Second Embodiment) A second embodiment of the image synthesizing apparatus of the present invention will be described below.

In the second embodiment, the operation and the configuration of the image synthesizing device are the same as those of the image synthesizing device of the first embodiment except that the address interleaving method of the arbiter unit 12 is different.

FIG. 6 shows the arbiter unit 12 in this embodiment.
An example of the method of address interleaving of is shown below. The address space of the arbiter unit 12 is assigned to a plurality of memory blocks 11a, 11b, ...
Here, it is assumed that an address space of 256 words is assigned to one memory block. The interleaved block (16 × 16 block in this case) assigned to one memory block is obtained when each of the original image data 30 and the composite image data 33 is divided into a plurality of rectangular areas in the two-dimensional coordinate space. Is allocated to one rectangular area. By performing address interleaving in this way, in most cases, the number of memory blocks accessed by each processor when synthesizing an image of an assigned one surface is reduced as compared with the first embodiment. You can

Further, in the present embodiment, in addition to the control for allocating one surface to be combined with each image to each processor,
As a plurality of surfaces for which image combination is performed at the same time, control is performed to select a surface in which a portion corresponding to each surface of the original image data 30 or the like exists in different memory blocks. This can reduce the frequency of memory access conflicts.

Two examples of such control methods will be described below. Since the access amount to the model data 31 and the rendering data 32 is smaller than the access amount to the original image data 30 and the composite image data 33, the access collision to the original image data 30 and the composite image data 33 is avoided here. The control to be performed will be mainly described.

As described above, the plurality of processors 10
A, 10b, ... Simultaneously perform image combination processing of the same number of faces as the total number of processors according to the order in the model configuration information of the model data 31. Therefore, the arrangement order of the surfaces in the model configuration information may be determined so that the original image data 30 and the combined image data 33 corresponding to the surfaces to be processed at the same time exist in different memory blocks.

In the first control method, the surfaces are arranged in advance in the model configuration information of the model data 31 in an arbitrary order. When the original image data 30 and the model data 31 are read from the secondary storage device or generated by calculation and read into the memory unit 11, there is a portion corresponding to each surface of the model data 31 and the original image data 30. The memory block to be used is determined. The above-mentioned control unit (not shown) checks in which memory block the portion corresponding to each surface of the original image data 30 exists based on the read model configuration information. As a result, if the same number of consecutive planes as the total number of processors, that is, the planes in which image combining processing is likely to be performed at the same time, the portions of the original image data 30 are present in different memory blocks, they are left as they are. On the other hand, if something exists in the same memory block, the arrangement order of the planes in the model configuration information is changed so that the portions of the original image data 30 corresponding to consecutive planes exist in different memory blocks. .

The first control method will be described more specifically with reference to the control flow shown in FIG. Here, an image synthesizing apparatus including three processors 10a to 10c and a memory unit 11 divided into six memory blocks 11a to 11f is an image of an object having six planes p0 to p5. Consider as an example the case of synthesizing. In addition, the surfaces p0, p1, p2, p3, p of the original image data 30
The portions corresponding to 4 and p5 are the memory blocks 11a, 11b, 11a, 11c, 11d and 11e, respectively.
Shall be stored in.

After the original image data 30 and the model data 31 are read into the memory section 11, the control section executes the processing shown in FIG. First, the control unit specifies, out of the plurality of surfaces, the number of surfaces equal to the number of processors as the surface in which image synthesis is performed simultaneously in the order of arrangement in the model configuration information (step S1). For example, the planes p0, p1 and p
The three planes of 2 are specified as the planes on which image synthesis is performed at the same time. Subsequently, the control unit determines whether or not the number of pieces of the original image data 30 corresponding to the specified surface stored in the same memory block is n or less (step S2). n is an integer of 0 or more and is determined in advance in consideration of the number of processors provided in the image synthesizing device, the number of memory blocks, and the like. When the number of items stored in the same memory block exceeds n, the control unit controls the original image data 30 corresponding to the same memory block.
One of the n or more faces in which the part of is stored is selected as the target of the face arrangement change (step S
3). For example, the control unit selects the surface having the earliest arrangement order from the corresponding surfaces. Here, n = 0,
Since the parts of the original image data 30 corresponding to the surfaces p0 and p2 are stored in the same memory block 11a, the surface p0
Is selected as the surface whose order is to be changed.

Then, the control section selects the corresponding portion of the original image data 30 from the surfaces arranged after the surface specified in step S1 among the plurality of surfaces in step S3. The presence or absence of a surface stored in a memory block different from the stored surface is checked (step S4), and if there is a corresponding surface, one of the corresponding surfaces, for example, the one having the earliest arrangement order is determined to be step S3. The arrangement order is exchanged with the surface selected in (step S5). Such replacement of the array order of the planes is repeated until the number of those existing in the same memory block among the portions of the original image data 30 corresponding to the specified plane becomes n or less. If no surface remains after the surface specified in step S4, the process proceeds to step S6 and the process ends. By repeating such processing until there is no undetermined surface, control is performed to select a surface having corresponding portions of the original image data 30 in different memory blocks as much as possible, as surfaces to be simultaneously processed.

In the above example, the plane p3 and the selected plane p
The arrangement order is exchanged between 0 and 0. At this point, the arrays of the six faces in the model configuration information are p3, p1, p
The order is 2, p0, p4, p5. Next, the surfaces p0, p4, and p5 are selected as the surfaces to be processed at the same time, and the same processing as that described above is performed. Here, the portions of the original image data 30 corresponding to these surfaces are present in the memory blocks 11a, 11d, and 11e, respectively, and are all different. Therefore, the order of arrangement of the faces is not changed.

In this way, the plurality of processors 10
It is possible to prevent access to the original image data 30 from colliding as much as possible when images of a plurality of surfaces are simultaneously combined by a, 10b, .... Also, in general,
It is highly possible that surfaces that are not adjacent in the two-dimensional coordinate space of the original image data 30 are not adjacent in the two-dimensional coordinate space of the composite image data 33. This is because normally, in order to synthesize an image having a high image quality with a small area noise, the model data 31 and the original image data are arranged so that the area ratio of the original image data 30 and the synthetic image data 33 is as large as 1: 1. 30 are prepared, and therefore, the original image data 3
This is because there is a high possibility that the relationship between the surfaces of 0 and the relationship between the surfaces of the composite image data 33 are close to each other. Therefore, if the access to the original image data 30 is made to avoid the collision as much as possible by the above-described method, the possibility of the access collision to the combined image data 33 can be reduced.

Next, the second control method will be described.

Original image data 30 generated by calculation
Before the model data 31 and the model data 31 are read into the memory unit 11, the original image data 30, the model data 31, the rendering data 32, and the composite image data 33 are stored in the memory space.
The area in which is stored is defined. At this time, the portion of the original image data 30 corresponding to each rectangular area is assigned to the same memory block at a constant cycle. In the following, the u-direction and v-direction periods in the two-dimensional coordinate space are respectively represented by u.
Let λ and vλ. When the area for storing each data is secured, the control unit refers to the original image data 30 and the model data 31 before being read into the memory unit 11, and sets the original image data 30 and the model data 31 so as to satisfy a predetermined condition. The model data 31 is reconstructed. This will be described in detail later. Subsequently, the control unit determines a set of faces having a low probability that a corresponding portion of the original image data 30 exists in the same memory block, based on the vertex configuration information in the model data 31 read in the memory unit 11. To do. Based on this, the control unit controls the order of the surfaces on which the images are combined by the plurality of processors.

FIG. 12 is a diagram showing an example of the flow of the reconstruction process of the original image data 30 and the model data 31. First, the control unit examines the memory block to which each rectangular area of the original image data 30 is assigned, and based on this, obtains the cycles uλ and vλ (S101). Then, the control unit
The sizes of the parts of the original image data 30 corresponding to the respective surfaces in the two-dimensional coordinate space are examined, and the average sizes of the parts corresponding to the plurality of surfaces in the u and v directions are the cycles uλ and v, respectively.
It is determined whether it is smaller than λ (S102). If the average sizes in the u-direction and v-direction of the portions corresponding to the plurality of surfaces are larger than the cycles uλ and vλ, respectively, the setting of the surface size for generating the original image data 30 is changed. (S103). Corresponding to this, the model data 31 is also reconfigured (S104).

For example, if the object has surfaces p0 to p5 and the average size of the portions of the original image data 30 corresponding to these surfaces is larger than the cycles uλ and vλ, the control unit. Divides each face into smaller pieces. Assuming that the surfaces of the object are the surfaces p0 to p23 due to the division, the model data 31 correspondingly changes the model configuration information to the array of the surfaces p0 to p23, and the original image data reference information is 1 The part of the original image data 30 used for image composition of one surface is changed to one. At the same time, the surface configuration information and the vertex configuration information are also changed.

In the above-described processing, the average size of the portions of the original image data 30 corresponding to a plurality of surfaces is determined by the periods uλ and vλ.
Repeat until smaller. In this way, the original image data 30 and the model data 31 are reconstructed.

When the reconstructed original image data 30 and model data 31 are read into the memory section 11, subsequently,
A set of surfaces having a low probability that the corresponding portion of the original image data 30 exists in the same block is determined. Model data 31
As shown in FIG. 4, the configuration information of each of the vertices includes coordinates (ui, vi) in the two-dimensional coordinate space of the original image data 30. Using this, the control unit obtains the coordinates of the center of gravity of each surface and the distances between the centers of gravity in the u and v directions. If the distances in the u direction and the v direction between the centers of gravity of two planes are close to the natural multiples of the above-mentioned periods uλ and vλ, the portions of the original image data 30 corresponding to these two planes will be High probability of being in the same memory block. On the contrary, if they are not close (they are apart from each other to some extent), they are unlikely to exist in the same memory block. In practice, the control unit regards all surfaces as a “similarity” with a numerical value indicating the closeness between the distance between the centers of gravity of the two surfaces in the u direction and the v direction and the cycle uλ, a natural multiple of vλ. A surface having a low probability that the corresponding portion of the original image data 30 exists in the same memory block is determined based on the calculated similarity.

Based on this determination, the control unit controls the order of the surfaces on which the plurality of processors 10a, 10b, ... Combine images. As a result, it is possible to reduce access collisions when images of a plurality of surfaces are simultaneously combined by different processors.

Here, in a stage before the original image data 30 and the model data 31 generated by the calculation are read into the memory section 31, the portions of the original image data 30 corresponding to the respective surfaces in the two-dimensional coordinate space are calculated. The size is checked, and the original image data 30 and the model data 31 are reconstructed based on the size. However, a period uλ in which a rectangular area in the two-dimensional coordinate space is assigned to the same memory block,
Since vλ is known in advance, in the calculation for generating the original image data 30 and the model data 31, the size in the u direction and the v direction of the portion corresponding to each surface of the original image data 30 has a period uλ, It may be smaller than vλ.

As described above, in the present embodiment, one of the address-interleaved memory blocks is a rectangle obtained by dividing the original image data 30 and the composite image data 33 in a two-dimensional coordinate space in a grid pattern. It is assigned to one of the areas. This allows any one processor to
It is possible to reduce the number of memory blocks to be accessed when synthesizing an image of one surface. Further, the order of the planes for image synthesis is controlled so that the portions of the original image data 30 corresponding to the planes for image synthesis at the same time exist in different memory blocks. As a result, it is possible to reduce access collisions, and as a result, it is possible to realize an image synthesizing apparatus capable of performing high-speed image synthesizing.

In the present embodiment, two methods have been described as examples of control for making a plurality of surfaces on which image combination is performed simultaneously such that original image data and the like exist in different memory blocks. However, the same effect can be obtained when other control methods are applied. Further, instead of having a control unit, a plurality of processors 10a, 10b, ...
Any one of-may have a function similar to that of the control unit described above.

(Third Embodiment) A third embodiment of the image synthesizing apparatus of the present invention will be described below.

In the third embodiment, the operation and configuration of the image synthesizing apparatus are the same as those of the image synthesizing apparatus of the second embodiment except that the address interleaving method of the arbiter unit 12 is different. Further, in this embodiment, one memory cell array of DRAM is used as each of the plurality of memory blocks 11a, 11b, ....

FIG. 7 is a general configuration diagram of one memory cell array of DRAM. The data stored in the cell array 70 is specified by the combined address of the row address 71 and the column address 72. When reading data at a specific address in the memory cell array of the DRAM, first, all the data for one column having the same column address is once read by designating the column address of the data. Then, by specifying the row address, the data at the specific address is accessed. Therefore, continuous access to data having the same column address can be performed faster than continuous access to data having different column addresses.

In order to take advantage of the above-described advantages of the memory cell of the DRAM, in this embodiment, as in the second embodiment, the rectangular areas of the original image data 30 and the composite image data 33 are divided into one memory block, that is, one memory cell array. , And a small rectangular area obtained by further dividing this rectangular area is allocated to one column of one memory cell array. FIG. 8 shows an example of an address interleaving method of the arbiter unit 12 in this embodiment. Here, as one memory block, a memory cell array having a total of 8 bits, that is, a row address of 4 bits and a column address of 4 bits, is used, and the lower 4 bits of the address in the memory block are the row address and the upper address. It is assumed that 4 bits indicate the column address.

As described in the first and second embodiments, when a plane for image synthesis is assigned to each of a plurality of processors and image synthesis of a plurality of planes is performed at the same time, the original image data 30 and the synthesized image are combined. The frequency of continuous access to the portion of the data 33 corresponding to the adjacent region in the two-dimensional coordinate space increases. However, if the small rectangular areas are allocated to one column as in the present embodiment, the portions of the original image data 30 and the combined image data 33 corresponding to the adjacent areas are stored in the same column of memory cells. Therefore, it is possible to prevent a decrease in the access speed to the memory cell of the DRAM due to the change of the column address.

Further, in this embodiment, as in the second embodiment, if the order of the planes for synthesizing the images is controlled at the same time, D
The frequency of memory access competition can be reduced even in an image synthesizing apparatus using a RAM. This gives D
A high-speed image synthesizing device using RAM can be realized.

(Fourth Embodiment) A fourth embodiment of the image synthesizing apparatus of the present invention will be described below.

In the fourth embodiment, the operation and configuration of the image synthesizing apparatus are the same as those of the image synthesizing apparatus of the third embodiment except that the address interleaving method of the arbiter unit 12 is different.

FIG. 9 shows the arbiter unit 12 in this embodiment.
An example of the method of address interleaving of is shown below. Also in this embodiment, one memory cell array of DRAM is used as one memory block as in the third embodiment.
A portion of the original image data 30 and the combined image data 33 corresponding to one small rectangular area is assigned to one column in the memory cell array. Further, in this embodiment, the portions corresponding to the adjacent small rectangular areas in the two-dimensional coordinate space are allocated to different memory blocks.

In the third embodiment, a plurality of processors 10a,
10b, ...
It was stated that the frequency of memory access conflicts can be reduced by controlling the planes that are separated in the dimensional coordinate space, that is, controlling the order of the planes that synthesize images. However, conversely, for example, as a surface for simultaneously synthesizing images, a surface on which images are simultaneously synthesized by control such as selecting a surface in which all surfaces are present in one cycle uλ, vλ Can be surfaces close to each other in the two-dimensional coordinate space. The address interleaving method of the present embodiment is effective in such a case, and the frequency of memory access competition can be reduced.

It should be noted that the above first to fourth embodiments do not refer to the memory arrangement of the model data 31. However, as shown in FIG. 4, the portion corresponding to a specific surface of the surface configuration information including the array of vertices defining each surface may be stored in the same memory block as the portion of the original image data 30 corresponding to that surface. For example, it is possible to reduce the frequency of contention for memory access when accessing the model data 31. The same applies to the vertex configuration information including the coordinates of each vertex, and the portion of the vertex configuration information corresponding to a specific surface can be
By storing the same in the same memory block as the portion of the original image data 30 corresponding to the plane, it is possible to reduce the frequency of memory access conflict. This makes it possible to realize a faster image synthesizing device.

In the first embodiment, the processor unit 1
Although the address space of the arbiter unit 12 viewed from 0 is 16 bits, the same effect can be obtained even if the address space is other than 16 bits. Further, in the second embodiment, each memory block has an address space of 256 words, but the same effect can be obtained even if it is not 256 words.

In the first to fourth embodiments, the case where the object is composed of polygonal surfaces has been described. However, each of the plurality of surfaces of the object does not have to be a polygon, and the effects described in the above-described first to fourth embodiments may be used as long as the images of the plurality of surfaces are combined by the plurality of processors. The same effect as can be obtained.

Further, in any of Examples 1 to 4,
If the memory unit 11 and the arbiter unit 12 are mounted by one LSI, it leads to downsizing of the entire image synthesizing apparatus,
As a result, the cost can be further reduced.

[0068]

As described above, in the image synthesizing apparatus of the present invention, the synthetic image data is written in the memory space equivalent to the memory space in which the original image data exists, as seen from a plurality of processors. Therefore, even when the generated combined image data is further used as the original image data to generate another combined image data, it can be accessed from any processor, and as a result, compared to the image combining apparatus having the conventional multiprocessor configuration. High-speed image composition can be performed. Moreover, since it is not necessary to store a plurality of copies of each data in duplicate, the memory capacity can be reduced.

Further, each of the rectangular areas obtained by dividing the original image data and the combined image data in the two-dimensional coordinate space is allocated to one of the address-interleaved memory blocks. As a result, one processor can reduce the number of memory blocks accessed when synthesizing an image of one assigned surface. Furthermore, by controlling the order of the planes for synthesizing the images and synthesizing the images of the planes in which the corresponding portions of the original image data exist in different memory blocks at the same time, it is possible to reduce the defensive access conflict. .

When the memory section is composed of DRAM,
Each of the memory blocks is assigned to one memory cell array, and a small rectangular area obtained by further dividing the rectangular area is assigned to one column. This allows
Higher-speed image composition is possible.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a first embodiment of an image synthesizing apparatus of the present invention.

FIG. 2 is a diagram showing an address arrangement by address interleaving in the first embodiment.

FIG. 3 is a diagram showing a data arrangement in a memory unit in the first embodiment.

FIG. 4 is a diagram showing a structure of model data.

FIG. 5 is a diagram illustrating an arrangement of composite image data according to the first embodiment.

FIG. 6 is a diagram showing address arrangement by address interleaving in the second embodiment.

FIG. 7 is a block diagram showing a configuration of one memory cell array of DRAM.

FIG. 8 is a diagram showing address arrangement by address interleaving in the third embodiment.

FIG. 9 is a diagram showing address arrangement by address interleaving in the fourth embodiment.

FIG. 10 is a block diagram showing a configuration of a conventional image synthesizing device.

FIG. 11 is a flowchart showing the flow of a first method for controlling the order of the planes on which images are combined.

FIG. 12 is a flowchart showing the main part of the flow of a second method for controlling the order of the planes on which images are combined.

[Explanation of symbols]

10 Processor part 10a, 10b processor 11 Memory section 11a, 11b memory block 12 Arbiter part 13 processor bus 14 memory bus 30 original image data 31 model data 32 rendering data 33, 33a, 33b Composite image data 70 cell array 71 line address 72 column address 100a, 100b processor 101a, 101b bus 102a, 102b Local memory 103a, 103b frame memory 104 image bus

─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Masahiro Hamada 1006 Kadoma, Kadoma City, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. (56) Reference JP-A-3-201081 (JP, A) JP-A-5- 189550 (JP, A) JP-A-2-219184 (JP, A) JP-A-62-140181 (JP, A) JP-A-6-215143 (JP, A) JP-A-6-309471 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) G06T 15/00 G06F 15/167 G06F 15/177 G09G 5/36 G06T 17/40 CSDB (Japan Patent Office)

Claims (7)

(57) [Claims] 1. Model data including information defining a three-dimensional structure of an object having a plurality of surfaces, original image data representing values of pixels belonging to the plurality of surfaces, the original image data and the model data. And rendering data for converting a three-dimensional image synthesized using
An image synthesizing device for synthesizing images, comprising: memory means divided into a plurality of memory blocks at a predetermined address unit, the model data, the original image data, the rendering data, and a synthesized two-dimensional An arbiter unit having a memory means for storing composite image data representing an image and an address space, and consecutive addresses in the address space are assigned to different memory blocks, whereby the addresses of the plurality of memory blocks are assigned. Is an interleaved arbiter unit and a plurality of processor units that respectively combine images of different faces of the plurality of faces of the object, each of the plurality of processor units including the arbiter unit. A portion of the model data corresponding to a specific surface of the plurality of surfaces by accessing the memory means via A plurality of processor means for synthesizing an image of the specific surface based on a portion of the original image data corresponding to the specific surface and a portion of the rendering data corresponding to the specific surface, And each of the original image data and the composite image data is 2
An image synthesizing apparatus, which is divided into a plurality of rectangular areas in a dimensional coordinate space, and the plurality of rectangular areas are respectively allocated to the plurality of memory blocks. 2. The information defining the three-dimensional structure is a one-dimensional array of information defining the plurality of surfaces, and the plurality of processors are arranged in the order in which the information defining the plurality of surfaces is arranged. The images of the plurality of planes are combined to thereby simultaneously combine the images of the same number of planes as the number of the plurality of processors of the plurality of planes, It is determined whether or not the portions corresponding to the surfaces to be combined at the same time are stored in the same memory block. When the portions corresponding to the surfaces to be combined at the same time are stored in the same memory block, the plurality of The image synthesizing apparatus according to claim 1, further comprising a unit that changes an array of information that defines a plane of the image. 3. The plurality of processors simultaneously combine images of the same number of surfaces as the number of the plurality of processors of the plurality of surfaces, and the plurality of rectangular regions are separated by a distance uλ in a first direction. Every v or in the second direction
The image synthesizing device allocates a portion corresponding to any one surface of the original image data in the first direction to a size smaller than uλ. Two
So that the magnitude in the direction of is sufficiently smaller than vλ,
A means for changing the structure of the original image data before the original image data is stored in the memory section, and a portion of the original image data corresponding to the surface to be simultaneously combined exists in different memory blocks, The composite image device according to claim 1, further comprising: a unit that selects the surfaces to be composited at the same time. 4. The memory means includes a DRAM, and each of the plurality of memory blocks includes the DRA.
M is one memory cell array, each of the plurality of rectangular areas is further divided into a plurality of small rectangular areas, and the plurality of small rectangular areas are respectively allocated to a plurality of column addresses in the memory cell array. The image synthesizing apparatus according to claim 1, 2, or 3. 5. The memory means has a DRAM, and each of the plurality of memory blocks has the DRA.
M is one memory cell array, each of the plurality of rectangular areas is further divided into a plurality of small rectangular areas, and each of the plurality of small rectangular areas is assigned to one column address in the memory cell array. The image synthesizing apparatus according to claim 1, wherein the adjacent small rectangular areas are allocated so as to correspond to different memory cell arrays. 6. The portion of the model data corresponding to the specific surface is stored in the same memory block as the portion of the original image data corresponding to the specific surface. The image synthesizing apparatus according to any one of items 1 to 5. 7. The memory means and the arbiter unit are
The image synthesizing device according to claim 1, wherein the image synthesizing device is mounted by a single LSI.