JP3460918B2 - Input buffer circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an input buffer circuit included in a semiconductor device such as a memory.

[0002]

2. Description of the Related Art Generally, a semiconductor device for inputting and processing a digital signal has a configuration as schematically shown in FIG.
A plurality of input buffer circuits 10A for converting an external signal DI into an internal signal DIX via an input pad PI connected to an external terminal, and an input of the internal signal DIX to execute predetermined signal processing and output an internal signal DM. Internal signal D through the internal circuit 20 and the output pad PO connected to the external terminal.
And a plurality of output buffer circuits 30 for outputting M as an output signal DO to the outside.
The internal circuit 20 executes a predetermined process on the signal input via 0 A, and outputs the process result to the output buffer circuit 3.
It is configured to output to the outside via 0.

The above-mentioned input buffer circuit 10A is provided with a CMOS inverter in the first stage of which a P-type field effect transistor TP1 and an N-type field effect transistor TN1 are cascade-connected between a power supply line Vdd and a ground line GND. , The external signal D based on the input threshold of this inverter
The logical value of I is determined and the internal signal DI corresponding to the logical value is determined.
X is generated and given to the internal circuit 20. In addition, in FIG.
For convenience of explanation, the first stage of the input buffer circuit 10A is simply represented by being configured with an inverter. However, in reality, a driver or the like is provided on the rear side of the input buffer circuit 10A. For the purpose of blocking the through current of, the input first stage is generally configured by using a NOR (Not OR) logic gate or the like.

Next, the output buffer circuit 30 is configured as a tri-state buffer whose output state can be set to a high impedance state by the output control signal S, and an inverter which inverts the output control signal S for controlling the output impedance state. INV, the output control signal S and its inverted signal are input to one of the respective inputs and the internal circuit 2
NOR logic gate N for commonly inputting signal DM from 0
A P-type field effect transistor TP connected between the O and NAND logic gate NA, the power supply line Vdd and the output pad PO, and the gate of which is connected to the output of the NAND gate NA.
2 and an N-type field effect transistor TN2 connected between the ground line GND and the output pad PO and having a gate connected to the output of the NOR gate circuit NO1.

This output buffer circuit 30 includes NAND logic gates NA and N when the output control signal S is at L level.
The OR logic gate NO inverts the signal DM from the internal circuit B and supplies it to the transistors TP2 and TN2 to make them conductive, and outputs a signal having a logical value corresponding to the internal signal DM to the outside.

As described above, a semiconductor device composed of a MOS field effect transistor inputs a signal of MOS level, but generally, a TTL (Transistor Transistor) is used.
storLogic) is configured to be compatible. In the TTL level signal, the maximum value of the input signal level V _IL corresponding to the logical value “0” is defined as 0.8V, and the minimum value of the input signal level V _IH corresponding to the logical value “1” is defined as 2.2V. Has been done. Therefore, when configuring a TTL compatible semiconductor device, the input logic threshold value of the input buffer circuit 10A described above is set between the input signal levels V _IL and V _IH, and the logic value of the external signal DI is based on this threshold value. To judge.

[0007]

By the way, the semiconductor device uses a buffer provided with transistors TP2 and TN2 having a large driving capability, such as the output buffer circuit 30, when the signal needs to be transmitted quickly. Drives the load of the signal transmission line (output). In this case, since a relatively large load (mainly the capacitance component) is driven by a transistor having a large driving capability, a large current instantaneously flows. As a result, a noise signal may be generated in the power supply line Vdd or the ground line GND wired inside the semiconductor device, and the input buffer circuit 10A may malfunction.

The mechanism of malfunction of the input buffer circuit A due to this noise signal will be described below with reference to FIG. With the signal level V _IL (about 0.8 V) of the logical value “0” being given to the input buffer circuit A as the external signal DI, at the time t1, the output buffer circuit 30
, The N-type field effect transistor TN2, which has been in the ON state until then, is turned OFF, and conversely, the P-type field effect that has been in the OFF state until then is changed. The transistor TP2 is turned on.

At this time, the output load is rapidly charged through the P-type field effect transistor TP2 having a large driving capability. This charging current decreases as charging progresses,
At the beginning of charging, the current becomes extremely large. Therefore,
When a plurality of buffers are moved at the same time, a current obtained by adding the charging currents generated in the buffers flows out from the power supply line Vdd, and an extremely large instantaneous current flows in the initial stage of charging. As a result, the potential of the power supply line Vdd is instantaneously drawn to the potential on the output side and lowered, and a noise signal is generated.
This noise signal is generated by the power supply line Vdd formed in the internal circuit B.
Is transmitted to the ground line GND via the capacitance component CAP between the ground line GND and the ground line GND, and the potential of the ground line GND is changed to the power supply line Vdd.
As well as.

When the potential of the ground line GND drops, the source potential of the transistor TN1 forming the input buffer circuit A connected to the ground line GND also drops. At this time, the signal level VIL of the external signal DI externally applied to the input section of the input buffer circuit A is kept constant (0.8 V) without being affected by the instantaneous current inside the semiconductor device.
The potential of the gate of the transistor TN1 relatively rises. As a result, the transistor TN1 is turned on more deeply, and the input logic threshold value of the input buffer circuit A is apparently lowered.

Here, for example, the input buffer circuit IB
When the input threshold of the inverter constituting the above is set to 1.5 V, there is only a 0.7 V margin between this input threshold and the input signal level V _IL or V _IH . So in this case,
When the logical threshold value of the input buffer circuit A apparently drops by 0.8 V or more, the internal signal DIX which is the output signal thereof is temporarily inverted even though the logical value of the external signal DI has not changed, The input buffer circuit A malfunctions.

Conventionally, the input buffer circuit A as described above is used.
In order to prevent the malfunction of the output buffer circuit C, the instantaneous current is reduced by reducing the driving capability of the output buffer circuit C, or in a semiconductor device such as a memory having a multi-bit output configuration, the output time of each bit is shifted so that each output buffer circuit Measures such as suppressing the peak of the noise signal by dispersing the generation time of the instantaneous current of are taken, but in any case,
There is a problem that the data output time is delayed.

As disclosed in Japanese Patent Publication No. 5-52091, the potential of the input terminal is controlled so as to detect the change in the potential due to the noise signal on the power supply line and cancel the influence of the noise signal. There are also things. But according to this,
A circuit for controlling the potential of the input terminal is required, which causes an increase in chip area. In addition, there is a difference in the generation time of the noise signal depending on the position on the chip, so that there is a problem that the potential of the input buffer must be appropriately controlled according to the position of each input buffer.

The present invention has been made in view of the above problems, and effectively prevents malfunction due to a noise signal of a power supply line or a ground line with a simple structure without causing a delay in data output time. An object is to provide an input buffer circuit of a semiconductor device that can be prevented.

[0015]

[Means for Solving the Problems] The present invention has the following configuration in order to solve the problems described above. An input buffer circuit according to the present invention is an input buffer circuit of a semiconductor device, comprising a first conductivity type field effect transistor having a source and a drain connected to an input section and a power supply line, and a first conductivity type field effect transistor. A first resistance element connected between the gate of the transistor and the power supply line, a second conductivity type field effect transistor in which a source and a drain are connected to the input section and the ground line, and the second conductivity type A second resistance element connected between the gate of the field effect transistor and the ground line , the first resistance element and the front
The value of the gate capacitance of the first conductivity type field effect transistor
To reduce the noise transmitted to the gate via the power supply line
So as to select the second resistance element and the second conductivity type.
The value of the gate capacitance of the field effect transistor of
Selected to mitigate noise transmitted to the gate through
Having the configuration of the input buffer circuit, characterized in that that.

[0016]

In the input buffer circuit according to the present invention, the first resistance element is formed by using the diffusion resistance of the second conductivity type, and the second resistance element is formed by using the diffusion resistance of the first conductivity type. having the configuration of the input buffer circuit you wherein a.

[0018]

The input buffer circuit according to the present invention has a structure of the input buffer circuit you comprising the third resistor element between the input portion and the external terminal.

[0020]

The operation of the present invention having the above structure will be described below.
To describe. According to the input buffer circuit of the present invention, when the potential of the power supply line changes, the source of the first conductivity type field effect transistor changes together with the potential of the power supply line. The potential of the gate connected to the power supply line hardly changes because the change in the potential of the power supply line is moderated by the first resistance element and the gate capacitance.

As a result, a potential difference is generated between the source and the gate of the first conductivity type field effect transistor to make them conductive,
It induces the potential of the input unit so as to follow the potential change of the power supply line. Similarly, when the potential of the ground line changes, the second
A potential difference is generated between the source and the gate of the conductivity type field effect transistor to make them conductive, and the potential of the input section is induced to follow the potential change of the ground line. As a result, even if the logic threshold value of the input buffer circuit fluctuates due to the fluctuation of the potential of the power supply line or the ground line, the potential of the signal externally applied to the input section does not exceed this logic threshold value and malfunction occurs. To be prevented.

[0023]

According to the input buffer circuit of the present invention,
The third resistance element increases the impedance between the input section and the external terminal. As a result, the induction of the potential of the input section is performed more effectively.

[0025]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a configuration diagram of an input buffer circuit according to a first embodiment of the present invention. As shown in the figure, the input buffer circuit 10 of the present embodiment has a P-type field effect transistor TP0 (of the first conductivity type) whose source and drain are respectively connected to the input portion P of the input buffer circuit 10 and the power supply line Vdd. Field effect transistor),
A resistance element RP (first resistance element) connected between the gate of the P-type transistor TP0 and the power supply line Vdd, and an N-type field effect transistor in which a source and a drain are connected to the input section P and the ground line GND, respectively. TN0 (second conductivity type field effect transistor) and the N-type transistor T
One end is connected to the resistance element RN (second resistance element) connected between the gate of N0 and the ground line GND and the input pad PI connected to the external terminal, and the other end is connected to the input section P. And a resistance element R1 (third resistance element).

The resistance element RP is formed by using the diffusion resistance of the N type diffusion layer, and the resistance element RN is formed by using the diffusion resistance of the P type diffusion layer. Here, as illustrated in FIG. 2, the substrate on which the N-type transistor TN0 is formed is biased to the potential of the ground line GND, and by utilizing the substrate resistance up to this biased portion, a high resistance resistance element is obtained. The RN can be formed in a small area. Similarly,
The resistance element RP is connected to the N where the P-type transistor TP0 is formed.
It can be easily formed by utilizing the diffusion resistance of the well.

Next, referring to FIG. 3, the logical value of the external signal DIN supplied to the input buffer circuit is "0" (0.8
The operation of the input buffer circuit 10 of this embodiment when the logical value of the output data D0 of the output buffer circuit changes from "0" to "1" in the V) state will be described. First, before time t1, the external signal DI (0.8 V) is given to the input section P as the external signal DIN via the resistor R1, and the P-type transistors TP1 and N-type transistors whose gates are commonly connected to the input section P are provided. The transistor TN1 is complementarily conductive, and is in an on state and an off state, respectively.

If the thresholds of the P-type transistor TP1 and the N-type transistor TN1 are 0.7V, an external signal DIN (0.8V) is commonly applied to the gates of the P-type transistor TP1 and the N-type transistor TN1. The P-type transistor TP1 is turned on in the high current region while being turned on in the region. As a result, the internal signal DIX becomes H level, the logical value of the external signal DIN is inverted, and the external signal DIN is supplied to the internal circuit as the internal signal DIX. In this case, the N-type transistor TN1 is turned on in the weak current region, but since the flowing current is extremely small, it can be regarded as an off state in fact. In the following description,
A transistor that conducts in a weak current region is treated as an off state.

Next, at time t1, when the transistor TP2 shown in FIG. 5 constituting the output buffer circuit is turned on and the logical value of the output signal changes from "0" to "1", as described above, Ground wire GN due to instantaneous current
A noise signal is generated at D, and the potential of the ground line GND temporarily drops. Since the power supply line Vdd and the ground line GND are wired in the chip with low resistance by a wide metal wiring, the noise signal generated in the output buffer circuit immediately passes through the power supply line Vdd and the ground line GND of the input buffer. Via the resistance element RN and the source potential of the N-type transistor TN0 is lowered.
Input to the gate of N0.

Here, the resistance element RN and the gate capacitance of the N-type transistor TN0 constitute an RC delay circuit,
By appropriately selecting the values of the resistance element RN and the gate capacitance, the noise signal transmitted to the gate of the N-type transistor TN0 via the ground line GND is mitigated, and the potential of the gate before the noise signal is generated. It is maintained almost at the electric potential. Therefore, the noise signal is effectively an N-type transistor TN0.
Is not transmitted to the gate.

As a result, a potential difference is generated between the source and drain of the N-type transistor TN0, and when this potential difference exceeds the threshold of the N-type transistor TN0, the N-type transistor TN0 becomes conductive and the input buffer circuit 10 is turned on. The potential of the gate of the N-type transistor TN1 forming the first stage is lowered. That is, the transistor T connected to the input portion P
The gate potential of N1 is induced and decreases in the direction of the change of the potential of the ground line GND.

As described above, when the gate potential of the N-type transistor TN1 drops following the source potential thereof, the potential relationship between the source and gate of the N-type transistor TN1 is substantially maintained before and after time t1. As a result, the N-type transistor TN1 maintains the off state and the internal signal DIX maintains the H level. That is, even if the potential of the ground line GND lowers due to the noise signal and the input logic threshold value of the input buffer circuit 10 lowers, the potential of the input portion P follows and lowers. Without internal signal D
Maintain the signal state of IX.

Next, when the logical value of the external signal DIN supplied to the input portion P of the input buffer circuit 10 is "1" (2.2V), the logical value of the output data D0 of the output buffer circuit is "1" (2.2V). When changing from "0" to "1", the N-type transistor TN2 discharges the output load rapidly,
The potential of the ground line GND temporarily rises, and under the influence of this, the potential of the power supply line Vdd also rises.

In this case, the noise signal on the power supply line Vdd is given to the gate of the P-type transistor TP0 via the resistance element RP.
The gate potential of 0 is attenuated by the RC delay circuit, and the gate potential of the P-type transistor TP0 is maintained substantially constant. Therefore, a potential difference is generated between the gate and the source of the P-type transistor TP0, the P-type transistor TP0 becomes conductive, and the potential of the input section is raised.

That is, the gate potential of the P-type transistor TP1 forming the first stage of the input buffer circuit rises so as to follow the change of the source potential, and as a result, the P-type transistor TP1 is not affected by the noise signal. Time t
The off state is maintained before and after 1, and the state of the internal signal DIX is maintained.

As described above, according to the input buffer circuit of this embodiment, the power supply line Vdd or the ground line GND is used.
Since the electric potential of the input section is induced in the same direction as the direction of change of the signal, even if the logical threshold value of the input buffer circuit changes due to the noise signal, the external signal DIN follows the change of the logical threshold value, and It won't happen.

Next, a second embodiment of the present invention will be described with reference to FIGS. As shown in FIG. 4, the input buffer circuit 11 of the present embodiment is provided with a capacitive element C1 connected between its input portion P and the ground line GND. As shown in FIG. 5, the capacitive element C1 can be formed in a small area by using the gate capacitance of the field effect transistor.

That is, in the capacitor C1 shown in FIG. 4, as shown in FIG. 5, the P-type impurity high concentration region formed in the N-well is used as one electrode, and the P-type impurity is sandwiched with the gate oxide film interposed therebetween. The gate wiring layer GL facing the high concentration region PL is configured as the other electrode. Then, the one electrode is
It is connected to the ground line GND together with the source of the N-type transistor TN1, and the other electrode is connected to the N-type transistor TN1.
Is connected to the input section P together with the gate of. Here, the capacitance value of the capacitive element C1 is, for example, the parasitic capacitance value (1
pF) is set to about 3 to 5 times.

In the example shown in FIG. 5, the P-type impurity region PL forming the one electrode is formed in the N well, but it may be formed directly on the P substrate. It is also possible to use a so-called MOS capacitor, but in the case of a MOS capacitor, if a potential difference does not occur until the threshold is exceeded, the channel that constitutes one of the electrodes is not formed, so that a large noise signal However, the malfunction due to a small noise signal cannot be prevented. Therefore, as in this embodiment, it is desirable to have a configuration capable of forming a capacitance without going through a channel.

In the input buffer circuit 11 of the present embodiment having such a configuration, as shown in FIG. 6, the capacitance C1 induces the potential (signal DIN) of the input portion P in the direction of change of the ground line GND. As a result, even if the input logic threshold value of the input buffer circuit 11 apparently changes due to the noise signal, the external signal DIN follows the change of the input logic threshold value, so that the external signal DIN exceeds this input logic threshold value. , There is no inversion of the internal signal DIX.

Similarly, by providing a capacitive element between the input section P and the power supply line Vdd, even if the potential of the power supply line Vdd is temporarily increased due to a noise signal, the internal signal DIX of the internal signal DIX Inversion does not occur and malfunction can be prevented.

[0042]

As is apparent from the above description, according to the present invention, the potential of the input external signal is induced in the direction of the change of the potential of the power supply line or the ground line, and the external signal becomes the input logic threshold value. Since it is configured so as not to exceed the limit, it is possible to prevent malfunction even when the potential of the power supply line or the ground line changes due to a noise signal, and it is possible to expand the operation margin.

Further, since the potential of the external signal is induced based on the change in the potential of the power supply line or the ground line in the input buffer circuit, even if there is a time lag in the noise signal in the plurality of input buffer circuits, It is possible to quickly deal with each input buffer circuit and prevent malfunction.

Therefore, according to the present invention, it is possible to effectively prevent a malfunction caused by a noise signal generated in the power supply line or the ground line, and to construct it by only adding an extremely small-scale element. .

[Brief description of drawings]

FIG. 1 is a configuration diagram of an input buffer circuit according to a first embodiment of the present invention.

FIG. 2 is a partial cross-sectional view of a semiconductor chip having an input buffer circuit according to the first embodiment of the present invention.

FIG. 3 is a waveform diagram for explaining the operation of the input buffer circuit according to the first embodiment of the present invention.

FIG. 4 is a configuration diagram of an input buffer circuit according to a second embodiment of the present invention.

FIG. 5 is a partial cross-sectional view of a semiconductor chip having an input buffer circuit according to a second embodiment of the present invention.

FIG. 6 is a waveform diagram for explaining the operation of the input buffer circuit according to the second embodiment of the present invention.

FIG. 7 is a schematic configuration diagram of a semiconductor device including a conventional input buffer circuit.

FIG. 8 is a waveform diagram for explaining a malfunction mechanism of a conventional input buffer circuit.

[Explanation of symbols]

Input buffer circuit TP0, TP1 P-type field effect transistor TN0, TN1 N-type field effect transistor C1 capacitive element R1 resistance element Resistance element using RPP type impurity diffusion layer Resistance element using RN N-type impurity diffusion resistor P input section PI input pad

─────────────────────────────────────────────────── ─── Continuation of front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) H03K 19/0175 H03K 17/16 H03K 19/003

Claims (3)

(57) [Claims] 1. An input buffer circuit of a semiconductor device, comprising: a first conductivity type field effect transistor having a source and a drain connected to an input section and a power supply line; and a gate of the first conductivity type field effect transistor. A first resistance element connected between the power supply line, a second conductivity type field effect transistor in which a source and a drain are respectively connected to the input section and the ground line, and a second conductivity type field effect transistor connected and a second resistive element, said first resistive element and a field effect tiger of the first conductivity type between the gate and the ground line
The gate capacitance value of the
Selected to mitigate the noise transmitted to the second resistor.
The anti-element and the field effect transistor of the second conductivity type.
The value of the gate capacitance is transmitted to the gate through the ground line.
An input buffer circuit, which is selected so as to reduce sound . 2. An input buffer circuit for a semiconductor device
The source and drain to the input section and the power supply line, respectively.
The first conductivity type field effect transistor, the gate of the first conductivity type field effect transistor and
A first resistance element connected between the source line and the source and drain to the input section and the ground line, respectively.
The connected second conductivity type field effect transistor, the gate of the second conductivity type field effect transistor and the contact.
A second resistance element connected to the ground wire, the first resistance element is formed by using a diffusion resistance of the second conductivity type, and the second resistance element is a diffusion resistance of the first conductivity type. input buffer circuit characterized by being formed with. 3. The input buffer circuit according to claim 1 or 2, further comprising a third resistive element between the input portion and the external terminal.