JP3460115B2 - Cross connect device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a cross-connect device for cross-connecting a plurality of incoming lines and a plurality of outgoing lines in time slot units. In various networks, there is provided a cross-connect device that can arbitrarily set the state of line connection between multiple points. There is also known a cross-connect device for performing time-slot-based cross-connection for time division multiplex lines. There has been a demand for simplification of the structure of such a cross-connect device and cost efficiency.

[0002]

2. Description of the Related Art FIG. 8 is an explanatory view of a conventional cross-connect device. 81-1 to 81-3 are time switches corresponding to incoming lines, 82 is a space switch, and 83-1 to 83-3 are outgoing lines. Of the time switch T, and the case of the T-S-T configuration of the time switch T and the space switch S is shown.

For example, data A, B, and C corresponding to the first to third time slots are input to the time switch 81-1 on the incoming line side, and data D corresponding to the first to third time slots are input to the time switch 81-2. , E, F are input, and the data G, corresponding to the first to third time slots is input to the time switch 81-3.
H and I are input, and time slots are exchanged at time switches 81-1 to 81-3,
C, A, B order, E, F, D order and I,
The case where the order is G and H is shown, and each is input to the space switch 82.

The space switch 82 controls the switches at the matrix intersections corresponding to the time slots. For example, the time switches 83-1 to 83-3 on the outgoing line side are provided with the data C, F, and I corresponding to the time slots, respectively. , E, G,
Input B, H, A, and D. Time switch 83-1
~ 83-3 are I, F, C and E, B, G, respectively.
Cross-connect is performed as a time slot order with A, H, and D.

In this case, the time switch 81-1 on the incoming line side
The data A of the first time slot input to the first time slot is output from the time switch 83-3 on the outgoing line side to the first time slot, and the data B of the second time slot is input from the time switch 83-2 on the outgoing line side. Output to the second time slot,
The data C of the third time slot is output from the time switch 83-1 on the outgoing line side to the third time slot.

[0006]

The time switches 81-1 to 81-1 on the incoming line forming the conventional cross-connect device are known.
-3 and the time switches 83-1 to 83-3 on the outgoing line side are
It is equipped with an address control memory for sequential writing, random reading for writing and reading data corresponding to the time slot to the data memory, random writing, or vice versa, and the number of incoming lines and outgoing lines. Since it is necessary to provide time switches for each of the numbers, the size becomes large and the configuration becomes expensive. Similarly, since the space switch 82 is also composed of a switch having a matrix configuration for distributing data corresponding to time slots between incoming lines and outgoing lines, the spatial switch 82 becomes large in size as the number of incoming lines and outgoing lines increases. It becomes an expensive structure.
An object of the present invention is to reduce the size and cost of a cross-connect device.

[0007]

The cross-connect device according to the present invention includes (1) a plurality of time slots of incoming lines 1-1 to 1-3 and a plurality of selected outgoing lines of 7-1 to 7-3. A cross-connect device for converting into a selected time slot of a line, and input side buffer memories 2-1 to 2 for writing data of at least one frame of time slot corresponding to a plurality of input lines 1-1 to 1-3. -3 and this buffer memory 2
-1 to 2-3, the data of the time slot for one frame read at high speed is written into the address corresponding to the input lines 1-1 to 1-3, and the output line 7-1 from the data memory 4. To output buffer memories 5-1 to 5-3 for reading and writing data in time slots corresponding to 7-3 at high speed and reading data at a speed corresponding to output lines 7-1 to 7-3,
Address control memories 6-1 to 6-3 corresponding to outgoing lines for sequentially outputting the read addresses of the data memory 4 are provided. Therefore, the data memory 4 for exchanging time slots can be shared by a plurality of incoming lines 1-1 to 1-3 and a plurality of outgoing lines 7-1 to 7-3.

(2) In the data memory 4, the incoming lines 1-1 to 1-1
Input-side buffer memories 2-1 and 2-2 store channel pulses for writing only the data of valid time slots corresponding to 1-3.
-3 can be provided with channel pulse generators 3-1 to 3-3.

(3) Channel pulse generators 3-1 to 3
-3 can generate a channel pulse for writing only the data of the valid time slot corresponding to the incoming line into the incoming side buffer memories 2-1 to 2-3.

(4) Channel pulse generators 3-1 to 3-1
-3 sequentially writes the data of each time slot corresponding to the incoming line into the incoming buffer memories 2-1 to 2-3, and reads only the data of the valid time slot from the incoming buffer memories 2-1 to 2-3. It can be configured to generate a channel pulse.

(5) Data is written in the data memory 4 at a speed which is at least a multiple of the number of incoming lines with respect to the transmission speed of the incoming lines 1-1 to 1-3 from the incoming buffer memories 2-1 to 2-3. It is to be configured.

Further, (6) From the data memory 4, the output line 7-1
To 7-3, the data is read out at a speed at least several times the number of outgoing lines, and the output side buffer memories 5-1 to 5-5 are read.
-3 is written.

[0013]

1 is an explanatory view of a cross-connect device according to an embodiment of the present invention. 1-1 to 1-3 are incoming lines, 2-1 to 2-3 are incoming buffer memories (BF). ) 3
-1 to 3-3 are channel pulse generators (CP), 4 are data memories (DM), 5-1 to 5-3 are output side buffer memories (BF), and 6-1 to 6-3 are address control memories. (ACM), 7-1 to 7-3 indicate outgoing lines.

The cross-connect device of this embodiment is
Input side buffer memories 2-1 to 2-3 and data memory 4
And the output side buffer memories 5-1 to 5-3 as main parts, and three incoming lines 1-1 to 1-3 and three outgoing lines 7-.
The case of 1-7-3 is shown. It should be noted that the present invention can be applied to the case of a larger number of incoming lines and outgoing lines.

The input side buffer memories 2-1 to 2-3 and the output side buffer memories 5-1 to 5-3 are the data memories 4.
Shows the case of connection in bus form. Therefore, the input side buffer memories 2-1 to 2-3 and the output side buffer memories 5-1 to 5-3 are selectively connected to the data memory 4 by controlling a bus driver, a gate and the like (not shown). It is possible to write data and read data. In addition, the input side buffer memories 2-1 to 2-3 are
The data corresponding to the time slot is written by the clock signal corresponding to the transmission speed of the incoming lines 1-1 to 1-3, and the data is written in accordance with a clock signal faster than the clock signal at the time of writing the data, for example, a clock signal which is a multiple of the incoming lines. Is read and the data is written in the data memory 4. Writing in this case is sequential writing, and the address control memory in that case is not shown.

Data is read from the data memory 4 by random read, and the address control memories 6-1 to 6-3 respectively output lines 7-1 to 7-1.
Addresses to be sent to -3 compatible time slots are stored, and the addresses are used to sequentially correspond to the outgoing lines 7-1 to 7-3 in accordance with the clock signal from the data memory 4 at a high speed, for example, in accordance with a clock signal which is the number of outgoing lines. Read the data, write the data in sequence to the output side buffer memories 5-1 to 5-3,
The output side buffer memories 5-1 to 5-3 are provided by clock signals corresponding to the transmission speeds of the respective output lines 7-1 to 7-3.
The data is read from and sent out.

In this case, the structure of sequential write and random read is shown, but it is of course possible to adopt the structure of random write and sequential read.
In addition, the channel pulse generators 3-1 to 3-3 are previously connected to the input line 1
Since the effective time slot corresponding to -1 to 1-3 (the time slot corresponding to the channel for actually transmitting data) is known, the channel pulse indicating the effective time slot is output. The channel pulse is used to write the data of the valid time slot to the input side buffer memories 2-1 to 2-3, or the channel pulse is used to read the data of the valid time slot from the input side buffer memories 2-1 to 2-3. It can be input to the data memory 4.

FIG. 2 is a diagram for explaining the operation of the embodiment of the present invention. The same reference numerals as those in FIG. 1 denote the same parts. For example, the input side buffer memories 2-1 to 2-1 corresponding to the input lines 1-1 to 1-3. 2-
In Fig. 3, data A1 to A4, B1 to B1 corresponding to time slots when one frame consists of four time slots, respectively.
Assuming that B4 and C1 to C4 are written, first, the data A1 for one frame from the input side buffer memory 2-1 at high speed.
To A4 are read out and sequentially written from the top address of the data memory 4, then the data B1 to B4 for one frame are read out at high speed from the input side buffer memory 2-2 and written from the next address of the data memory 4 in order. Next, the data C1 for one frame from the input side buffer memory 2-3 at high speed
C4 is read and written from the next address of the data memory 4 in order. That is, the data corresponding to the incoming lines 1-1 to 1-3 is written in the data memory 4 by sequential writing.

Address control memories 6-1 to 6-1
-3 (see FIG. 1) holds the storage address of the data memory 4 for the data to be output corresponding to each of the outgoing lines 7-1 to 7-3. For example, for outgoing line 7-1,
Data A2 of the second time slot of incoming line 1-1, data B2 of the second time slot of incoming line 1-2, and incoming line 1-
One frame of the data C4 of the third time slot of No. 3 and the data A1 of the first time slot of the incoming line 1-1,
The data is sequentially read out from the data memory 4 at a high speed, temporarily written in the output side buffer memory 5-1 and read out by a clock signal according to the transmission speed of the output line 7-1 and sent out.

Next, from the data memory 4, the data B4 of the fourth time slot of the input line 1-2, the data A3 of the third time slot of the input line 1-1, and the data C2 of the second time slot of the input line 1-3. And the data C of the first time slot
One frame of 1 and 1 are read at high speed, once written in the output side buffer memory 5-2, read out by a clock signal according to the transmission speed of the output line 7-2, and sent out.

Next, from the data memory 4, the data C3 of the third time slot of the input line 1-3, the data B3 of the third time slot of the input line 1-2, and the data A4 of the fourth time slot of the input line 1-1. And one frame of data B1 of the first time slot of incoming line 1-2 are read at high speed,
The data is temporarily written in the output side buffer memory 5-3, read out by the clock signal according to the transmission speed of the output line 7-3, and sent out.

As described above, the data memory 4, the input side buffer memories 2-1 to 2-3 and the output side buffer memories 5-1 to 5-3 for speed conversion are used as the conventional TS-S-.
Similar to the T-configuration cross-connect device, an arbitrary incoming line 1-
The desired outgoing line 7-
The desired time slot of 1 to 7-3 can be replaced. Therefore, it is possible to reduce the size, and it is not necessary to provide a time switch corresponding to the incoming line, which results in an economical structure.

FIG. 3 is a diagram for explaining the operation by the channel pulse according to the embodiment of the present invention. The same reference numerals as those in FIG. 1 denote the same parts, and the input side buffer memories 2-1 to 2-3 have the channel pulse CP1. .About.CP3, only the data designated as the valid time slot is written, sequentially read from each of the input side buffer memories 2-1 to 2-3 at a high speed, and written to the data memory 4.

Therefore, the data A1 and A2 of the first and second time slots TS1 and TS2 are written in the input side buffer memory 2-1 by the channel pulse CP1, and the input side buffer memory 2 is written by the channel pulse CP2. -2, the data B2 of the second time slot TS2 is written, and the channel pulse CP3 writes the data C3 of the third time slot TS3 to the input side buffer memory 2-3. In this case, 24 of TS1 to TS24
The case where one frame is formed by time slots is shown, and a1, b1, and c1 respectively indicate the data of the time slot TS1 of the next frame.

In the data memory 4, the valid time slot data A1, read from the input side buffer memories 2-1 to 2-3, in accordance with the address which is sequentially stepped from the start address 0000h (h = hexadecimal display). A2, B2
C3 will be written. Therefore, the required storage capacity of the data memory 4 can be reduced. The access address of the data memory 4 stored in the address control memory 6-1 is 0003h, 0002 as shown in the figure.
In the case of h, 0000h, and 0001h, the output buffer memory 5-1 corresponds to the time slots TS1 to TS4,
Data C3, B2, A1 and A2 are written. And
Data is read from the output side buffer memory 5-1 by a clock signal corresponding to the transmission speed of the output line and transmitted.

FIG. 4 is a diagram for explaining the operation by the channel pulse according to the embodiment of the present invention. Channel pulses CP1 to CP3 in FIG. 3 are input side buffer memories 2-1 to 2-.
3, the data of the effective time slot is written, and the channel pulses CP1 to CP3 of this embodiment are written.
Is used to read only the data of the valid time slot from the data of the time slots TS1 to TS24 once written in the input side buffer memories 2-1 to 2-3 and write it in the data memory 4. Therefore, also in this case, the storage capacity of the data memory 4 can be reduced.

Although the channel pulses CP1 to CP3 may have the same timing, for example, in the order of the input side buffer memories 2-1 to 2-3, high speed reading is sequentially performed at that timing to perform the data memory. You can write in 4. Therefore, the channel pulse CP1 has time slots TS1 and TS3 as effective time slots, the channel pulse CP2 has time slot TS2 as an effective time slot, and the channel pulse CP3 has time slot TS3 as an effective time slot. With respect to the data of TS1, the data A1 corresponding to the time slot TS1 of the input side buffer memory 2-1 is read by the channel pulse CP1 and written to the address 0000h of the data memory 4.

For the data of the next time slot TS2, the data B2 corresponding to the time slot TS2 of the input side buffer memory 2-2 is read by the channel pulse CP2 and written to the address 0001h of the data memory 4. For the data of the next time slot TS3, the data A3 corresponding to the time slot TS3 of the input side buffer memory 2-1 is read by the channel pulse CP1 and written to the address 0002h of the data memory 4, and then the channel The data C3 corresponding to the time slot TS3 of the input side buffer memory 2-3 is read by the pulse CP3 and written in the address 0003h of the data memory 4. Therefore, even when the same time slot TS3 is used as an effective time slot, it is possible to write to the data memory 4 at a high speed corresponding to the incoming lines 1-1 to 1-3 and write only the data of the effective time slot to the data memory 4. it can.

The address control memory 6-
The address stored in 1 is 0003
If h, 0001h, 0000h, and 0002h, the data read from the data memory 4 at high speed is written in the output buffer memory 5-1. Therefore, as shown in the figure, the data C3 corresponding to the time slots TS1 to TS4 is written. ，
The data becomes B2, A1, and A3, and the data is read and transmitted according to the clock signal corresponding to the transmission speed of the outgoing line.

FIG. 5 is a diagram for explaining the operation when all the time slots are valid according to the embodiment of the present invention, and the same reference numerals as those in FIG. 1 indicate the same parts. With respect to each frame of the time slots TS1 to TS24, the input side buffer memories 2-1 to 2-3 are time slots corresponding data A1 to A24, B1 to B24, C1 to C2, which are valid time slots.
4 is written, and the data A1 to A2 corresponding to the time slots TS1 to TS24 from the input buffer memory 2-1 at high speed.
4 is read out and the address of the data memory 4 from 0000h to
Write to 0017h.

Then, the data B1 to B24 corresponding to the time slots TS1 to TS24 are read out at high speed from the input side buffer memory 2-2, and the address 0 of the data memory 4 is read.
Then, the data C1 to C24 corresponding to the time slots TS1 to TS24 are read out from the input side buffer memory 2-3 at high speed and written to the addresses 0030h to 0047h of the data memory 4.

Address control memories 6-1 to 6
-3 stores the address shown in the figure, first, the address 0 read from the address control memory 6-1 is read.
According to 030h, 0018h, 0000h, ...
Data C1, B1, A1, ... A from the data memory 4
22 is read at a high speed and once written in the output side buffer memory 5-1.

Similarly, the addresses 0031h, 0019h, read from the address control memory 6-2,
In accordance with 0001h, ..., The data C2, B2, A2, ... A23 are read from the data memory 4 at a high speed, temporarily written in the output side buffer memory 5-2, and then the address 0032 read from the address control memory 6-3.
The data C3, B3, A3, ... A24 are read from the data memory 4 at high speed according to h, 001Ah, 0002h ,.

Then, the output side buffer memories 5-1 to 5-
The data is read out and sent out according to the clock signal corresponding to the transmission speed of the outgoing line from 3. In this case, for example,
-1 first time slot TS1 is replaced with the third time slot TS3 of the outgoing line 7-1 and the second time slot TS2 of incoming line 1-1 is replaced with the third time slot TS3 of the outgoing line 7-2. Become. 1 time slot is 6
Assuming 4 kbps, the transmission speed of incoming and outgoing lines is 1.
It will be 544 Mbps. At that time, as for the writing and reading speeds to and from the data memory 4, since the number of incoming lines and the number of outgoing lines are three, respectively, from the incoming side buffer memories 2-1 to 2-3 based on a clock signal of 4.6 Mbps which is three times as high. The data is read and written in the data memory 4, and the data is read from the data memory 4 based on the clock signal of 4.6 Mbps and written in the output side buffer memories 5-1 to 5-3.

FIG. 6 is a diagram for explaining the operation of the branch line according to the embodiment of the present invention. The same reference numerals as those in FIG. 1 denote the same parts, and show the case where the low speed line is branched from the high speed line. That is, FIG.
In the same manner as in the case shown in FIG.
Every time one frame of data in the time slots TS1 to TS24 is written in 3, the data is read out at high speed and sequentially written in the data memory 4.

For example, the incoming line 1-1 is 1.544 Mbps
When the outgoing line 7-1 has a transmission rate of 64 kbps and the outgoing line 7-1 has a transmission rate of 64 kbps, when the outgoing line 7-1 is branched from the incoming line 1-1, it corresponds to the time slots TS1 to TS24 of the address control memory 6-1. The same address of the data memory 4, for example, 0000h is stored in the address, and the data memory 4 is accessed by the same address 0000h read from the address control memory 6-1 to access the input side buffer memory 2-1. The data A1 of the time slot TS1 is read and shown as the data a1 of the time slot TS1 in the next frame. Therefore, the contents of the output buffer memory 5-1 are the data a1 read from the data memory 4 after the data A1 is read. Will be written. In addition, the time slot TS of the incoming line 1-1
When the data A2 of No. 2 is branched to the output line 7-1, 0001 is assigned to each address of the address control memory 6-1.
will hold h.

FIG. 7 is a diagram for explaining the operation of the branch line according to the embodiment of the present invention. The difference from FIG. 6 is that the access address 0000h to the data memory 4 is stored at the head address of the address control memory 6-1. However, the case where the access address is not stored in another address is shown. Therefore, in this case, the data A1 of the time slot TS1 written at the start address 0000h of the data memory 4 is read, and the data a1 of the time slot TS1 is read in the next frame. That is, 2
Data is read from the data memory 4 once every four times. Therefore, the data A is stored in the output buffer memory 5-1.
After 1 is written and the data A1 is read, the data a1 of the next frame is written. Thereby, 1.
Data can be branched from the line of 544 Mbps to the line of 64 kbps.

[0038]

As described above, the present invention mainly includes the input side buffer memories 2-1 to 2-3, the data memory 4, and the output side buffer memories 5-1 to 5-3. The incoming line 1-1 to the incoming buffer memories 2-1 to 2-3.
Data of at least one frame corresponding to 1 to 3 is written, read at a speed of the number of incoming lines and sequentially written to the data memory 4, and data is read at a time of the outgoing line corresponding to the time slot of the outgoing line. Output buffer memory 5
Write once in -1 to 5-3 and output lines 7-1 to 7
-3 for reading and transmitting data according to the transmission speed, and has a configuration similar to that of the conventional time switch, but has a plurality of incoming lines 1-1 to 1-3 and a plurality of outgoing lines 7-1 to 7
-3 has the advantage that the common data memory 4 can be used for cross-connecting and downsizing and economy can be achieved.

[Brief description of drawings]

FIG. 1 is an explanatory diagram of a cross-connect device according to an embodiment of the present invention.

FIG. 2 is an operation explanatory diagram of the embodiment of the present invention.

FIG. 3 is an operation explanatory diagram with channel pulses according to the embodiment of the present invention.

FIG. 4 is an explanatory diagram of an operation using a channel pulse according to the embodiment of the present invention.

FIG. 5 is an explanatory diagram of an operation in the case where all time slots are valid according to the embodiment of this invention.

FIG. 6 is an operation explanatory diagram of a branch line according to the embodiment of the present invention.

FIG. 7 is an operation explanatory diagram of a branch line according to the embodiment of the present invention.

FIG. 8 is an explanatory diagram of a conventional cross-connect device.

[Explanation of symbols]

1-1 to 1-3 Input line 2-1 to 2-3 Input side buffer memory (BF) 3-1 to 3-3 Channel pulse generator (CP) 4 Data memory (DM) 5-1 to 5-3 Output Side buffer memory (BF) 6-1 to 6-3 Address control memory (AC
M) 7-1 to 7-3 outgoing line

─────────────────────────────────────────────────── ─── Continuation of the front page (56) Reference JP-A-55-21662 (JP, A) JP-A-62-274999 (JP, A) JP-A 58-148586 (JP, A) JP-A 58- 129898 (JP, A) JP-A-6-29970 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) H04Q 11/06 H04Q 3/52 101

Claims (6)

(57) [Claims] The method according to claim 1, wherein each time slot of a plurality of incoming lines, in the cross-connect device into a plurality of selected time slots of the selected outgoing line in the outgoing line, provided on the plurality of incoming lines corresponding Te, entering-and entry side buffer memory for writing data in at least one frame of time slots, respectively, the data of the one frame of time slot read out at a higher speed than the speed of the entering line corresponding from the entry side buffer memory A data memory for writing to a line-corresponding address, and reading and writing the data of the time slot corresponding to the output line from the data memory at a speed higher than the speed corresponding to the output line ,
A cross-connect device comprising an output buffer memory for reading data at a speed corresponding to an output line, and an address control memory corresponding to an output line for sequentially outputting read addresses of the data memory. 2. The data memory is provided with a channel pulse generating section for inputting a channel pulse for writing only data of an effective time slot corresponding to the incoming line to the incoming side buffer memory. Item 1. The cross-connect device according to item 1. 3. The channel pulse generating section has a configuration for generating a channel pulse for writing only data of an effective time slot corresponding to the incoming line into the incoming side buffer memory. The cross-connect device described. 4. The channel pulse generator writes channel pulse data for each time slot corresponding to the incoming line to the incoming side buffer memory sequentially and reads out only the data of the valid time slot from the incoming side buffer memory. The cross-connect device according to claim 2, wherein the cross-connect device has a configuration for generating it. 5. The data memory according to claim 1, wherein the data is written from the input side buffer memory at a speed which is at least a multiple of the number of incoming lines with respect to the transmission speed of the incoming line. Cross-connect device. 6. The data memory is configured to read data from the data memory at a speed that is at least a multiple of the outgoing line speed and write the data into the outgoing buffer memory. Item 1. The cross-connect device according to item 1.