JP3458370B2 - Resonant converter - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a so-called voltage resonance type converter, and more particularly to an improvement for realizing stable operation with high efficiency by making an oscillation frequency substantially constant.

[0002]

2. Description of the Related Art The applicant of the present application has proposed a discontinuous mode current resonance type converter having a period in which no current flows, as disclosed in Japanese Patent Laid-Open No. 3-18274. In such a circuit configuration, the output parasitic capacitance of the switch element and the inductance of the transformer resonate the voltage applied to the switch element in the discontinuous mode of the flyback converter type switching power supply. In order to reduce the switching loss of the switching power supply, the turn-on / off is performed when either the voltage or the current is zero.

[0003]

However, according to the conventional structure, the oscillation frequency fluctuates greatly due to the fluctuations of the input voltage and the load, and it is difficult to secure stable operation. For example, in a light load state, when the switch element is turned off at the first zero voltage of resonance, the oscillation frequency becomes extremely high. On the other hand, at startup or overload,
Since the energy to be supplied to the load side increases, if the current peak value is kept constant, it becomes necessary to widen the pulse width, and the oscillation frequency drops extremely.

The present invention has been made to solve the above-mentioned problems. The switching loss is reduced and the input voltage is reduced by utilizing the resonance of the voltage applied to the switch element due to the output parasitic capacitance of the switch element and the inductance of the transformer. It is an object of the present invention to provide a resonant converter whose oscillation frequency is stable even when the load or load changes.

[0005]

(1) A resonant converter that obtains a main output voltage by rectifying and smoothing a switching signal induced by turning on / off a main switching element,
A zero voltage detector that outputs a trigger signal at the time when the resonance voltage applied to the main switching element becomes the lowest, and a light load that generates a mask signal that determines the period of resonance between the capacitance component and the inductance of the main switching element. An ON-time setting unit, a heavy-load ON-time setting unit that outputs a resonance number fluctuation width signal at the same time when the mask signal is turned OFF, and the trigger signal is invalid while the mask signal is valid,
The trigger signal in the discontinuous mode or the continuous mode
Wherein to turn on the main switching element based on either the time-up of the resonance speed fluctuation width signal that the on-period control unit, based on a comparison between the main output voltage and a reference voltage, turning off the main switching element pulses And a width control unit. (2) A flyback converter system in which a DC voltage applied to a primary winding of a transformer is turned on / off by a main switching element, and a switching signal induced in a secondary winding of the transformer is rectified and smoothed to obtain a main output voltage . Resonance type
A converter, the enter the switching signal induced in the bias winding of the transformer, and the main zero voltage detector for outputting a trigger signal to the most lowered timing of the switching element resonant voltage applied to said main A light load ON setting unit that generates a mask signal that determines the minimum value of the resonance number of the capacitance component of the switching element and the inductance of the primary winding, and a resonance number variation width that determines the number of variations from the minimum value of the resonance number. A heavy load on-time setting unit that outputs a signal, a mode switching unit that alternately outputs the mask signal and the resonance number fluctuation width signal, and while the mask signal is valid, while disabling the trigger signal, After the mask signal is valid , the trigger signal or continuous mode in discontinuous mode is used.
Mode, which turns on the main switching element at a time when any one of the time-ups of the resonance number fluctuation width signal that is the first mode is turned on, based on a comparison between the ON period control unit and the main output voltage and the reference voltage, A pulse width controller for turning off the main switching element.

(3) The on-period control section is characterized in that the on-state of the main switching element is continued even when the trigger signal is input when the main switching element is in the on state ( The resonant converter according to either 1) or (2). (4) The resonant converter according to any one of (1) and (2), further including an OR circuit for the mask signal and the Q output of the ON period control unit . (5) A maximum on-period setting unit that starts a trigger mask period at the same time as turning on the main switching element and turns off the main switching element when a time elapses is provided. (1) to (4) ) A resonant converter according to any one of the above. (6) A delay circuit is provided between the light load ON time setting unit and the ON period control unit, and a delay circuit is provided to provide a delay for the capacitor of the light load ON time setting unit to be sufficiently discharged ( The resonant converter according to any one of 1) to 5).

[0007]

According to the structure of the present invention, the zero voltage detecting section 10 is
It outputs a trigger signal corresponding to the turn-on timing that minimizes switching loss. When the light load is ON, the setting unit 21
A mask signal that determines the minimum value of the LC resonance number of the switching element and the transformer is generated to determine the upper limit of the oscillation frequency. The heavy load on-time setting unit 23 generates a resonance number fluctuation width signal that determines the fluctuation width of the LC resonance number, and determines the fluctuation width of the oscillation number. The mode switching unit 24 outputs the resonance number fluctuation width signal after the mask signal, thereby substantially defining the lower limit of the oscillation frequency.

The ON period control section 30 invalidates the trigger signal while the mask signal is valid to prevent the resonance frequency from becoming excessively high, and after the lapse of the period determined by the mask signal, trigger signal or resonance. The main switching element is turned on according to whichever of the time fluctuations of the number fluctuation width signal becomes valid first. Here, when the trigger signal is the first arrival, it is called the discontinuous mode, and when the zero voltage detection unit 10 minimizes the switching loss and the resonance frequency fluctuation width signal reaches the first arrival, it is called the continuous mode. The oscillation cycle is limited to the upper limit of the period in which the mask signal and the resonance number fluctuation width signal are added. The pulse width control unit 40 stabilizes the main output voltage by determining when to turn off the main switching element.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings. Figure 1
FIG. 3 is a configuration block diagram showing an embodiment of the present invention. In the figure, a commercial AC power supply is connected to a diode bridge DB via an input filter. The input filter prevents noise components from being superimposed on the supplied alternating current.
The current rectified by the diode bridge DB is smoothed by the input capacitor C1, and the primary winding N of the transformer is
1 is applied. The main switching element Q1 is an FET here, and turns on / off between the drain terminal and the source terminal according to an on / off control signal applied to the gate terminal. The parasitic capacitance C0 is generated between the drain terminal and the source terminal of the FET during manufacturing, and has LC resonance with the inductance of the transformer. The resistor R2 is a current detection resistor that grounds the source terminal of the FET.

Since a switching signal is induced in the secondary winding N2 of the transformer, it is rectified by the diode D2 and smoothed by the output capacitor C2 to obtain the main output voltage Vout. Since a switching signal is also induced in the bias winding N3, it is rectified by the diode D3, and the capacitor C3 is rectified.
To obtain the auxiliary power supply voltage Vcc.

The zero voltage detector 10 inputs the switching signal generated in the bias winding N3 and outputs a trigger signal which coincides with the time when the resonance voltage applied to the main switching element Q1 becomes the lowest. Here, the anode terminal of the diode D4 is connected to the bias winding N3, and the cathode terminal is connected to the base terminal of the transistor Q2 via the resistor R5. The capacitor C4 is connected between the collector terminal and the emitter terminal of the transistor Q2, the resistor R6 has one end connected to the collector terminal of the transistor Q2, and the other end connected to the reference voltage source Vref3. Capacitor C4
And the time constant of the resistor R6 is delayed by a quarter of the resonance period. This is because the voltage appearing in the bias winding N3 is at the point where 1/2 of the resonance amplitude is the ground, so the transistor Q2
This is because the timing at which the zero voltage is detected and turned off is earlier than the lowest point of the resonance voltage applied to the main switching element Q1 by a quarter cycle.

The light load ON time setting unit 21, the heavy load ON time setting unit 23, and the mode switching unit 24 are LC resonances generated between the parasitic capacitance C0 of the main switching element Q1 and the inductance of the transformer having the primary winding N1. In this case, the mask signal of the light load on-time setting unit 21 determines the minimum value of the LC resonance number, and the resonance number fluctuation width signal of the heavy load on time setting unit 23 indicates the fluctuation range of the LC resonance number. The mode switching unit 24 outputs the resonance number fluctuation width signal after the mask signal, thereby determining the maximum value of the oscillation cycle. Here, the LC resonance number is the LC resonance wave number within a certain time of the turn-off period, and the resonance frequency is the LC resonance wave number for 1 second. The oscillation frequency means the number of times of switching of the main switching element Q1 per second, and one cycle of this oscillation is [turn-on period] + [turn-off period].

The light load on-time setting unit 21 is provided with a constant current source CC1 capable of varying a current value, and a bias unit 211
A constant current value is set by the current setting resistor R7 connected to. The FET Q3 has a drain terminal connected to the constant current source CC1, and when the FET Q3 is turned off, the constant current source C
The capacitor C5 is charged by C1. Comparator C
P1 compares the voltage of the capacitor C5 with the reference voltage Vref1, and when the charging voltage becomes higher than the reference voltage Vref1, the output becomes H. The trigger mask period is defined by the time for charging the capacitor C5 to the reference voltage Vref1 by the constant current source CC1.

The heavy load-on setting unit 23 is provided with a constant current source CC2 whose current value can be varied, and a bias unit 211.
The current setting resistor R7 and the current setting resistor R7 are common to the light load ON setting unit 21. The drain terminal of the FET Q4 is a constant current source C
It is connected to C2, and when the FET Q4 is turned off, the constant current source CC2 charges the capacitor C6. The comparator CP2 compares the voltage of the capacitor C6 with the reference voltage Vref2.
When the charging voltage becomes higher than the reference voltage Vref2, the output is set to H. The period of the resonance number fluctuation width signal is determined by the time taken to charge the capacitor C6 to the reference voltage Vref2 by the constant current source CC2.

The mode switching unit 24 has an RS flip-flop 241, an OR circuit 242, a delay circuit 243, an inverter circuit 244 and an OR circuit 245. R
The S flip-flop 241 has a comparator C at the S terminal.
The output signal of P1 is input, and the OR circuit 245 is connected to the R terminal.
Is input, and the Q terminal is connected to the gate terminal of the FET Q3. The OR circuit 242 receives the Q output signal from the D-type flip-flop 31 and the RS flip-flop 2
The delay circuit 243 is ORed with the Q output signal of 41.
Output to. The delay circuit 243 delays the time signal corresponding to the discharge time of the capacitor C5, and is, for example, 10
Delay 0 nS. The inverter circuit 244 performs a negative operation on the Q output signal of the RS flip-flop 241 and is connected to the gate terminal of the FET Q4. Since the FETs Q3 and Q4 are alternately turned on by the inverter circuit 244, the timer signal τ1 and the resonance number fluctuation width signal τ2 are set respectively. The OR circuit 245 includes a Q output signal of the D flip-flop 31 and the comparator CP.
The output signal of 2 is ORed.

The ON period control unit 30 invalidates the trigger signal output from the zero voltage detection unit 10 while the mask signal generated by the light load ON time setting unit 21 is valid, and the period during which the mask signal is valid. After the passage of, the main switching element Q1 is turned on at the time when the trigger signal or the resonance frequency fluctuation width signal is timed up, whichever comes first. Here, the trigger signal is input to the clock terminal of the D-type flip-flop 31, the resonance number fluctuation width signal output from the comparator CP2 is input to the S terminal, and the Q output is the main switching element Q1 via the amplifier and the resistor R1. It is connected to the base terminal of. The mask signal output from the delay circuit 243 is input to the D terminal, and the output terminal of the maximum on-period setting unit 43 is connected to the R terminal.
Further, the Q output is also connected to the input terminals of the OR circuits 242 and 245.

The pulse width controller 40 controls the main output voltage Vout.
Is compared with the reference voltage Vref2 to determine the time when the main switching element Q1 is turned off so as to stabilize the main output voltage Vout at a predetermined voltage. Here, in order to ensure insulation between the primary side and the secondary side of the transformer, the auxiliary power supply voltage Vcc having a value proportional to the main output voltage Vout is divided by the voltage dividing resistors R3 and R4, and the error amplifier 41 is used. It is compared with the reference voltage Vref2. The minus terminal and the output terminal of the error amplifier 41 are connected by a capacitor C7. The correction circuit 42 corrects the output signal of the error amplifier 41 and reduces, for example, a limiter circuit that limits the error voltage and the input voltage dependency of the load current. Comparator C
P3 compares the error voltage signal of the correction circuit 42 with the source voltage of the main switching element Q1. This comparison signal is D
The main switching element Q1 is turned off by sending it to the R terminal of the type flip-flop 31.

Here, the maximum ON period setting section 43 is inserted between the comparator CP3 and the R terminal of the D-type flip-flop 31, and the logical sum of the output signal of the comparator CP3 and the output signal of the comparator CP1 is obtained. , Maximum on time is set. If the current waveform disappears at the positive terminal of the comparator CP3 for some reason,
Because the ON period becomes extremely long during startup or overload,
It may damage the power supply itself or the connected load. Therefore, using the output signal of the comparator CP1, when the trigger mask time has elapsed, the main switching element Q1 is forcibly turned off regardless of the operation of the pulse width control unit 40.

The operation of the thus constructed device will be described below. The light load on-time setting unit 21 resets the RS flip-flop 241 by the Q output signal of the D-type flip-flop 31 in order to start setting the trigger mask period at the same time when the main switching element Q1 is turned on.
ETQ3 is turned off to start charging the capacitor C5. In the discontinuous mode, the main switching element Q1 may be turned on immediately after the end of the trigger mask period. At this time, if charging is started again while the capacitor C5 is not sufficiently discharged, the trigger mask period becomes short and the oscillation frequency remarkably changes. The delay circuit 243 reliably waits until the capacitor C5 is fully discharged to zero voltage, so that a stable oscillation frequency can be obtained. Preferably, when MOSFET is used for FETQ3, the discharge time is short.

Since the heavy load ON time setting unit 23 outputs the resonance number fluctuation width signal at the same time when the mask signal is turned OFF,
When the mask signal is timed up by the output signal of the comparator CP1, the RS flip-flop 241 is set, the FET Q4 is turned off, and the charging of the capacitor C6 is started. That is, the mode switching unit 24 alternately sets the mask signal τ1 and the resonance number fluctuation width signal τ2. In the operation of the RS flip-flop 241, when the signal from the comparator CP1 is input to the S terminal, the output Q becomes H.
When the signal enters the R terminal, the output Q has the property of becoming L. The output Q of the RS flip-flop 241 is the FET Q
FE through the gate terminal of 3 and the inverter circuit 244
By connecting to the gate terminal of TQ4, Q3 and Q4
Are alternately turned on and off, so that the mask signal τ1 and the resonance number fluctuation width signal τ2 are alternately set.

The ON period control section 30 operates to control the oscillation frequency to be substantially constant. If only the zero voltage detection unit 10 is used, the main switching element Q1 is turned on at the first zero voltage at which resonance is always started. Then, when the input voltage or the load fluctuates and the switching time largely fluctuates, the oscillation frequency also fluctuates greatly. Therefore, the upper limit of the oscillation frequency is set using the mask signal output from the light load on-time setting unit 21.

First, when the main switching element Q1 is off during the trigger mask period, the D-type flip-flop 3
Since the D terminal of 1 is in the L state, the Q output signal holds the L state even if the trigger signal is input to the clock terminal.
That is, the trigger signal is invalid during the trigger mask period. When the trigger mask period ends, the D terminal of the D flip-flop 31 shifts to the H state. In the discontinuous mode, a phenomenon in which a resonance voltage is applied to the main switching element Q1 appears, so that the main switching element Q1 turns on after the trigger signal for zero voltage detection is input. Therefore, when a trigger signal is input to the clock terminal of the D-type flip-flop 31, the Q output signal changes to the H state and the main switching element Q1 turns on.

Next, the continuous mode will be described. The continuous mode, which appears when the power supply is started up or in an overload state, is characterized by the fact that no resonance phenomenon appears in the main switching element Q1, and a trigger signal for zero voltage detection is input immediately after the main switching element Q1 is turned on. To be done. Therefore,
When the main switching element Q1 is in the ON state and the output Q of the D-type flip-flop 31 is in the H state, it is necessary to maintain the ON state of the main switching element Q1 even if the zero voltage detection trigger signal is input. Because there is, OR circuit 2
42 is provided. Without the OR circuit 242, the D terminal of the D-type flip-flop 31 is in the L state immediately after the main switching element Q1 is turned on. Therefore, when the trigger signal enters the clock terminal, the Q output changes from H to L. However, the inconvenience arises that the main switching element Q1 which has been turned on at all times is immediately turned off.

The operation of the power supply device will now be described with reference to the flow chart and the waveform chart. FIG. 2 is an explanatory view of the operation of the apparatus of FIG. 1 in the discontinuous mode and the continuous mode. FIG. 3 is a waveform diagram of the discontinuous mode, and FIG. 4 is a waveform diagram of the continuous mode. In FIGS. 3 and 4, (A) shows the drain current I _D of the main switching element Q1 and the drain-source voltage V _DS ,
(B) is the voltage V _FB induced in the bias winding N3,
(C) shows the trigger signal, (D) shows the charging voltage of the capacitors C5 and C6, and (E) shows the D terminal, S terminal, R terminal and Q output terminal signal (OUT) of the D-type flip-flop 31.

First, the main switching element Q1 is turned off at the timing of (S10). Next, if the current flowing through the transformer is zero, the discontinuous mode is set, and if it is non-zero, the continuous mode is set. Therefore, a branch is made as to whether or not the trigger signal for zero voltage detection operates effectively (S11). . First, in the discontinuous mode, the drain of the main switching element Q1
The source-to-source voltage V _DS resonates with the primary winding N1 of the transformer and the parasitic capacitance C0 (). And the bias winding N
The following voltage V _FB is induced in 3. V _FB = (n3 / n1) × V _DS (1) The ground of the bias winding voltage V _FB is the primary winding N
It is the boundary between the input voltage Vin applied to No. 1 and the main output voltage Vout of the secondary winding N2 (S12).

Subsequently, the trigger signal and the resonance number fluctuation width signal τ
It is compared which of the two arrives first (S13). The trigger signal is the drain of the main switching element Q1 due to resonance.
The voltage is output from the zero-voltage detector 10 at the lowest point of the source-to-source voltage V _DS , and the first-arrival mode is the discontinuous mode. The resonance frequency fluctuation width signal τ2 is output from the converter CP2 when the charging voltage of the capacitor C6 reaches the threshold voltage Vref2, and is the continuous mode if it is the first arrival.

If the trigger signal is first-arrival, when the bias winding voltage V _FB reaches the minimum voltage (S14), the zero voltage detector 10 turns off the transistor Q2 (S16). Then, in the zero voltage detection unit 10, the capacitor C4 and the resistor R6 are
By the action of, the trigger signal is delayed by a quarter of the resonance period represented by 2π (L ₁ C ₀ ) ^1/2 (), and the trigger signal becomes the D-type flip-flop 3.
It is input to the clock terminal 1 (S18). At this time,
If the D terminal of the D-type flip-flop 31 is in the L state, S
Returning to step 11, if the mode is discontinuous, the process waits until the H state is reached (S20). The time up of the mask signal τ1 is
When the charging voltage of the capacitor C5 reaches the threshold voltage Vref1, the voltage is output from the converter CP1, and the H state is set at the timing. Here, when the trigger signal is input to the clock terminal, the Q output terminal signal (OUT) of the D-type flip-flop 31 becomes H, and the main switching element Q1 is turned on (S22). At this time, D terminal is H
Maintain state ().

At the timing of, the pulse width control circuit 40
A signal for stopping the pulse is applied to the R terminal of the D flip-flop 31 (S24). Then, the Q output terminal signal (OUT) of the D-type flip-flop 31 becomes L (S26), the D terminal also becomes L state (S28), the main switching element Q1 is turned off (S30), and one cycle ends. To do.

Now, the branch to the continuous mode will be explained.
To do. When branching to the continuous mode in S11, the fluctuation range of the resonance number
It is determined whether the signal τ2 has timed up (S32). This
Is determined by the charging voltage of the capacitor C6 and the threshold voltage V
By comparison with ref2. Next, the D-type flip-flop 31
The potential of the S terminal of turns to H at the timing of '(S3
4). Then, the Q output terminal signal (OUT) becomes H,
The main switching element Q1 is turned on (S36). In addition,
The D terminal also maintains the H state. Then the bias winding voltage
V_FBIs zero (S38), transistor Q2 is off
Yes (S40). Then, in the zero voltage detecting section 10,
By the action of the sensor C4 and the resistor R6, 2π (L ₁C₀)^1/2Represented by
Delayed by a quarter of the resonance period (), the trigger signal is D type
Input to the clock terminal of the flip-flop 31 (S
42). At this time, the D terminal of the D-type flip-flop 31
Maintains the H state, the process proceeds to S24 (S4
4).

In the above embodiment, when the output voltage of the pulse width control circuit 40 is stabilized, the auxiliary power supply voltage Vcc obtained from the bias winding N3 is input instead of the main output voltage Vout. It does not matter if the output voltage Vout is fed back. In this case, a transformer or a photocoupler is used to ensure insulation between the primary side and the secondary side.

[0031]

As described above, according to the present invention,
The zero voltage detection unit 10 outputs a trigger signal corresponding to the turn-on timing that minimizes the switching loss, and the light load on-time setting unit 21 generates a mask signal that determines the minimum value of the LC resonance numbers of the switching element and the transformer. Since the trigger signal is invalidated while the mask signal is valid via the ON period control unit 30, it is possible to prevent the resonance frequency from being excessively increased. In addition, when the heavy load is turned on, the setting unit 22 sets the LC of the switching element and the transformer.
Generates a resonance frequency fluctuation range signal that determines the fluctuation range of the resonance frequency, allows fluctuations in the resonance frequency within this range, and realizes low-loss switching in the discontinuous mode when supplying normal load current. is doing.

Further, since the heavy load ON time setting unit 22 and the ON period control unit 30 turn on the main switching element without waiting for the input of the trigger signal when the resonance frequency fluctuation width signal has timed up, the oscillation frequency is increased. It is possible to prevent the power supply voltage from becoming excessively low, and it is possible to prevent the main switching element from being damaged when the ON period during overload becomes extremely long by shifting to the continuous mode.

[Brief description of drawings]

FIG. 1 is a configuration block diagram showing an embodiment of the present invention.

FIG. 2 is an explanatory view of the operation of the apparatus of FIG. 1 in a discontinuous mode and a continuous mode.

3 is a waveform diagram in the discontinuous mode of the apparatus of FIG.

4 is a waveform diagram in the continuous mode of the apparatus of FIG.

[Explanation of symbols]

10 Zero voltage detector 21 Light load ON setting section 23 Heavy load ON setting section 24 Mode switching unit 30 ON period controller 40 pulse width control circuit

─────────────────────────────────────────────────── ─── Continuation of front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) H02M 3/28 H02J 1/00 H02M 1/08

Claims (6)

(57) [Claims] 1. A resonance type converter for rectifying and smoothing a switching signal induced by turning on / off of a main switching element to obtain a main output voltage, wherein a trigger signal is generated when a resonance voltage applied to the main switching element becomes the lowest. A zero voltage detection unit that outputs, a light load on-time setting unit that generates a mask signal that determines a period of resonance between the capacitance component and the inductance of the main switching element, and a resonance number fluctuation width signal at the same time when the mask signal is turned off. And a heavy load on-time setting unit that outputs, while the mask signal is valid, while disabling the trigger signal, the trigger signal or the continuous signal in the discontinuous mode.
The main switching element is turned on based on any one of the time-ups of the resonance frequency fluctuation width signals that are in the mode, and the main switching element is turned off based on a comparison between the ON period control unit and the main output voltage and the reference voltage. And a pulse width control unit for controlling the resonance width. 2. A flyback converter for obtaining a main output voltage by turning on / off a DC voltage applied to a primary winding of a transformer by a main switching element and rectifying and smoothing a switching signal induced in a secondary winding of the transformer. co-scheme
A swing converter , which inputs a switching signal induced in the bias winding of the transformer, and outputs a trigger signal at the time when the resonance voltage applied to the main switching element becomes the lowest, A light load ON setting unit that generates a mask signal that determines the minimum value of the resonance number of the capacitance component of the main switching element and the inductance of the primary winding, and the resonance number that determines the number of fluctuations from the minimum value of the resonance number. A heavy load ON setting unit that outputs a fluctuation width signal, a mode switching unit that alternately outputs the mask signal and the resonance number fluctuation width signal, and disables the trigger signal while the mask signal is valid. Together with the trigger signal or continuation in discontinuous mode after the mask signal is valid.
The main switching element is turned on at a time when any one of the time-ups of the resonance number fluctuation width signal that is a continuous mode is valid first, based on a comparison between the ON period control unit and the main output voltage and the reference voltage, A resonant converter comprising: a pulse width control unit for turning off the main switching element. 3. The on-period controller is configured to control the main switch.
The trigger signal is input when the trigger element is on.
In this case, keep the main switching element in the ON state.
3. The method according to claim 1 or 2, wherein
Resonant converter. 4. The mask signal and Q of the ON period control section
2. An OR circuit with an output is provided.
Alternatively, the resonant converter according to claim 2. 5. The main switching device is turned on at the same time when it is turned on.
When the Rigamask period starts and the time elapses, the main
Maximum on-period setting unit that turns off the switching element
It is provided with any one of claims 1 to 4.
A resonant converter according to claim 1. 6. The light load ON time setting unit and the ON period control
It is placed between the control unit and the control unit, and delays when the capacitor of the light load ON setting unit is fully discharged.
A delay circuit for providing the delay is provided.
The resonant converter according to any one of claims 1 to 5.