JP3457453B2 - Coordinate transformation processing device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a coordinate conversion processing device, and more particularly to a coordinate conversion processing device for performing geometrical processing used for computer graphic processing and the like.

[0002]

2. Description of the Related Art In recent years, the rapid spread of multimedia, W
Thorough implementation of YSWYG, advanced GUI (Graphic User Int)
computer graphics (CG) due to the spread of TV games using graphics
Is becoming very important. In particular, due to the rapid spread of personal computers in homes and the spread of TV game machines, there is an increasing demand for three-dimensional computer graphics (3D-CG), especially high-quality moving images, as applications that run on high-performance processors. In order to process a moving image, it is necessary to process one frame in 30 to 1/60 second, and this process requires a huge amount of calculation and calculation ability.

Graphic processing by a computer is
There are two major phases. That is, movement of modeled data itself, transformation of coordinates such as movement according to a viewpoint, geometric processing for performing projection and geometric processing for generating an image projected on a CRT, and actual image processing for CRT. This is the rendering process that we will draw above. In geometrical processing, which is a phase of performing geometrical graphic model conversion processing such as coordinate conversion and viewpoint conversion, and illumination processing, matrix operations and vector operations are performed, and thus inner product operations are often used. Details of coordinate transformation are introduced in various documents of computer graphics.

FIG. 8 shows a typical coordinate conversion processing device (GT
The structure of E) is shown. The GTE is composed of an arithmetic unit 801, a register file 802, an internal storage device 803, an input / output interface 804, and the like. The calculation unit 801
This is a data path for matrix operations, and is composed of adder / subtractor, multiplier, divider, square root calculator, and the like. Internal storage device 80
3 temporarily stores the data stored in the external storage device in order to efficiently process the data, and also stores a constant such as a conversion matrix. I / O interface 804
Is an interface between the external storage device and the internal storage device 803, the register file 802, and the arithmetic unit 801.

1: Data Transfer 3D computer graphics data, though modeled, is generally treated as a collection of independent triangles. The three vertices of the independent triangle are represented by homogeneous coordinates and are stored in the external storage device.

Most of the conventional coordinate conversion processing devices do not have a large capacity storage device installed therein. Therefore, graphic data is read from an external storage device and sent to a data path such as an arithmetic unit or a register file through a FIFO or the like. This way, the latency of the bus,
The fluctuation of the data transfer rate due to the access speed of the storage device is hidden by using the FIFO as a buffer for input or output, but it is controlled by the access speed of the storage device and the response speed of the bus, and the transfer band is sufficient. The width cannot be secured.

On the other hand, an internal storage device is mounted to some extent,
There is a method of fetching data at high speed and performing calculation by DMA (Direct memory access). In an arithmetic unit of such a system, the internal storage device is accessed from the external storage device and the internal arithmetic unit and register file, so that it is difficult to perform data transfer and arithmetic operation in parallel. Therefore, the two processing phases of data transfer and data processing are alternately performed, and the processing cannot be efficiently executed in a pipeline manner. Further, although the data transfer becomes faster by the DMA, it is not possible to sufficiently speed up the whole process.

A configuration having a storage device having a plurality of ports is conceivable in order to perform parallel execution and improve processing efficiency with the same configuration. However, in this case, there is a problem that the control is remarkably complicated such as arbitration of access conflict to the same storage device and the cost of the storage device is also increased. Therefore, it is necessary to use a large-capacity storage device that can obtain sufficient processing performance. Cannot be implemented.

2: Transform processing Here, an example of a simple perspective transformation is shown before showing the conventional example. The perspective transformation is a transformation in which a three-dimensional figure model is projected in two dimensions in consideration of perspective. Now input (x, y,
Let z, 1) be the coordinates of the vertex to be transformed, the perspective transformation is performed as follows, and the screen X and Y coordinates after (X, Y) perspective transformation are output.

[0010] (2) W = 1 / w ′ (3) (X, Y) = (x ′, y ′) × W Thus, in perspective transformation, not only the product sum operation associated with matrix calculation but also the result is used. It is necessary to perform division. Also, the calculation for each coordinate of x, y, z, w is
They are almost the same and independent, and have the characteristic that they have a high degree of parallelism and symmetry regarding arithmetic operations.

In the typical conventional example shown in FIG.
Only one adder / subtractor is implemented. In such a conversion processing device, the above-described operations can only be sequentially processed by a simple pipeline process. The feature of having high parallelism and symmetry with respect to operations is utilized only in instruction scheduling.

As a configuration to which the characteristics relating to the calculation are applied,
There is a configuration as shown in FIG. In this configuration, x, y,
By associating each register of z and w with a register file and a product-sum calculator, calculation can be performed independently. That is, (1) (x ', y', w ') = (x, y, z, 1) × (a, b, c) (d, e, f) (g, h, i) (j, k, l) ＝ (ax + dy + gz + j, bx + ey + hz + k, cx + fy + iz + l) where ax + dy + gz + j is the first arithmetic unit, bx + ey + hz + k is assigned to the second computing unit and cx + fy + iz + l is assigned to the third computing unit,
Calculate independently. By considering the characteristics of the calculation in this way, high-speed calculation is possible. However, with such a configuration, the calculation of (2) W = 1 / w '(3) (X, Y) = (x', y ') x W cannot be performed efficiently. Since the division only needs to be performed once, a plurality of arithmetic units cannot be effectively used while the division is being performed. Moreover, since the latency of the division is larger than that of other arithmetic operations, there is a problem that particularly expensive plural arithmetic units cannot be effectively operated. However, such a configuration has a problem in that sufficient performance commensurate with the invested hardware cannot be obtained.

3: Illumination processing Further, in order to obtain a realistic image, the object is illuminated. In the following example, colors are represented as a composite of R, G, B, and processing is performed by each color. The calculation of the brightness depends on the modeling of light, but is generally obtained as follows. That is, the color of the apex = reflection from the material at the apex + the total ambient light scaled by the environmental constants of the material at the apex + the ambient light appropriately attenuated from all light sources, diffuse, mirror surface It is an influence. The outline of the processing is shown below.

If it is necessary to start processing, normalize the rays and the normals of the vertices. Set the radiated light and ambient light in the absence of a light source as constants for each (light source) {Ambient light / diffused light / specular light for each light source. Is calculated for each light source and all are added.

The vector from the apex to the light source (light incident vector: ray vector) is obtained, the distance between the apex and the light source is obtained, and the vector from the apex to the light source is also normalized.

Spotlight effect that calculates the attenuation rate from the distance and the inner product (cosθ) of the light source vector and the vertex normal. Environmental light environmental influence of each light source = Environmental light source environmental coefficient x Material (vertex) environmental coefficient Diffuse light diffusion of each light source Impact = (Light source vector / vertex normal) × Light source diffusion coefficient × Material (vertex) Diffusion coefficient Specular light L for each light source is the unit vector in the joining direction, V is the unit vector in the line-of-sight direction, and N is the unit vector in the radial direction ,
If θ is the angle of incidence and α is the angle between the line-of-sight vector and the reflection vector, To calculate the line-of-sight vector from the vertex vector sx = lx-vx sy = ly-vy sz = lz-vz To force the line-of-sight vector in the −Z-axis direction sx = lx sy = ly sz = lz + 1 Find s (sx, sy, sz) and find the inner product of s and norm.

The result of the inner product is used as the specular coefficient Shinine for each light source.
ss [i] raised (pow) to obtain spec_coef.

Specular effect ＝ spec_coef × Light source specular coefficient × Material (vertex) Specular coefficient total effect ＝ Attenuation rate × Spotlight effect × (Environmental light effect + Diffuse light effect + Specular light effect) Total effect of light source i is R, G , Add to B} Clamp R, G, B between 0 and 1 after adding all the influences of light sources Since each calculation in the illumination process depends on the modeling of light as described above, The details are slightly different, but what is important here is that the brightness is defined by the values of and the brightness after the calculation is performed is clamped to these values [0,1]. Here, [0, 1] represents n satisfying 0 ≦ n ≦ 1.

In the conventional arithmetic unit, as shown in the following processing flow, the brightness value and "0" or "1" are given by the comparison instruction.
, And if necessary, branch by a conditional branch instruction, and the constants “0” and “1” are output to perform the clamp processing.

/ * Clamping flow of R, G, B values * / if (R 0.0) {R = 0.0} if (R 1.0) {R = 1.0} if (G 0.0) {G = 0.0} if (G 1.0) {G = 1.0} if (B 0.0) {B = 0.0} if (B 1.0) {B = 1.0} In such a method, execution of a branch instruction occurs during clamping, and the operation pipeline is disturbed. Occurs. The brightness calculation requires a huge amount of processing because the three primary colors R, G, B are calculated for each vertex forming the screen.
Therefore, in the conventional flow as described above, the pipeline is frequently disturbed, and the processing performance of the brightness calculation is significantly impaired.

[0021]

As described above, in the conventional coordinate transformation processor (GTE), (1) the graphic data to be transformed cannot be efficiently transferred to the arithmetic unit and the register file. ) It is not possible to efficiently execute the inner product operation and the division by'depth 'that accompany the matrix operation that performs perspective transformation. (3) The brightness R in the illumination processing,
There is a problem that the G and B clamp processing cannot be executed at high speed. The present invention has been made in view of these problems. (1) Efficient data transfer between a storage device for graphic data and a coordinate conversion processing device (2) Matrix for performing perspective conversion Efficiently perform inner product operation and division by'depth 'accompanying operation,
(3) The object is to perform the clamp processing of the brightness R, G, B in the illumination processing at high speed, and to realize the above three.

[0022]

To achieve the above object, a feature of the first invention is that a predetermined geometric operation is performed on vertex data of a figure stored in an external storage device and represented by homogeneous coordinates. In the coordinate conversion processing device that performs processing,
An internal storage unit that is divided into a plurality of storage blocks and is capable of inputting / outputting data for each storage block, and holds the predetermined vertex data from the external storage device by inputting to the storage block. An internal storage unit that switches the connection destination to a data holding unit and outputs the vertex data,
A data holding unit for temporarily storing a part of the vertex data stored in a predetermined storage block of the internal storage unit;
An arithmetic unit for inputting vertex data stored in the data holding unit and performing predetermined processing to generate graphic data, wherein the first storage block is connected to the external storage device.
To receive the vertex data and store the data in the first storage block.
When the data reception is completed, the first storage block is
Connected to the data holding unit to output the vertex data,
The calculation unit performs a predetermined process, and the processing result is the first record.
Stored in the memory block, and the second memory block is
Connects to the external storage device and processes the next vertex data
And data reception to the second storage block is completed.
Then, the first storage block is the external storage device.
, And write back the processing result to the external storage device,
The vertex data to be processed next is received, and the second storage block is received.
Output the vertex data by connecting to the data holding unit
However, the arithmetic unit performs a predetermined process, and the processing result is the first
So that it can be written back to the second memory block.
It

In the configuration of the above invention, the second storage device is divided into a plurality of storage blocks that can be accessed independently, and some of these storage blocks are connected to an external storage device to store the data. The graphic data is transferred at high speed by the transfer device. On the other hand, some of the memory blocks not connected to the external storage device are connected to the register file or the arithmetic unit and converted to the graphic data stored in the memory block. On the other hand, the intended processing is performed. When the target processing and data transfer are completed, the memory block connected to the above-mentioned register file or arithmetic unit among the plurality of memory blocks is connected to the external memory device this time, and the data transfer device performs high-speed graphic processing. The memory block that was transferring data, on the other hand, was connected to the external memory device and was transferring the graphic data at high speed by the data transfer device, was connected to the register file and the arithmetic unit, and was stored in the memory block. The intended processing is applied to the graphic data. In this way, the storage block is an external storage device, or
It is exclusively connected to the register file and the arithmetic unit, and can transfer a large amount of data and arithmetic processing at high speed and in parallel.

The feature of the second invention is that at least a product-sum operator for performing a product-sum operation of x, y, z corresponding to x, y, z of the homogeneous coordinate system, and at least one divider. , First, second, and third register files storing at least vertex data of figures corresponding to x, y, and z of the homogeneous coordinate system, the product-sum calculator, the divider, and the register file. Connected to the product-sum calculator and the divider, and
Connecting the first bus network for supplying the operand data to the product-sum calculator and the divider and the register file, and supplying the second operand data to the product-sum calculator and the divider. A third bus that connects the second bus network to the product-sum calculator and the divider and the register file, and writes back the calculation results of the product-sum calculator and the divider to the register file. A network, wherein each first read port of the first, second, and third register files is the first read port.
Connected by the first bus network to the input terminals of the first operands of the corresponding first, second, and third product-sum calculators and the divider, and the first, Each of the second read ports of the second and third register files has a second operand input terminal of the first, second, and third product-sum calculators and a second operand of the divider. The input terminal is connected by the second bus network including a crossbar switch, and the input terminal of the second operand of each of the first, second, and third product-sum calculators and the divider is connected to the input terminal. First,
The second read ports of the second and third register files are interconnected such that register pair arithmetic units are in a one-to-one correspondence such that they are mutually exclusive combinations, and specific registers are connected to a plurality of arithmetic units. One-to-many interconnection is possible, and the output terminals of the first, second, and third product-sum calculators and the divider are write ports of the first, second, and third register files. And at least one of the output terminals of the first, second, and third product-sum calculators and the output terminal of the divider are used to write any of the first, second, and third register files. This means that it is possible to connect exclusively to a port and to write to a predetermined address of the register.

In the configuration of the above-mentioned invention, the vertex data of the graphic is first and second data using the first and second bus networks.
Input from the second and third register files to the corresponding first, second, and third arithmetic units, the target arithmetic operation is performed, and the corresponding first and second arithmetic operations are performed using the third bus network. , And is written back to the third register file. As a result, it is possible to efficiently execute the inner product operation and the division by the “depth” that accompany the matrix operation that performs the perspective transformation.

Here, the output terminals of the first, second and third product-sum calculators and the divider are the first, second and third output terminals.
Connected directly to the second input terminal of the multiply-accumulate operator and the divider, and before the operation result is written back to the register file, or in parallel with the writing back processing, the first, second, and third A first bypass network for supplying directly to the first input terminals of the first, second, and third product-sum calculators and the divider as an operand of the product-sum calculator and the divider; The output terminals of the first, second, and third product-sum calculators and the divider are directly connected to the first and second bus networks, and the first and second operations are performed in parallel with the process of writing back the operation results. A second supply supplied directly to the first or second input terminal of the first, second or third product-sum operator as an operand of the second and third product-sum operator or the divider. A bypass network, and the configuration of the second invention. It is preferably provided.

Further, a feature of the third invention is that at least one of a product-sum operator for performing a product-sum operation of x, y, z, w corresponding to x, y, z, w of the homogeneous coordinate system Two dividers, first, second, third, and fourth register files storing at least vertex data of a figure corresponding to x, y, z, and w of the homogeneous coordinate system; The divider and the register file are connected to each other, and the product-sum calculator is
A first bus network for supplying first operand data to the divider is connected to the product-sum calculator and the divider and the register file, and a second bus is connected to the product-sum calculator and the divider. Second bus network for supplying the operand data of the above, the product-sum calculator and the divider, and the register file are connected, and the calculation results of the product-sum calculator and the divider are written in the register file. A third bus network for returning, each first read port of the first, second, third, and fourth register files being associated with the first bus network by the first bus network. , The second, the third, the fourth product-sum operator and the input terminal of the first operand of the divider are connected by the first bus network, and the first,
The second read port of each of the second, third, and fourth register files has a second operand input terminal of each of the first, second, third, and fourth product-sum operators and the divider. Connected to the input terminal of the second operand of the second bus network including a crossbar switch of the first, second, third, and fourth product-sum operators and the divider. There is a one-to-one correspondence between register-pair arithmetic units in which the input terminals of the second operand and the respective second read ports of the first, second, third, and fourth register files are mutually exclusive combinations. And a one-to-many interconnection connecting a specific register to a plurality of arithmetic units are possible, and the output terminals of the first, second, third and fourth multiply-accumulate arithmetic units and the divider. Is the first, second, third,
At least one of the output terminals of the first, second, third and fourth product-sum calculators and the output terminal of the divider are connected to the respective write ports of the fourth register file, It is possible to exclusively connect to any write port of the second, third, and fourth register files, and to write to a predetermined address of the register.

Here, the output terminals of the first, second, third, and fourth product-sum calculators and the divider are connected to the first, second, third, and fourth product-sum calculators and the output terminals of the dividers. The first, second, third, and fourth product-sum calculators, which are directly connected to the second input terminal of the divider, before the operation results are written back to the register file, or in parallel with the write-back processing. And directly as the operand of the divider, the first, second, third,
A fourth bypass-sum network for supplying to the first input terminal of the fourth product-sum calculator and the divider, and the first, second, third, and fourth product-sum calculators and the divider. Of the first and second bus networks are directly connected to the first and second bus networks, and the first and
Directly as an operand of the second, third, fourth product-sum calculator and the divider, the first or second input terminal of the first, second, third, fourth product-sum calculator It is preferable to further include a second bypass network for supplying to the above-mentioned third invention.

[0029]

[0030]

[0031]

[0032]

Figure 1 DETAILED DESCRIPTION OF THE INVENTION, the coordinate conversion processing device of the present invention (hereinafter GTE: Graphic Tran s lateEngine) is a block diagram showing the configuration of. First, the configuration of the embodiment of the proposed calculation method will be described with reference to FIG. The coordinate conversion processing device 100 inputs predetermined vertex data from an external storage device 200 to a storage block and holds the same, and switches a connection destination to a data holding unit 120 to output the vertex data, and an internal storage unit 110. The data holding unit 120 that temporarily stores a part of the vertex data stored in a predetermined storage block of the unit 110, and the vertex data stored in the data holding unit 120 are input, and a predetermined process is performed to draw a figure. The storage block of the internal storage unit 110 receives the graphic data generated by the calculation unit 130, switches the connection destination to the external storage device 200, and outputs the graphic data. It is configured as follows.

FIG. 2 shows the configuration of the internal storage unit 110. D
An external storage device 20 using the MA controller 111 (described later)
It is connected to 0. The internal storage device 112 is a 2 Mbyte storage device and has two banks 112 a and 112 b (each having 1 Mbytes).
These banks are connected to the arithmetic unit and the register file through the load / store unit 121 or the storage device through the DMA controller 111. These connections are exclusively connected to each other, and only one of them is not connected. The address generator 113 generates an address for accessing the internal storage device 112.

FIG. 3 shows the structure of the data holding unit 120.
The load / store unit 121 is the internal storage device 11.
2 and the register file 122 are connected by a 128-bit (32-bit × 4) high-bandwidth bus 114 to mutually transfer data. The register file 112 is a 32-bit x64 register file divided into four banks, Bank 0 to Bank 3. Register number n (6
Registers with 4> n ≧ 0 have bank numbers (n mod
4) belongs to the bank (where a modb is a
Represents the remainder divided by b). Here, each bank corresponds to (x, y, z, w) in the homogeneous coordinate system. That is, bank 0 corresponds to x, bank 1 corresponds to y, bank 2 corresponds to z, and bank 3 corresponds to w.

FIG. 4 shows the configuration of the arithmetic unit 130. The constituent members 131 to 134 are sum-of-products arithmetic units and have a three-stage pipeline structure. Like the register, it corresponds to (x, y, z, w) in the homogeneous coordinate system. That is, the arithmetic unit 131 corresponds to x, the arithmetic unit 132 corresponds to y, the arithmetic unit 133 corresponds to z, and the arithmetic unit 134 corresponds to w. The calculator 135 is a division / square root calculator. The calculation is completed in 6 cycles. The port 136 is an input / output port that transfers data with an external processor. It is connected by a 64-bit bus.

The bus 141 is a bus network for interconnecting the register file 122, the arithmetic unit 130, and the load / store unit 121. The bus has a width of 32 bits x 4 (128 bits), and the register file 122 corresponding to (x, y, z, w) in the homogeneous coordinate system.
And the arithmetic unit 130 are connected via a crossbar switch 190a. The crossbar switch includes the register file 122, the arithmetic unit 130, and the load / store unit 1.
If 21 is exclusive, connection is possible to any combination.

The bus 142 is a bus network for interconnecting the register file 122 and the arithmetic unit (excluding the port 136) 130. The bus is 32 bits x 4 (1
It has a width of 28 bits, and has (x, y, z,
w) corresponding register file 122 and operation unit 130
And connect.

The bus 143 is a bus network that interconnects the register file 122, the arithmetic unit 130, and the load / store unit 122. The bus has a width of 32 bits x 4 (128 bits), and the register file 122 corresponding to (x, y, z, w) in the homogeneous coordinate system.
The calculation unit 130 and the load / store unit 121 are connected to each other via the crossbar switch 190b. The switch 190b includes the register file 122 and the arithmetic unit 13.
0, the load / store unit 121 can be exclusively connected. The calculation result of the calculation unit 130 can be written back only to the corresponding register file 122.
On the other hand, arithmetic units 134 and 135, port 136, load
The value of the store unit 121 can be written to any address in the register file. The above is the configuration of the present embodiment. Next, the operation of data transfer and coordinate conversion processing in this embodiment will be described.

First, the data transfer between the external storage device 200 and the coordinate conversion processing device 100 will be described. The external storage device 200 stores vertex information of graphics, color information, texture information, and the like. It is also used as a general-purpose storage device of the processor. One bank 112b of the internal storage device 110 is connected to an external storage device through the DMA controller 111, and
Under the control of the controller 111, required graphic data is transferred at high speed to the bank 112b of the internal storage device. During this time, the bank 112a keeps the load / store unit 12
1 to connect to buses 1 4 1, 1 4 3 and
30 and the register file 122.

[0040] Once the data necessary for the bank 112b transfer terminates, the bank 112b is connected through a load store unit to the bus 1 4 1,1 4 3, operation unit 130, connected to the register file 122. The necessary data is transferred from the bank 112b to the register file 122,
The arithmetic unit 130 performs a predetermined process. The processing result is written back to the bank 112b through the register file 122. On the other hand, the bank 112a is connected to an external storage device through the DMA controller 111,
Under the control of the controller 111, required graphic data is transferred at high speed to the bank 112a of the internal storage device.

Processing on the data of the bank 112b,
When the data transfer to the bank 112a is completed, the bank 112b is connected to the external storage device again, and the processing result is written back to the external storage device under the control of the DMA controller 111, and the graphic data to be processed next is transferred. I do.
On the other hand, the bank 112a is connected to the buses 141 and 143 through the load / store unit, and is connected to the arithmetic unit 130 and the register file 122. The necessary data is transferred from the bank 112b to the register file 122, and the arithmetic unit 130 performs a predetermined process. The processing result is written back to the bank 112a through the register file 122.

Hereinafter, as described above, the two banks are alternately assigned to the data transfer and the arithmetic processing, thereby
Two processes can be executed in parallel and at high speed. Also, because it does not require complicated controls or special storage devices,
It is possible to implement a sufficient amount of internal storage device at low cost.

Next, an example of performing perspective transformation in this embodiment will be described. Now, letting the input (x, y, z, 1) be the vertex coordinates to be transformed, the perspective transformation is performed as follows,
(X, Y) Output screen X and Y coordinates after perspective transformation.

(1) (x ', y', w ') = (x, y, z, 1) x (a, b, c) (d, e, f) (g, h, i) (j , k, l) ＝ (ax + dy + gz + j, bx + ey + hz + k, cx + fy + iz + l) (2) W = 1 / w ′ (3) (X, Y) = ( x ′, y ′) × W The following is an example of a program that applies the above processing to an independent triangle (3 vertices). Normally, three-dimensional graphic data is treated as a set of independent triangles, and therefore the program shown below is repeatedly processed. Here, the matrix is a product matrix of coordinate transformation / perspective transformation, the latency of multiplication and product-sum operation is 3, throughput is 1, latency of division is 6, throughput is 5, latency of the last instruction is not taken into consideration. And Further, the input vertex data is loaded from the internal storage device, and the coordinate conversion result is converted into a fixed point and then stored in the internal storage device.

The symbols and mnemonics appearing in the program will be briefly described below.

Symbol / R *: CPU register GR *: GTE floating register IR: GTE integer register mnemonic / GMACn: Multiply-add operation instruction, write back to accumulator GMACFn: Multiply-add operation instruction, write back to register file GMULAn: Multiply instruction , Write back to accumulator GDIV: Division instruction GFTOIn: Floating-point to fixed-point conversion instruction GSWn: Store instruction GLWn: Load instruction Here, n represents the number of arithmetic units operating simultaneously. For example, in the GMAC4, data is independently input from the register file 122 to each arithmetic unit of the four arithmetic units 130, and the arithmetic result is written back to the corresponding four register files 122.

Each data is stored in the register file 122 as follows.

[0048] register map ; GR00, GR01, GR02, GR03,; vertex 1 (x, y, z, 1) coordinates ; GR04, GR05, GR06, GR07,; Vertex 2 (x, y, z, 1) coordinates ; GR08, GR09, GR10, GR11,; vertex 3 (x, y, z, 1) coordinates GR12, GR13, GR14, GR15,; 640, 480, 0, 1 (constant storage) ; GR16, GR17, GR18, GR19,; vertex 1 tmp coordinate (x ′, y ′, z ′), 1 / z GR20, GR21, GR22, GR23,; vertex 2 tmp coordinates (x ′, y ′, z ′), 1 / z ; GR24, GR25, GR26, GR27,; vertex 3 tmp coordinates (x ′, y ′, z ′), 1 / z GR28, GR29, GR30, GR31,; GR32, GR33, GR34, GR35 ,; Coordinate / perspective transformation matrix GR36, GR37, GR38, GR39 ,; Coordinate / perspective transformation matrix GR40, GR41, GR42, GR43 ,; Coordinate / perspective transformation matrix GR44, GR45, GR46, GR47 ,; Coordinate / perspective transformation matrix GR48, GR49, GR50, GR51,; Final result (x ", y") Vertex 1 GR52, GR53, GR54, GR55 ,; Final result (x ", y") Vertex 2 GR56, GR57, GR58, GR59,; final result (x ", y") vertex 3 GR60, GR61, GR62, GR63,; The following shows the program when optimization is not performed.

Vertex 1 -------------------- GLW4 GR (00-03), 0x00 (IR1); V1: Vertex 1 coordinate load GMULA3 GR (32- 34), GR00; V1: Transform vertex 1 x & ACC clear GMAC3 GR (36-38), GR01; V1: Transform vertex 1 y GMAC3 GR (40-42), GR02; V1: Transform vertex 1 z GMACF3 GR (16 -18), GR (44-46), GR03; V1: Translating element (GR03 = 1) GDIV GR19, GR15, GR18; V1: Division execution (GR15 = 1) GMUL2 GR (48-49), GR (16 -17), GR19; V1: (x ′, y ′) × 1 / z GFTOI2 GR (48-49), GR (48-49), FM1; V1: Fixed point conversion GSW2 GR (48-49), 0x10 (IR2); V1: Store to GPU preprocessor; Vertex 2 -------------------- GLW4 GR (00-03), 0x10 (IR1); V2: Vertex 1 coordinate load GMULA3 GR (32-34), GR04; V2: Transform vertex 2 x & ACC clear GMAC3 GR (36-38), GR05; V2: Transform vertex 2 y GMAC3 GR (40-42), GR06; V2 : Transform vertex 2 z GMACF3 GR (20-22), GR (44-46), GR07; V2: Translating element (GR07 = 1) GDIV GR23, GR15, GR22; V2: Division execution (GR15 = 1) GMUL2 GR (52-53), GR (20-21), GR23; V2: (x ′, y ′) × 1 / z GFTOI2 GR (52-53), GR (52-53), FM1; V2: Fixed point conversion GSW2 GR (52-53), 0x10 (IR2); V2: Store to GPU preprocessor; Vertex 3 ------------------- -GLW4 GR (00-03), 0x20 (IR1); V3: Load vertex 1 coordinate GMULA3 GR (32-34), GR08; V3: Convert vertex 3 x & ACC clear GMAC3 GR (36-38), GR09; V3 : Transform vertex 3 y GMAC3 GR (40-42), GR10; V3: Transform vertex 3 z GMACF3 GR (24-26), GR (44-46), GR11; V3: Translating element (GR11 = 1) GDIV GR27 , GR15, GR26; V3: Division execution (GR15 = 1) GMUL2 GR (56-57), GR (24-25), GR27; V3: (x ′, y ′) × 1 / z GFTOI2 GR (56-57 ), GR (56-57), FM1; V3: Fixed-point conversion GSW2 GR (56-57), 0x20 (IR2); V3: Store to GPU preprocessor The following is optimized considering latency and throughput. It is a program when you do. However, in the following program, the data loading / storing / conversion to fixed point is omitted.

GMULA3 GR (32-34), GR00; V1: Conversion vertex 1 x & ACC clear GMAC3 GR (36-38), GR01; V1: Conversion vertex 1 y GMAC3 GR (40-42), GR02; V1: Transform Vertex 1 z GMACF3 GR (16-18), GR (44-46), GR03; V1:: Translating element (GR03 = 1) GMULA3 GR (32-34), GR04; V2: Transform Vertex 2 x & ACC clear GMAC3 GR (36-38), GR05; V2: Transform vertex 2 y GMAC3 GR (40-42), GR06; V2: Transform vertex 2 z GDIV GR19, GR15, GR18; V1: Perform division (GR15 = 1) GMACF3 GR (20-22), GR (44-46), GR07; V2: Translating element (GR07 = 1) GMULA3 GR (32-34), GR08; V3: Transform vertex 3 x & ACC clear GMAC3 GR (36-38 ), GR09; V3: Transform vertex 3 y GMAC3 GR (40-42), GR10; V3: Transform vertex 3 z GDIV GR23, GR15, GR22; V2: Perform division (GR15 = 1) GMACF3 GR (24-26), GR (44-46), GR11; V3: Translating element (GR11 = 1) --stall --stall GMUL2 GR (48-49), GR (16-17), GR19; V1: (x ′, y ′ ) × 1 / z GDIV GR27, GR15, GR26; V3: Division execution (GR15 = 1) --stall --stall GMUL2 GR (52-53), GR (20-21), GR23; V2: (x ′, y ′) × 1 / z --stall --stall GM UL2 GR (56-57), GR (24-25), GR27; V3: (x ′, y ′) × 1 / z The timing when the program above is executed is shown in Fig.5.
As shown in FIG. By applying the present invention to GTE in this way, it is possible to efficiently execute the inner product operation that accompanies the matrix operation that performs coordinate conversion. In particular, since division and matrix operation can be executed in parallel, the capacity of a plurality of arithmetic units is not wasted.

That is, by adopting this configuration, (1) efficient data transfer between the graphic data storage device and the coordinate conversion processing device, and (2) inner product calculation accompanying matrix calculation for coordinate conversion are performed. It is possible to provide a coordinate transformation processing device (GTE) capable of executing efficiently.

FIG. 7 is a block diagram showing the configuration of the fourth invention. The configuration and operation of the embodiment of the proposed arithmetic method will be described with reference to FIG. 7. The floating point numbers handled by this floating point unit are IEEE754.
It is a single precision number (32 bits) defined in the floating point arithmetic standard.

The constituent member 701 is a floating point arithmetic unit including the functions of the present invention, and is one of the arithmetic units constituting the coordinate transformation processing device. The arithmetic unit 701 includes a code part determination means 702, an exponent part determination means 703, and a constant generation means 704. The sign part determination unit 702 determines whether the input value is positive or negative, depending on the value of the sign part of the input floating-point number. In the embodiment, if it is “1”, it is negative,
If it is "0", it is determined to be positive. Therefore, in the embodiment, a specific circuit is not necessary and the code signal can be used as it is. The determination result is input to the constant generation unit 704.

The exponent part judging means 703 is a comparator for judging whether or not the absolute value of the input value is “1 or more” based on the value of the exponent part. Since inputted floating-point numbers are normalized, the absolute value of the input value if the value of the exponent is '127' in the embodiment, the mantissa (1.xxxxx .....) × 2 ⁰ ( x represents "0" or "1"). Therefore, if the value of the exponent part is a normalized number of 127 or more (≧ 127), the input floating-point number is determined to be 1 or more. Therefore, in the embodiment, the exponent part determination means may be a comparison circuit (comparator) that determines the magnitude relationship with the constant 127. The determination result is input to the constant generation unit 704.

The constant generation means 704 is the code part determination means 7
02, according to the judgment result of the exponent part judging means 703,
A floating point number of "0" or "+1" is output as the operation result. The constant generation means 704 is the code part determination means 7
When the determination result of 02 is'negative ', the values of the three fields of the sign part, the exponent part, and the mantissa part are changed so as to be a floating point number representing' 0 '. Also, the code part determination means 70
The determination result of 2 is “positive”, and the exponent determination means 7
If the determination result of 03 is'absolute value is 1 or more ', the values of the three fields of the sign part, exponent part, and mantissa part are changed so that the floating point number represents' + 1'.
Outputs "+1" as the calculation result. Therefore, in the present embodiment, the constant generation unit selects either the constant "0" or "1" or the input value (the input code decimal point number) according to the results of the sign unit determination unit and the exponent unit determination unit. It can be configured by a selection circuit.

In the above embodiments, single precision numbers have been described. In the case of a double precision number, the exponent part determining means may compare with the constant 1023 instead of comparing with the constant 127. Further, in the above description, the floating point number based on the IEEE754 standard is described, but a floating point number expressed in another format can be realized by the same processing procedure.

As described above, if the coordinate conversion processing device of this embodiment is used, it is possible to clamp to a specific value (in the embodiment, [0, 1]) by the input value by adding a small amount of hardware. Therefore, the clamp processing, which has been conventionally performed by using the comparison instruction and the conditional branch instruction, can be executed at high speed without causing the disturbance of the pipeline due to the branch. In particular, the illumination processing can be executed at a high speed by using it for the brightness calculation of the illumination processing in computer graphics, the blend calculation of colors, etc., and the clamp processing to [0, 1] which is often used in the unaliasing processing.

[0058]

According to the present invention, in comparison with the conventional method, (1) efficient data transfer between the graphic data storage device and the coordinate conversion processing device, and (2) matrix operation for performing perspective transformation are performed. Coordinate conversion processing unit (GTE) that enables high speed execution of inner product calculation and division by'depth ', and (3) clamp processing of brightness R, G, B in illumination processing.
Can be provided.

[Brief description of drawings]

FIG. 1 is a block diagram of a coordinate conversion processing device according to the present invention.

FIG. 2 is a block diagram showing an internal storage unit 110.

FIG. 3 is a block diagram showing a data holding unit 120.

FIG. 4 is a block diagram showing a calculation unit 130.

FIG. 5 is an execution timing diagram (part 1) of coordinate conversion using the arithmetic unit of the present embodiment.

FIG. 6 is an execution timing diagram (part 2) of coordinate conversion using the arithmetic unit of the present embodiment.

FIG. 7 is a block diagram of a floating-point arithmetic unit of the coordinate conversion processing device according to the present invention.

FIG. 8 is an example (No. 1) of a conventional coordinate conversion processing device.

FIG. 9 is an example (No. 2) of a conventional coordinate conversion processing device.

[Explanation of symbols]

100 coordinate conversion processing device 110 internal storage 111 Direct Memory Controller 112 internal memory 113 address generator 114 Bus between internal memory and register file 120 data storage 121 Load / Store Circuit 122 register file 130 arithmetic unit 131, 132, 133, 134 Product-sum calculator 135 divider 136 I / O port 137 Bypass Network 141,142,143 bus network 151,152 Crossbar switch 200 External storage device 701 floating point calculator 702 code part determination means 703 Exponent part determination means 704 constant generation means 801,901 Computing unit 802,902 register file 803,903 Internal storage device 804,904 Input / output interface 805,905 data bus

Continuation of front page (51) Int.Cl. ⁷ Identification code FI G09G 5/36 530C (72) Inventor Maki Ueno 25, Ekimaehonmachi, Kawasaki-ku, Kawasaki-shi, Kanagawa Toshiba Microelectronics Stock Association In-house (56) References Special Features Kaihei 4-348485 (JP, A) JP 7-200404 (JP, A) JP 62-205482 (JP, A) JP 4-144361 (JP, A) JP 5-73706 ( JP, A) JP 57-193840 (JP, A) JP 58-51352 (JP, A) JP 5-46783 (JP, A) JP 6-511330 (JP, A) (58) ) Fields surveyed (Int.Cl. ⁷ , DB name) G06T 15/00 G06F 7/00 G09G 5/36 G06F 12/00-12/12

Claims (5)

(57) [Claims] 1. A coordinate conversion processing device which is stored in an external storage device and which performs a predetermined geometric operation process on vertex data of a figure represented by homogeneous coordinates, wherein a first storage block and a second storage block are provided. And a memory block,
An internal storage unit for inputting and outputting data for each of these storage blocks, in which the predetermined vertex data is input and held in the storage block from the external storage device, and the connection destination is switched to a data holding unit to store the vertex data. An internal storage unit that outputs data, a data holding unit that temporarily stores a part of the vertex data stored in a predetermined storage block of the internal storage unit, and the vertex data stored in the data holding unit. An arithmetic unit for inputting, performing a predetermined process to generate graphic data, and connecting the first storage block to the external storage device.
When the vertex data is received and the data reception to the first storage block is completed,
The first storage block is connected to the data holding unit.
The vertex data is output and the arithmetic unit performs a predetermined process.
Then, the processing result is written back to the first storage block,
The second storage block is connected to the external storage device.
When the vertex data to be processed next is received and the data reception to the second storage block is completed,
The first storage block is connected to the external storage device.
Then, the processing result is written back to the external storage device and then processed.
Receiving the vertex data to be processed, the second storage block is
Connect to the data holding unit to output the vertex data,
The arithmetic unit performs a predetermined process, and the process result is stored in the second storage.
A coordinate conversion processing device characterized by being written back to a block . 2. A product-sum operator for performing a product-sum operation of x, y, z corresponding to x, y, z of at least a homogeneous coordinate system, at least one divider, and at least x of a homogeneous coordinate system. , Y, z, first, second, and third register files for storing vertex data of figures, and the product-sum calculator and the divider and the register file are connected to each other, and the product-sum calculator is connected. A first bus network for supplying first operand data to the divider, the product-sum calculator, the divider and the register file are connected to each other, and A second bus network for supplying two operand data, the product-sum calculator and the divider, and the register file are connected to each other, and the calculation results of the product-sum calculator and the divider are stored in the register file. Write back A first read port of each of the first, second, and third register files corresponding to the first, second, and third bus networks. 3 is connected to the input terminal of the first operand of the product-sum operator and the divider by the first bus network, and the second read ports of each of the first, second, and third register files are , A second operand input terminal of each of the first, second, and third product-sum calculators, an input terminal of the second operand of the divider, and the second bus network including a crossbar switch And an input terminal of the second operand of each of the first, second, and third product-sum calculators and the divider, and the first, second, and
Each second read port of the third register file is
It is possible to make interconnections in which register-pair arithmetic units that are mutually exclusive combinations have a one-to-one correspondence and one-to-many interconnections that connect specific registers to a plurality of arithmetic units. Output terminals of the third product-sum calculator and the divider are connected to respective write ports of the first, second, and third register files, and the first, second, and third product-sum calculators are connected. At least one of the output terminals of the register and the output terminal of the divider can be exclusively connected to any of the write ports of the first, second, and third register files, and can be connected to a predetermined address of the register. A coordinate conversion processing device characterized by being writable also. 3. The output terminals of the first, second and third product-sum calculators and the divider are connected to the first, second and third product-sum calculators and the second terminal of the divider. Before connecting the input terminal directly and writing the operation result back to the register file,
Alternatively, in parallel with the writing back process, the first, second, and third
A first bypass network that supplies directly to the first input terminals of the first, second and third product-sum calculators and the divider as operands of the product-sum calculator and the divider. The output terminals of the first, second, and third product-sum calculators and the divider are directly connected to the first and second bus networks, and the first result is written in parallel with the process of writing back the calculation result. ,
A second supply supplied directly to the first or second input terminal of the first, second or third product-sum operator as an operand of the second and third product-sum operator or the divider. The coordinate transformation processing device according to claim 2, further comprising: a bypass network. 4. An x, y, z, w of at least a homogeneous coordinate system.
The sum-of-products calculator for performing the sum-of-products calculation of x, y, z, w corresponding to, at least one divider, and at least the vertex data of the figure corresponding to x, y, z, w of the homogeneous coordinate system The first, second, third, and fourth register files to be stored, the product-sum calculator and the divider, and the register file are connected to each other, and the product-sum calculator and the divider have a first operand. A second bus network for supplying data, the product-sum calculator and the divider are connected to the register file, and a second operand data is supplied to the product-sum calculator and the divider. And a third bus network for connecting the product-sum operation unit and the divider to the register file, and writing back the operation results of the product-sum operation unit and the divider to the register file. , The first read port of each of the first, second, third, and fourth register files is connected to the corresponding first, second, third, and fourth by the first bus network. An input terminal for the first sum operand of the product-sum operator and the divider,
The second read port of each of the first, second, third, and fourth register files connected by the first bus network is connected to each of the first, second, third, and fourth. A second operand input terminal of the product-sum calculator and an input terminal of the second operand of the divider, and a crossbar
The first and second input / output terminals of the first, second, third, and fourth product-sum calculators and the divider are connected to each other by the second bus network including a switch. Each second of the second, third, and fourth register files
The read ports can be interconnects in which register pair arithmetic units have a one-to-one correspondence such that they are mutually exclusive combinations, and one-to-many interconnects that connect a specific register to a plurality of arithmetic units. The output terminals of the first, second, third, fourth product-sum calculator and the divider are connected to the write ports of the first, second, third, and fourth register files, respectively. At least one of the output terminals of the first, second, third, and fourth product-sum calculators and the output terminal of the divider write to any of the first, second, third, and fourth register files. A coordinate conversion processing device, which can be exclusively connected to a port and can be written to a predetermined address of the register. 5. The output terminals of the first, second, third and fourth product-sum calculators and the divider are connected to the first, second, third and fourth product-sum calculators and the divider. Of the first, second, third, and fourth product-sum calculators, which are directly connected to the second input terminal of A first bypass network for supplying directly to the first, second, third, fourth product-sum operator and the first input terminal of the divider as an operand of the divider; The output terminals of the second, third, fourth product-sum calculator and the divider are directly connected to the first and second bus networks, and the first result is written in parallel with the process of writing back the calculation result. , The second, the third, the fourth product-sum operator and the divider as a direct operand, , Second, third, fourth
5. The coordinate transformation processing device according to claim 4, further comprising: a second bypass network that supplies the first or second input terminal of the multiply-accumulate calculator.