JP3456832B2 - ECL logic circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an improvement in an IC logic circuit, and more particularly to an ECL capable of operating at high speed and low power consumption.
Regarding logic circuits.

[0002]

2. Description of the Related Art An example of a conventional ECL logic circuit will be described with reference to FIG. In the figure, transistors Q1 to Q
3, resistors R1 to R3, and voltage sources V1 to V3 form a differential amplifier. The base of the transistor Q1 is the circuit input terminal 1
And the voltage source V1 is connected to the base of the transistor Q2.
The reference voltage Vref is applied. For example, voltage source V
1 is -1.3 volts, voltage source V2 is -5.2 volts, and voltage source V3 is -3.9 volts.

An emitter follower output circuit is connected to the collector of the transistor Q2 which is the output terminal of this differential amplifier. The emitter follower output circuit includes an emitter follower transistor Q4, a current source transistor Q5, and a resistor R.
4 series circuits. The collector output of the transistor Q2 is input to the base of the transistor Q4,
The connection point between the emitter of the transistor Q4 and the collector of the transistor Q5 serves as the circuit output terminal 2. Transistor Q
The output Vcs of the voltage source V3 is applied to the bases of 3 and Q5, and the levels of the current Ics1 flowing through the transistor Q3 and the current Ics2 flowing through the transistor Q5 are set. A load capacitance CL is connected to the circuit output terminal 2. This load capacitance CL corresponds to, for example, the input capacitance of the next-stage logic circuit.

In such a structure, when the L level (negative level) is applied to the input terminal 1, the transistor Q1 becomes non-conductive and the transistor Q2 becomes conductive. As a result, the collector output of the transistor Q2 has the ground potential V
SS-Ics1 · R2. Due to the voltage drop Vbe4 between the base and emitter of the emitter follower transistor Q4, the potential of the output terminal 2 is set to VSS-Ics1.R2-Vbe4. In this case, the collector current of the transistor Q4 is (VSS-Ics1.R2) applied to the base,
A relatively small current flows.

On the other hand, when the H level (Vss level) is applied to the input terminal 1, the transistor Q1 becomes conductive and the transistor Q2 becomes non-conductive. As a result, the collector output of the transistor Q2 becomes the ground potential Vss.
In this case, the output terminal 2 is set to Vss-Vbe4. A relatively large current flows in the collector current of the transistor Q4 by applying Vss to the base.

The current source transistor Q5 is connected to Vcs
It operates so that the constant current Ics2 determined by is always drawn from the output terminal 2. As a result, when the H level is applied to the circuit input terminal 1, the load capacitance CL is charged by the difference current between the collector current of the transistor Q4 and the constant current Ics2 when the waveform rises, and the potential of the output terminal 2 becomes It is pulled up toward the ground. Further, when the L level is applied to the circuit input terminal 1, electric charges are extracted from the load capacitance CL by the difference current between the collector current of the transistor Q4 and the constant current Ics2 when the waveform falls, and the output terminal 2 The potential is pulled down in the negative direction.

Another example of the conventional ECL logic circuit (active pull-down circuit of negative logic operation) will be described with reference to FIG. In the figure, parts corresponding to those in FIG. 4 are designated by the same reference numerals, and transistors Q1 to Q3 and resistors R1 to R are provided.
3. The voltage sources V1 to V3 form a differential amplifier. The emitter follower transistor Q4 and the current source transistor Q5 form an emitter follower output circuit. The connection point of the transistor Q4 and the transistor Q5 is the circuit output terminal 2
Becomes A series circuit of the voltage source V5, the clamp circuit 3, the resistor R4, and the voltage source V6 constitutes a base bias circuit of the transistor Q5. For example, the voltage source V5 is -0.5 to-.
2.5 V, the voltage source V6 is -5.2 V, and the clamp circuit 3 clamps the base potential to suppress the current of the transistor Q5 to a small value when no signal component is supplied to the base of the transistor Q5.

The collector of the transistor Q2 which is the positive phase output terminal of the differential amplifier is connected to the output terminal 2 via the transistor Q4.
Connected to. The collector of the transistor Q1 which is the negative phase output terminal of the differential amplifier is connected to the base of the transistor Q5 via the coupling capacitor Cc. The bias circuit connected to the base of the transistor Q5 is connected for the purpose of suppressing current consumption in the steady state.

Also in this ECL circuit, the circuit input terminal 1
The circuit operates in the same manner as the circuit of FIG. 4 with respect to the input signal to the transistor Q5, but the bias circuit provided on the base side of the transistor Q5 suppresses the current of the transistor Q5 in a steady state (H level input) to a low level. That is, when an H-level signal near the ground potential is supplied to the input end 1, the transistor Q1 becomes conductive, the transistor Q2 becomes non-conductive, the base of the transistor Q4 is set to Vss, and the output end 2 is set to Vss-. Set to Vbe4. The base of the transistor Q4 is relatively deeply biased to allow a large collector current to flow through the load capacitance CL. Due to the conduction state of the transistor Q1, the collector of the transistor Q1 is Vss-Ics1.
It becomes R2. This is applied to the base of the transistor Q5 to which the clamp circuit 3 is connected via the differentiating circuit capacitor Cc. By the action of the clamp circuit 3, the collector output does not bias the base of the transistor Q5 deeply in the forward direction, and the collector current of the transistor Q5 is suppressed. Therefore, the collector current of the transistor Q4 flows into the load capacitance and quickly raises the output waveform.

On the other hand, when an L level signal is supplied to the input terminal 1, the transistor Q1 becomes non-conductive, the transistor Q2 becomes conductive, and the base of the transistor Q4 becomes V.
ss-Ics1 ・ Set to R2 and output terminal 2 is Vss-Ics1 ・
Set to R2-Vbe4. The base of transistor Q4 is biased relatively shallow to allow a small collector current. Due to the non-conducting state of the transistor Q1, the collector potential of the transistor Q1 becomes Vss. This is applied to the base of the transistor Q5 to which the clamp circuit 3 is connected via the differentiating circuit capacitor Cc. Due to this VSS, the base-emitter of the transistor Q5 is biased deeper, increasing the collector current of the transistor Q5. Therefore, the collector current of the transistor Q5 pulls out the charge from the load capacitance CL, and the output waveform falls.

In this way, the collector current of the transistor Q5 in the steady state is reduced to suppress the power consumption, and when the input waveform falls, the collector current of the transistor Q5 is set to be large and the load capacitance CL is set.
The charge of is quickly extracted to improve the transient response of the output waveform.

[0012]

In the conventional circuit shown in FIG. 4, the rise time of the output waveform at the circuit output terminal 2 is determined by the flow of the current from the emitter follower Q4 into the load capacitance CL. By increasing the current flowing through the base of the output transistor Q4, the rising speed of the output waveform can be increased. On the other hand, the fall time of the output waveform is determined by the discharge from the load capacitance CL. The discharge rate depends on the time constant determined by the current Ics2 flowing through the collector of the transistor Q5 and the load capacitance CL. To increase the discharge speed, use transistor Q5
It is necessary to increase the collector current Ics2 of. Since this collector current Ics2 is always flowing, the current consumption of the circuit increases. Therefore, in the conventional circuit shown in FIG. 4, the gate speed cannot be increased without increasing the power consumption of the circuit.

In another example of the conventional circuit shown in FIG. 5, a large current flows through the collector of the transistor Q5 only when the output waveform falls and transitions, and a small amount of current flows in the steady state. It is a logic circuit that consumes less power and has a faster fall.

However, the differentiation circuit capacitor Cc
is necessary. That is, the differential circuit capacitor Cc must be formed on the integrated circuit, which increases the chip area. Also, a semi-custom LS such as a gate array
In the case of I, it may be necessary to newly create a matrix (base) whose capacity has already been created. In such a case, there is a problem that a new process needs to be added.

Therefore, an object of the present invention is to provide an ECL logic circuit which operates at high speed and consumes less power and which is suitable for an integrated circuit.

[0016]

In order to achieve the above object, an ECL logic circuit of the present invention comprises an ECL logic section (Q1 to Q3, R1 to R3, V1 to V) including a transistor differential pair.
3), a first transistor (Q4) of the emitter follower type which receives at its base one collector output of the transistor differential pair, and second and third transistors (Q11,
Q12) and an emitter follower output circuit (Q4, Q11, Q12, V4) including a series circuit composed of the same, and the other collector output of the transistor differential pair are level-shifted and supplied to the base of the second transistor (Q11). A first level shift circuit (LS1), a second level shift circuit (LS2) that level-shifts the emitter output of the first transistor (Q4) and supplies it to the base of the third transistor (Q12), It is characterized by being provided.

Further, the ECL logic circuit of the present invention is an ECL including a transistor differential pair (Q1, Q2) that generates first and second outputs that complementarily change according to the input (1).
L logic units (Q1 to Q3, R1 to R3, V1 to V3),
An output transistor circuit (Q4) that receives the first output of the transistor differential pair at its input end and drives the circuit output end (2)
And a current source (Q11, Q) connected to the circuit output terminal (2).
12) and an output circuit (Q
4, Q11, Q12, V4) and the first level (H) of the input (1) sets the circuit output end (2) to the first output level (H), the transistor differential pair (Q
The second output of the current source (Q11, Q1)
2) is deactivated and when the circuit output (2) is set to the second output level (L) by the second level (L) of the input (1), the second output causes the current source ( Q11, Q12) is activated and the current source (Q11, Q12) is deactivated when the circuit output terminal (2) transits from the first output level (H) to the second output level (L). Current source control means (LS1, LS2) are provided, and the rise and fall of the output signal at the circuit output end (2) can be made quick and the current consumption in the output circuit can be suppressed.

[0018]

DETAILED DESCRIPTION OF THE INVENTION The present invention will be described below with reference to the drawings. FIG. 1 shows an example of an embodiment of the present invention, in which parts corresponding to those in FIG.
A description of this part will be omitted.

In FIG. 1, transistors Q1 to Q3,
The resistors R1 to R3 and the voltage sources V1 to V3 form a differential amplifier. Also, the transistor Q4 and the transistor Q1
1, the transistor Q12 and the voltage source VEE are connected in series to form an output circuit. The collector output of the transistor Q2, which is the positive phase output of the differential amplifier, is led to the output terminal 2 via the output transistor Q4 of the emitter follower configuration. The collector output of the transistor Q1, which is the negative phase output of the differential amplifier, is led to the base of the transistor Q11 via the level shift circuit LS1. The output terminal 2 is connected to the base of the transistor Q12 via the level shift circuit LS2. The load capacitance CL connected to the output terminal 2 is
It corresponds to the input capacitance of the next stage circuit.

FIG. 2A shows a configuration example of the level shift circuit LS1. It is composed of a transistor Q21, a current source transistor Q22, and a current limiting resistor R21 which are connected in series between power sources. The collector output of the transistor Q1 is applied to the base of the transistor Q21, and the emitter of the transistor Q21 is connected to the base of the transistor Q11. The voltage drop between the base and emitter of the transistor Q21 is used as a level shift. The current through transistor Q22 is set by the applied voltage Vcs to its base. The transistor Q22 and the resistor R21 correspond to a current source.

FIG. 2B shows a configuration example of the level shift circuit LS2. In the figure, the transistor Q3
1 and Q33 are level shift transistors, transistors Q32 and Q34 are current source transistors that set a current according to the voltage Vcs to the base, resistors R31 and R
32 is a current limiting resistor. This circuit is configured by forming the circuit of FIG. 2 (a) in two stages, and includes transistors Q33 and Q3.
The voltage obtained by dropping the level of 2Vbe from the potential of the output terminal 2 by 1 is applied to the base of the transistor Q12. The transistor Q32 and the resistor R31 correspond to the current source, and the transistor Q34 and the resistor R32 correspond to the current source.

Next, the operation of the ECL logic circuit will be described with reference to FIG. First, when a rising signal (H level) is input to the base input terminal of the transistor Q1 which is the circuit input terminal 1, one transistor Q1 of the differential pair becomes conductive and the other transistor Q2 becomes non-conductive. The potential of the collector of the transistor Q2, and hence the base of the output transistor Q4 becomes the potential VSS,
Make transistor Q4 conductive more deeply. The potential of the output terminal 2 drops from the potential VSS of the base of Q4 by the amount Vbe4 of the base-emitter voltage drop. At this time, the transistor Q1 is conductive. A current Ics1 flows through the collector of the transistor Q1 and a voltage drop occurs due to the resistor R1. Collector output of transistor Q1 (Vss-Ics1
R1) is applied to the base of the transistor Q11 via the level shift circuit LS1. As a result, the transistor Q11 becomes non-conductive and cuts off the collector current Ics2 'of the transistor Q12. The load capacitance CL is quickly charged by the collector current of the transistor Q4 and the output waveform rises.

On the other hand, the transistor Q which is the circuit input terminal 1
When the falling signal (L level) is input to the base input terminal of No. 1, one transistor Q1 of the differential pair becomes non-conductive and the other transistor Q2 becomes conductive. A current Ics1 flows through the collector of the transistor Q2, and the potential of the base of the output transistor Q4 is lowered by the voltage drop Ics1.R2 due to the resistor R2, so that the transistor Q4 is brought into a shallow conductive state. The emitter potential of the transistor Q4 is changed to VSS by the base-emitter voltage drop of the transistor Q4.
-Ics1 ・ Reduce to R2-Vbe4. The potential of the output terminal 2 follows this. At this time, since the transistor Q1 is non-conductive, no current flows in the collector of the transistor Q1 and no voltage drop occurs due to the resistor R1. The collector of the transistor Q1 becomes the ground potential Vss. The high potential Vss of the collector is applied to the base of the transistor Q11 via the level shift circuit LS1. The transistor Q11 becomes conductive. The potential of the output terminal 2 is applied to the base of the transistor Q12 via the level shifter LS2, and the collector current of the transistor Q12 is caused to flow to extract the electric charge from the load capacitance CL to lower the potential of the output terminal 2. When the potential of the output terminal 2 drops to a certain level, the base potential of the transistor Q12 connected to the output terminal 2 via the level shifter LS2 further drops, and the transistor Q12 that was operating as a current source becomes inactive. Therefore, when the level at the output end is lowered to some extent, a large current does not flow in the collector of the transistor Q11, and the charge withdrawal from the load capacitance CL ends.

In the conventional circuit shown in FIG. 4, assuming that the voltage value of the constant voltage source V2 is VEE, the power consumption is VEE × (I
cs1 + Ics2). Of these, Ics2 is the load capacity C
Since it is a current for extracting the charge from L, increasing the value increases the extraction speed and speeds up the gate speed. Along with this, there is a problem that power consumption increases.

On the other hand, in the circuit of the present invention shown in FIG. 1, assuming that the voltage value of the constant voltage source V2 is VEE and the voltage value VREF of the constant voltage source V4 is | VEE | ≧ | VREF |, the power consumption is VEE x Ics1 + VREF x Ics2 '. here,
Ics2 'is a transient current that flows only when the charge is extracted from the load capacitance CL, unlike the steady current Ics2.
REF x Ics2 'is a sufficiently small value. Power consumption
VEE x Ics1 + VREF x Ics2 ', which is approximately VEE x I
Since it becomes cs1, the power consumption can be reduced as compared with the conventional circuit shown in FIG.

FIG. 3 is a graph showing the load capacitance dependence of the output rise and fall times of the circuit of the present application and the conventional circuit shown in FIG. In the figure, the horizontal axis represents the load capacity (p
F), vertical axis is rise or fall time (nS)
Is shown. △ in the figure is the fall time of the conventional circuit,
Black Δ indicates the rise time of the conventional circuit, ○ indicates the fall time of the circuit of the present application, and black ○ indicates the rise time of the circuit of the present application. From the figure, it can be seen that high speed circuit operation is realized at the same time as low power consumption.

Further, the circuit of the present invention does not have a capacitor in the circuit unlike the conventional circuit shown in FIG. Therefore, when this circuit is formed by the gate array, there is no need to create a new matrix of the gate array and an increase in the chip area as described above.

[0028]

As described above, according to the ECL logic circuit of the present invention, the output of one of the differential transistor pair (Q1, Q2) generating complementary outputs is used as the emitter follower transistor of the emitter follower output circuit. (Q
4) includes an operation (Q12) of controlling the current source (Q11) of the emitter follower output circuit by the other output, and further shutting off the current source by the output of the emitter follower output circuit when the current source operates. Therefore, an ECL logic circuit and an amplifier circuit that operate at high speed with low power consumption can be obtained.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of an ECL logic circuit of the present invention.

FIG. 2 is a circuit diagram showing a configuration example of a level shift circuit.

FIG. 3 is a graph showing load capacitance dependence characteristics of rise and fall times of an ECL logic circuit of the present invention and a conventional ECL logic circuit.

FIG. 4 is a circuit diagram showing an example of a conventional ECL logic circuit.

FIG. 5 is a circuit diagram showing another embodiment of a conventional ECL logic circuit.

[Explanation of symbols]

Q1-Q5, Q11, Q12, Q21, Q22, Q21
-Q34 Transistors V1 to V5 Constant voltage sources LS1 and LS2 Level shift circuit CL Load capacitance Cc Differentiating circuit capacitors R1 to R4, R21, R31, R32 Resistance

─────────────────────────────────────────────────── --- Continuation of the front page (56) References JP-A-6-77810 (JP, A) JP-A-4-13310 (JP, A) JP-A-63-171022 (JP, A) JP-A-3- 32224 (JP, A) JP-A-6-162782 (JP, A) JP-A-4-61418 (JP, A) JP-A-4-61419 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) H03K 19/086

Claims (5)

(57) [Claims] 1. An ECL logic unit including a transistor differential pair, an emitter follower type first transistor having a base that receives one collector output of the transistor differential pair, and second and third transistors. An emitter follower output circuit including a series circuit, a first level shift circuit that level-shifts the other collector output of the transistor differential pair and supplies the level-shifted collector output to the base of the second transistor, and A second level shift circuit for level-shifting an emitter output and supplying the level-shifted emitter output to the base of the third transistor, the ECL logic circuit comprising: 2. An emitter follower including a series circuit including a transistor differential amplifier circuit, a first transistor of an emitter follower type which receives one output of the differential amplifier circuit, and second and third transistors. An output circuit, a first level shift circuit that level-shifts the other output of the differential amplifier circuit and supplies the level-shifted output to the base of the second transistor, and a potential at a connection point between the first and second transistors. And a second level shift circuit for level-shifting and supplying the level to the base of the third transistor. 3. The first level shift circuit receives the other collector output of the transistor differential pair or the other output of the differential amplifier circuit at the base, and the emitter is connected to the base of the second transistor. 3. An ECL logic circuit as claimed in claim 1 or claim 2, comprising a fourth transistor of the emitter follower type, which is provided with: and a first current source connected in series with the fourth transistor. The described amplifier circuit. 4. The second level shift circuit includes an emitter follower type fifth transistor having a base connected to the emitter of the first transistor, and a fifth transistor.
A second current source connected in series to the transistor and a base connected to the emitter of the fifth transistor,
An emitter follower type sixth transistor having an emitter connected to the base of the third transistor, and a third current source connected in series to the sixth transistor,
The ECL logic circuit according to claim 1 or the amplification circuit according to claim 2. 5. An ECL logic unit including a transistor differential pair for generating first and second outputs that complementarily change according to an input, and an input terminal for receiving a first output of the transistor differential pair. An output transistor circuit for driving a circuit output end by a circuit, and an output circuit of an emitter follower type including a current source connected to the circuit output end; and a first level of the circuit output end depending on a first level of the input.
Second output of the transistor differential pair deactivates the current source and a second level of the input sets the circuit output to a second output level. And a current source control means for activating the current source by the second output and deactivating the current source when the circuit output terminal transits from the first output level to the second output level. An ECL logic circuit comprising: