JP3451921B2 - Processor - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a processor, and more particularly to a technique for reducing the number of execution cycles and improving code efficiency by parallel processing.

[0002]

2. Description of the Related Art With the recent advancement in functionality and speed of microprocessor application products, a microprocessor having high processing performance (hereinafter simply referred to as "processor") is desired. And, as one of the techniques for realizing this, there is one that simultaneously executes a plurality of instructions in one cycle,
A VLIW (Very Long Instruction Word) type processor is one of the technologies.

This VLIW type processor statically analyzes the dependency relationship between instructions by a compiler or the like when generating an execution code, moves the instruction code, and generates an instruction stream with high execution efficiency. This method has a merit that the hardware can be simplified as compared with a superscalar processor that dynamically analyzes the dependency between instructions, and therefore the operating frequency can be easily increased.

However, in the VLIW system, since the instruction is generally treated as a fixed length, there are the following problems.

That is, a large number of bits is required to specify an instruction that handles a long constant, but a very large number of bits is not necessary to specify an inter-register operation instruction. There are variations in the number of bits. However, since the VLIW method handles an instruction as a fixed length, it is inevitable to use an excessive number of bits to specify an instruction that requires only a short number of bits, resulting in a large code size.

As one means for solving this problem, it is possible to make the instruction length variable.

FIG. 13 shows the configuration around the instruction register of a processor in which one instruction is composed of one or two instruction constituent elements (herein referred to as "unit") and which is capable of simultaneously executing three instructions. It is a block diagram shown. In the figure, the broken line represents the control signal. In FIG. 13, the unit queue 50 is an array of units and transfers the units to the instruction register in the order supplied from the instruction memory or the like.

In this configuration, the instruction register A52a and the instruction register B52b, the instruction register C52c and the instruction register D52d, the instruction register E52e and the instruction register F.
52f are paired, and the instruction is always stored in the instruction register with any one of the three registers of the instruction register A52a, the instruction register C52c, or the instruction register E52e as a head, and the two units are connected to form one instruction. Only when configured does the unit transfer to the other pair of instruction registers. Therefore, when the unit transferred to the instruction register A52a constitutes an instruction by the unit itself, the instruction register B52
No units will be transferred to b.

As can be seen from FIG. 13, in this configuration, which instruction register each unit of the unit queue 50 is transferred to is not uniquely determined. Also,
Which unit of the unit queue 50 is to be transferred to each instruction register is not uniquely determined. Therefore, the selectors 51a to 51d are controlled to select the unit to be transferred. Furthermore, the control of these selectors cannot be determined at once, and the control of the selectors 51a and 51b is first determined.
After determining the unit to be transferred to the instruction register C,
By referring to the information about the instruction length in this unit, the control of the selector 51c and the selector 51d is determined as shown by the broken line in the figure.

[0010]

However, the above-mentioned conventional processor has a problem that the delay in transferring from the unit queue to the instruction register becomes significantly large. This is because the control of the selector for the instruction register cannot be determined without referring to the information regarding the instruction length in the unit transferred to the preceding instruction register. Further, as the degree of parallelism increases, the number of instruction registers to be transferred increases, and this delay becomes even larger.

On the other hand, the correspondence between the units in the unit queue and the instruction register is made one-to-one, and the problem of delay due to the selector in the transfer from the unit queue to the instruction register, which has been a problem in the processor shown in FIG. 13, is solved. As a technique, there is one shown in FIG. In this processor, decoding is performed for all combinations of units that may form an instruction, and the decoding result is selected and used based on the instruction length information output from the preceding instruction decoder. Specifically, as indicated by the broken line in the figure, the control of the selector 51e is determined based on the information output from the first instruction decoder 53d, and based on the above information and the information output from the second instruction decoder 53e or the third instruction decoder 53f. The control of the selector 51f is determined.

However, in order to execute three instructions at the same time, five decoders for decoding an instruction having a length of two units are required, which causes a problem that the hardware becomes very large.

Therefore, the present invention has been made in view of the above problems, and provides a processor that can achieve both performance improvement and code efficiency improvement while overcoming the problem of hardware complication in parallel execution at the instruction level. The purpose is to do.

[0014]

In order to achieve the above-mentioned object, the processor according to claim 1 has a variable bit length.
Unit consisting of variable-length bit length included in the execution unit
A processor that can execute instructions in parallel,
An instruction supply and issue unit that fetches and outputs, and multiple interpreters
A step for solving the instruction output from the instruction supply and issue section.
The deciphering unit to read and the instructions deciphered by the deciphering unit are executed.
And an execution unit that executes the smallest bit among the unit instructions.
Except for unit instruction of G length, it is decoded by the decoding means.
A part and a part not decoded by the decoding means,
The maximum bit length of the execution unit depends on the plurality of decoding means.
It is characterized by being larger than the total bit length.

A processor according to claim 2 is the execution unit.
If the unit has the maximum bit length, the last unit of the execution unit is
The unit instruction is a unit instruction with the maximum bit length.
The processor according to claim 1, which is a characteristic of the processor.

The processor according to claim 3 has the maximum bit size.
The unit instruction with the same bit length is the same as the unit instruction with the smallest bit length.
Only a word element and a constant containing the same bit length operation
The unit instruction is composed of word elements, and the unit instruction
However, by one decoding means, the part of the minimum bit length is
Minutes are deciphered, according to claim 1 or 2.
It is a processor.

A processor according to claim 4 is the processor.
Furthermore, the decoder is not a target for decryption by the decryption unit.
And an instruction register for storing an instruction.
Data and the decryption means have a one-to-one correspondence
The processor according to any one of claims 2 to 3,
It

The processor according to claim 5 is the decoding unit.
When decoding a unit instruction with the maximum bit length,
Is the solution corresponding to the instruction register that stores the constant.
5. The program according to claim 4, wherein the reading means is invalidated.
It is a Rossa.

According to a sixth aspect of the present invention, in the processor, the unit instruction
Characterized in that the decree is composed of one or more word elements
The processor according to any one of claims 1 to 5.

The processor according to claim 7 issues the instruction.
The line supply unit instructs the decoding unit in units of a predetermined number of word elements.
An instruction, and each of the unit instructions has a predetermined number of word elements.
Depending on the location in the
7. The method according to claim 6, wherein whether or not the force is applied is uniquely determined.
It is a built-in processor.

A processor according to claim 8 is the execution unit.
Information about parallelism is explicitly added to the
The processor according to any one of claims 1 to 7, characterized in that
Is.

The processor according to claim 9 is characterized in that the parallel degree is
Is information on the boundary of the execution unit.
9. The processor according to claim 8, wherein:

The processor according to claim 10 is a unit instruction
Information about the length of the
Given in any one of claims 1 to 9 characterized in that
It is a built-in processor.

The processor according to claim 11, wherein the decryption is performed.
Command issue control unit that controls the length of the decoding result issued by the department
11. The method according to claim 1, further comprising:
The processor described there.

The processor according to claim 12 is the decoding device.
Decide whether to enable or disable the decoding result of each of the means
Further comprising a command issuing control unit for determining
A processor according to any one of claims 1 to 11.

A processor according to claim 13 is the processor
The instruction sequence executed by the sessa is statically transferred to the execution unit.
The method according to claim 1, wherein it is scheduled.
2 is a processor according to any one of

A processor according to claim 14 has a variable length.
Variable length bit length included in the execution unit consisting of bit length
Up to N (N: integer of 2 or more) unit instructions consisting of
Executable processor, bit of the execution unit
The length is not limited to the instruction length for instruction fetch, and it is variable.
Of the unit instructions with the maximum bit length
Predetermined bits that are shorter than the bit length of the execution unit for column execution
Professionals characterized by decoding only run units of length or less
It's Sessa.

A processor according to claim 15 is characterized in that the instruction is executed.
Decoding an execution unit longer than the fetched instruction length
15. The process according to claim 14, characterized in that
It's a sass.

A processor according to claim 16 has a variable length.
Variable length bit length included in the execution unit consisting of bit length
Up to N (N: integer of 2 or more) unit instructions consisting of
An executable processor, wherein the execution unit is a parallel processor
Information regarding the degree of line is explicitly added, and the unit
Actually execute N instructions with the maximum bit length in parallel
Execution with a predetermined bit length shorter than the bit length of each row
A processor characterized by decoding only units
It

A processor according to claim 17 is the processor.
The decoder has a decoding unit for decoding an instruction, and the decoding unit has
Among the unit instructions, the one with the maximum bit length is executed in parallel.
An instruction with a bit length shorter than the bit length of the execution unit
Any of claims 14 to 16 being provided.
The processor described in Crab.

A processor according to claim 18 has a variable length.
Variable length bit length included in the execution unit consisting of bit length
Processor that can execute up to N parallel unit instructions consisting of
The maximum length of the unit instruction is M bits (M:
Multiple integers (2 or more), the first fixed-length
The instruction is fetched in units of
Command supply and issue unit that outputs the unit
The second fixed-length bit output from the command supply issuing unit
Decoding that issues a variable length bit length decoding result out of the length
And the second fixed length is shorter than M × N bits.
With a processor that is limited to
is there.

The processor according to claim 19 is the second
Has a fixed length longer than the first fixed length.
19. The processor according to claim 18,

A processor according to claim 20 is the processor.
A set of bit lengths of the unit instructions that the sessa executes in parallel
The execution units are static so that the alignment meets the specified restrictions.
Claims that are dynamically scheduled
The processor according to item 19.

According to a twenty-first aspect of the present invention, in the processor, the predetermined
The limitation is that all the bit lengths of the second fixed length are issued.
In this case, at the end of the second fixed-length bit length,
Is a control in which a unit instruction with a bit length of M bits is arranged.
21. Processor according to claim 20, characterized in that
Is.

According to a twenty-second aspect of the present invention, in the processor, the predetermined
Is limited to the operation of the bit length output to the decoding unit.
Provide it so that the code is placed within the specified length from the beginning.
21. Professional according to claim 20, characterized in that it is a restricted limitation.
It's Sessa.

The processor according to claim 23, wherein the execution is performed.
Information related to the degree of parallelism is explicitly added to the unit.
19. The processor according to claim 14, wherein
is there.

A processor according to claim 24 is the parallel processor.
The information about the degree is the boundary of the execution unit.
24. The processor according to claim 23, which is a feature.

The processor according to claim 25 is a unit instruction.
Information about the length of the
25. Any one of claims 14 to 24 is provided.
The processor described in 1.

The processor according to claim 26 is characterized in that the decryption is performed.
Command issue control unit that controls the length of the decoding result issued by the department
23. The method according to claim 17, further comprising:
It is a processor described in some cases.

The processor according to claim 27 is the processor.
The instruction sequence executed by the sessa is statically transferred to the execution unit.
15. From claim 14, characterized in that it is scheduled.
26. The processor according to any one of 26.

[0041]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of a processor according to the present invention will be described below in detail with reference to the drawings. (Outline of Instruction Format and Architecture) First, the structure of an instruction (corresponding to a “unit instruction” described in the claims) executed and decoded by this processor will be described.

FIGS. 1A to 1E are diagrams showing the instruction format of this processor.

Each instruction of this processor is made up of a 21-bit instruction constituent element (herein referred to as a "unit", which corresponds to a "word element" described in the claims). There are two types of instruction formats, a 21-bit instruction composed of two and a 42-bit instruction composed of two units. The length of each instruction is determined by the 1-bit format information 11. Specifically, the format information 11 is “0”
In the case of, the unit itself becomes a 21-bit instruction, and when the format information 11 is "1", the unit and the subsequent unit are connected to form a 42-bit instruction.

Each instruction has 1-bit parallel execution boundary information 10. This information indicates whether or not there is a parallel execution boundary between this instruction and the instruction that follows it. Specifically, parallel execution boundary information 1
When 0 is “1”, there is a parallel execution boundary between the instruction and the subsequent instruction, and when parallel execution boundary information 10 is “0”, there is no parallel execution boundary. How to use this information will be described later.

Format information 11 from the instruction length of each instruction
The operation is specified in the part excluding the parallel execution boundary information 10. A 21-bit instruction can use a length of 19 bits, and a 42-bit instruction can use a length of 40 bits. Specifically, "Op1", "Op2",
In the “Op3” field, the operation code indicating the type of operation is set. In the “Rs” field, the register number of the register serving as the source operand is set to “Rd”.
Field specifies the register number of the register that is the destination operand. In addition, "imm
5 "and" imm32 "fields each have 5
Specifies the bit and 32-bit constant operands for the operation. In the "disp13" and "disp31" fields, 13-bit and 31-bit displacements are designated, respectively.

Transfer instructions and arithmetic instructions that handle long constants such as 32-bit constants, and branch instructions that specify large displacements are defined as 42-bit instructions, and most of the other instructions are defined as 21-bit instructions. .
As can be seen from FIG. 1, only a part of a long constant or a displacement is arranged in the rear unit, that is, the second unit of the two units which are the constituent elements of the 42-bit instruction. , Opcode is not placed.

Next, an outline of the architecture of this processor will be described.

This processor is a processor based on static parallel scheduling, and the concept of instruction supply and issue is as shown in FIG.

As shown in FIG. 10A, the instruction supply unit is an instruction supply unit having a fixed length of 64 bits per cycle (herein called "packet". It corresponds to "composite instruction" described in the claims. .) To supply 3 units each.
The length of 3 units is 63 bits, but the remaining 1
Not used for bits. And the execution of the instruction is
As shown in FIG. 6B, units (hereinafter referred to as “execution unit”) up to the boundary of parallel execution are simultaneously executed in one cycle. That is, in each cycle, the instructions up to the instruction whose parallel execution boundary information 10 is "1" are executed in parallel. Units that have been supplied but have not been executed remain in the instruction buffer, and are to be executed in the subsequent cycles.

That is, in this architecture, instructions are supplied in units of fixed length packets, and an appropriate number of units are issued in each cycle according to the degree of parallelism based on the statically obtained information. ,It turns out that. By adopting this method, the non-operation instruction (nop instruction) generated in the VLIW method of the normal fixed length instruction is completely eliminated, and the code size can be reduced.

Depending on the value of the format information 11 in the instruction, two units may be executed as one instruction and one unit may be executed as one instruction.
By using this method, the long instruction format can be used only for some instructions that require a large number of bits to specify instructions, and the short instruction format can be specified for most other instructions. Therefore, the code size can be further reduced. A specific example will be described later. (Hardware Configuration of Processor) Next, the hardware configuration of the present processor will be described.

FIG. 3 is a block diagram showing the hardware configuration of the processor according to the present invention.

This processor is a processor which executes a maximum of three instructions in parallel in one cycle.
The instruction supply / issuing unit 20, the decoding unit 30, and the execution unit 40 are included.

The instruction supply / issuance section 20 supplies an instruction group from an external memory (not shown) and outputs it to the decoding section 30, and comprises an instruction fetch section 21, an instruction buffer 22 and an instruction register 23.

The instruction fetch unit 21 uses a 32-bit IA
A block of units is fetched from an external memory (not shown) through an (instruction address) bus and a 64-bit ID (instruction data) bus, held in an internal instruction cache, and corresponds to an address output from the PC section 42. The unit group is supplied to the instruction buffer 22.

The instruction buffer 22 is provided with two 63-bit buffers and is used for accumulating the units supplied by the instruction fetch unit 21. A packet is supplied from the instruction fetch unit 21 to the instruction buffer 22 in units of 64 bits. Here, the most significant 1-bit information of the packet is not used. Instruction buffer 22
The unit stored in 1 is output to an appropriate register of the instruction register 23. The instruction buffer 22 is shown in more detail in another drawing.

The instruction register 23 is made up of four 21-bit registers and holds the unit sent from the instruction buffer 22. Instruction register 23
Regarding the periphery, a more detailed structure is shown in another drawing.

The decoding section 30 decodes the instruction held in the instruction register 23 and outputs a control signal according to the decoding result to the execution section 40. The decoding section 30 is roughly divided into an instruction issue control section 31 and an instruction. It consists of a decoder 32.

The instruction issue control unit 31 includes an instruction register 23.
The parallel execution boundary information 10 and the format information 11 in the unit are stored in the four registers
By referring to, the control is performed such that the two units are treated as one instruction, and the issuance of a unit that crosses the boundary of parallel execution is invalidated. The operation of the instruction issue control unit 31 will be described in more detail in another drawing.

The instruction decoder 32 is a device for decoding the instruction group stored in the instruction register 23, and comprises a first instruction decoder 33, a second instruction decoder 34 and a third instruction decoder 35. These decoders basically decode one instruction in one cycle and give a control signal to the execution unit 40. In addition, the constant operand placed in the instruction is transferred from each instruction decoder to the data bus 48 of the execution unit 40.

The execution unit 40 is a circuit unit that executes a maximum of three instructions in parallel based on the decoding result of the decoding unit 30, and includes an execution control unit 41, a PC unit 42, a register file 43, and a first operation unit 44. , The second operation unit 45, the third operation unit 46, the operand access unit 47 and the data bus 48,
It consists of 49.

The execution control unit 41 is a general term for control circuits and wirings for controlling the respective constituent elements 42 to 49 of the execution unit 40 based on the result of the decoding by the decoding unit 30, and includes timing control, operation permission / prohibition control, and status. It has circuits for management and interrupt control.

The PC (program counter) unit 42 outputs to the instruction fetch unit 21 of the instruction supply and issue unit 20, the address in the external memory (not shown) where the instruction to be decoded and executed next is placed.

The register file 43 is composed of 32 32-bit registers R0 to R31. The values stored in these registers are passed through the data bus 48 based on the decoding results of the first instruction decoder 33, the second instruction decoder 34, and the third instruction decoder 35, and the first operation unit 44, the second operation unit 44, and the second operation unit 44. Transferred to the calculation unit 45 and the third calculation unit 46,
Thereupon, an operation is performed, or after simply passing therethrough, the data is sent to the register file 43 or the operand access unit 47 via the data bus 49.

The first arithmetic unit 44, the second arithmetic unit 45 and the third arithmetic unit
The operation unit 46 internally has an ALU and a multiplier that perform an arithmetic logic operation on two pieces of 32-bit data, and a barrel shifter that performs a shift operation, and executes the operation under the control of the execution control unit 41. .

The operand access unit 47 is a circuit that transfers operands between the register file 43 and an external memory (not shown). Specifically, for example,
When “ld” (load) is placed as the opcode in the instruction, the 1-word (32-bit) data placed in the external memory is designated in the register file 43 via the operand access unit 47. When it is loaded into the register and "st" (store) is placed as the operation code, the stored value of the designated register of the register file 43 is stored in the external memory. The PC unit 42, the register file 43, the first arithmetic unit 4
4, the second operation unit 45, the third operation unit 46, and the operand access unit 47 are connected to the data bus 48 as shown.
(L1 bus, R1 bus, L2 bus, R2 bus, L3 bus, R3 bus) and data bus 49 (D1 bus, D2 bus, D3 bus). The L1 bus and the R1 bus are respectively connected to the two input ports of the first arithmetic unit 44, the L2 bus and the R2 bus are respectively connected to the two input ports of the second arithmetic unit 45, and the L3 bus and the R3 bus are respectively the third arithmetic unit. D1 bus, D2 on the two input ports of section 46
The bus and the D3 bus are connected to the output ports of the first arithmetic unit 44, the second arithmetic unit 45, and the third arithmetic unit 46, respectively. (Detailed Configuration of Instruction Buffer) Next, a detailed configuration of the instruction buffer 22 will be described.

FIG. 4 is a block diagram showing a detailed structure of the instruction buffer 22.

The instruction buffer 22 is the instruction buffer A 221.
And an instruction buffer B222, which are two 63-bit buffers, each capable of holding three units. The instruction buffer A221 is buffers A0 and A
1 and A2, each of which can hold one unit. Similarly, instruction buffer B consists of buffers B0, B1 and B2.

The instruction buffer 22 includes an instruction fetch unit 2
Packets are supplied in units of 1 to 64 bits. However, the most significant 1-bit information of the packet is not used. At this time, the instruction buffer A221 and the instruction buffer B2
It is not supplied over 22 and is supplied to any of the buffers in 63-bit units. The units stored in the instruction buffer 22 maintain the order of supply, and the order and which buffer is valid are managed as a state by the instruction buffer control unit 223.

The instruction buffer control section 223 controls the selectors 224a to 224d in order to sequentially transfer the valid units in the buffer every cycle to the instruction register 23. By this control, the first four units in the instruction buffer 22 are transferred to the instruction register 23. further,
Information from the instruction issue control unit 31 of the decoding unit 30 indicating how many units among the units transferred to the instruction register 23 remain without being issued, and the instruction fetch unit 21.
The state of the instruction buffer 22 is updated based on the information indicating which unit is valid among the units transferred from.

Specifically, when the instruction buffer 22 is empty and a branch is made to the second unit of a packet, the instruction fetch unit 21 supplies the packet, and the supplied packet is the instruction buffer. It is transferred to A221. The first unit of the packet is invalid, so
Under the control of the instruction buffer control unit 223, as the state of the instruction buffer 22, only the buffer A1 and the buffer A2 are valid.

In the next cycle, when the unit transferred from the instruction buffer 22 to the instruction register 23 is not issued at all and the instruction fetch unit 21 supplies a valid packet of 64 bits, the packet is the instruction buffer B22.
2 and the state of the instruction buffer 22 is buffer A
1, A2, B0, B1 and B2 are valid.

Further, in the next cycle, since the instruction buffer 22 has no free space, the supply from the instruction fetch unit 21 is not accepted and the instruction register 23 sequentially receives the buffer A.
1, the units of buffer A2, buffer B0, and buffer B1 are transferred.

As described above, packets are supplied from the instruction fetch unit 21 only when the instruction buffer 22 has a free space in units of 63 bits, and the order of supply is managed,
In each cycle, the first four units in the order supplied are transferred to the instruction register 23. (Structure around instruction register 23 and operation of instruction issue control unit 31) Next, the structure around the instruction register 23 is shown and the detailed operation of the instruction issue control unit 31 will be described.

FIG. 5 is a block diagram showing the configuration around the instruction register 23. In the figure, dashed arrows represent control signals.

The instruction register 23 is the instruction register A23.
1. It consists of four 21-bit registers: instruction register B232, instruction register C233, and instruction register D234. Units are supplied to the instruction register 23 from the instruction buffer 22, but for the sake of clarity, let us consider the concept of a unit queue 50, which is an array of units supplied from the instruction buffer 22. Then, here, it is considered that the unit is supplied from the unit queue 50 to the instruction register 23.

As can be seen from FIG. 5, which instruction register 23 a unit is transferred to is determined by
It is uniquely determined by the position (order) in the unit queue 50. That is, the unit 1 goes to the instruction register A231,
Unit 2 will be transferred to instruction register B 232. As a result, when transferring from the unit queue 50 to the instruction register 23, a selector for selecting a unit, which is present in the conventional example of FIG. 13, becomes unnecessary, the hardware is simplified, and the delay is minimized. It is limited to the limit.

Each of the instruction decoders 33 to 35 in the figure has 21
It takes a unit of bits as an input, decodes it, outputs a control signal related to the operation of an instruction formed by the unit to the execution control unit 41, and outputs a constant operand arranged in the unit. As can be seen from the instruction format in FIG. 1, only a part of the constant operand is arranged in the second unit of the two units forming the 42-bit instruction. In other words, since there is no opcode in this unit, there is no need to input it to the instruction decoder. Therefore, as shown in FIG. 5, the constant operand of each instruction is a combination of the constant in the unit output by the instruction decoder and the constant unconditionally directly transferred from the instruction register. Reference numerals 60 to 62 in FIG. 5 are constant operands of each instruction.

A 1-bit non-operation instruction flag is input as a control signal to each instruction decoder. When this flag is set to "1", the decoder outputs a non-operation instruction as an output. That is, by setting the non-operation instruction flag, decoding as an instruction of the instruction decoder can be invalidated.

The operation of the instruction issuance control unit 31 for controlling the combination of the units stored in the instruction register 23 to issue an instruction will be described below.

The instruction issue control unit 31 uses the instruction register A2.
31 and the parallel execution boundary information 10 and the format information 11 of each unit stored in the instruction register B232, the instruction decoder is controlled.

First, from these information, the instruction register 2
How much of the unit stored in 3 is to be issued in this cycle is calculated. Then, information about how many units remain without being issued is transmitted to the instruction buffer control unit 223 in the instruction buffer 22.

Next, the instruction decoder 32 is controlled so that only the instruction issued in this cycle is decoded. As can be seen from FIG. 5, the unit that may be decoded as an instruction is the instruction register A231,
Only the units stored in the instruction register B232 and the instruction register C233. Therefore, by referring to the information in the unit, with respect to the second unit of the 42-bit instruction and the one which remains without being issued among these units, the decoding as the instruction of the unit is invalidated. The unit corresponding to the second unit of the 42-bit instruction is directly output as a part of the constant operand of the instruction formed by the immediately preceding unit.

Specifically, when the format information 11 of the unit (unit 1) of the instruction register A231 is "1", the unit 1 and the unit (unit 2) of the instruction register B232 are connected to form a 42-bit instruction. Therefore, the decoding as the instruction of unit 2 is invalidated,
That is, the non-operation instruction flag of the second instruction decoder 34 is set to "1". In FIG. 5, the instruction issue control unit 3
The broken line from 1 to the second instruction decoder 34 corresponds to this operation. The unit 2 is directly output as a part of the constant operand 60 of the instruction formed by the unit 1.

Further, the format information 11 of the unit 1
Is "0" and the format information of the unit 2 is "1", the unit 2 and the unit (unit 3) of the instruction register C233 are connected to form a 42-bit instruction. Cancel, that is, the non-operation instruction flag of the third instruction decoder 35 is set to "1". In FIG. 5, the instruction issue control unit 3
The broken line from 1 to the third instruction decoder 35 corresponds to this operation. The unit 3 is directly output as a part of the constant operand 61 of the instruction formed by the unit 2.

As described above, by referring to the format information 11, the non-operation flag of the instruction decoder is set as necessary, and the decoding as the instruction is invalidated.

Then, when the parallel execution boundary information 10 of the unit 1 is "1" and the format information 11 is "0", only the unit 1 is issued in this cycle, so that the decoding as the instruction of the units 2 and 3 is performed. Is invalidated, that is, the non-operation instruction flags of the second instruction decoder 34 and the third instruction decoder 35 are both set to "1". In FIG. 5, broken lines from the instruction issue control unit 31 to the second instruction decoder 34 and the third instruction decoder 35 correspond to this operation.

Further, the parallel execution boundary information 10 of the unit 1
Is “0”, the parallel execution boundary information 10 of the unit 2 is “1”, and the format information 11 is both “0”,
Since only unit 2 is issued in this cycle, decoding as an instruction of unit 3 is invalidated.
That is, the non-operation instruction flags of the third instruction decoder 35 are both set to "1". In FIG. 5, the broken line from the instruction issue control unit 31 to the third instruction decoder 35 corresponds to this operation.

As described above, by referring to the parallel execution boundary information 10, the non-operation flag of the instruction decoder is set as necessary, and the decoding as the instruction is invalidated.

FIG. 6 shows the configuration of the instruction issue control unit 31 and its peripheral circuits that realize the above-described instruction issue control.

As described above, the instruction issue control unit 31 causes the unit parallel execution boundary information 10 and the format information 1 stored in the instruction register A 231 and the instruction register B 232.
1 is output, and a control signal serving as a non-operation instruction flag for determining whether to invalidate the decoding as the instruction of the second instruction decoder 34 and the third instruction decoder 35 is output.

By taking the circuit configuration as shown in FIG.
The second instruction decoder 34 is invalidated when the parallel execution boundary information 10 of the unit stored in the instruction register A 231 is “1” or the format information 11 of the unit is “1”. Also, the third instruction decoder 35 determines whether the parallel execution boundary information 10 of the unit stored in the instruction register A 231 or the unit stored in the instruction register B 232 is “1”, or the unit stored in the instruction register B 232. Invalidated when the format information 11 is "1".

As described above, the instruction format as shown in FIG. 1 is adopted, and the simple circuit as shown in FIG. 6 is prepared. It can be carried out.

By adopting the instruction issue control method as described above, some restrictions are imposed on the combination of instruction lengths of instructions that can be issued simultaneously in one cycle. FIG. 7 shows a combination of instruction lengths of instructions that can be simultaneously issued by this processor.

As can be seen from FIG. 7, in this processor, only the third unit from the beginning of the unit sequence can be decoded as an instruction. That is, the patterns (a) to (h) in the figure can be issued. Up to 4 units can be issued at the same time. However, among the patterns for issuing four units, the patterns (i) and (j) in the figure cannot be issued simultaneously. (Comparison with Conventional Instruction Issue Control Method) Here, a comparison is made between the processor of this embodiment and a conventional processor not according to the present invention.

First, in the conventional example shown in FIG. 13, in the transfer from the unit queue 50 to the instruction register,
Although the delay due to the selector has been a problem, in the processor of the present invention, the units in the unit queue 50 and the respective instruction registers correspond to each other in a one-to-one manner, so that the selectors 51a to 51d that are present in FIG. 13 are unnecessary. Next to
The above delay problem has been resolved.

In the configuration of FIG. 13, as the parallelism increases and the number of instruction registers to be transferred increases, the number of selectors increases and the delay further increases. Since the correspondence between the unit queue 50 and the instruction register is one-to-one, the delay does not increase.

On the other hand, it is also proposed to apply this variable length instruction method to a processor which executes parallel execution in a superscalar method. For example, the paper The Approach to Multi
pleInstruction Execution in the GMICRO / 400 Process
or (PROCEEDINGS, The Eighth TRON Project Symposiu
GM disclosed in m (International), 1991)
There is ICRO / 400. This technique has a limit in order to reduce the hardware while taking the concept of FIG.

FIG. 15 is a block diagram showing the configuration around the instruction register when the instruction issue control method adopted in GMICRO / 400 is adopted. In FIG.
The dashed lines represent control signals and 54a and 54b represent constant operands specified within the instruction. The instruction decoder decodes the input instruction, outputs a signal that controls the execution of the instruction to the execution control unit as a result, and also outputs a constant operand specified in the instruction.

In the GMICRO / 400 instruction issue control method, the unit 1 and the unit 2 are connected, the unit 2 and the unit 3 are once decoded,
When it is determined by the decoding of the first instruction decoder 53i whether the first instruction is a one-unit length instruction or a two-unit length instruction, the selector 51g and the selector 51h.
By controlling, the decoding result of the second instruction decoder 53j or the third instruction decoder 53k is selected and used.

As can be seen from FIG. 15, GMICR
In the O / 400, the fourth instruction decoder 53g and the fifth instruction decoder 53h are deleted by reducing the number of concurrently executable instructions from 3 to 2 in the configuration of FIG.
Also, the second instruction decoder 53j and the third instruction decoder k
Reduces the hardware by setting the input bit width to 1 unit. However, this causes a limitation that the second instruction to be simultaneously executed is only one unit length instruction.

Even if the hardware is reduced as described above, three instruction decoders are required to enable simultaneous issuance of two instructions, and there is a problem that the amount of hardware is still large.

In the configuration of FIG. 15, the selectors 51g and 51h are used until the decoding of the first instruction decoder 53i is completed.
Can not determine the control of. Until the control of this selector is determined, it is not possible to determine which decoding result of the second instruction decoder 53j or the third instruction decoder 53k is used as the second instruction, and the reading of the stored value of the register that is the operand cannot be started. . A method may be considered in which the stored values of all registers that may be operands are read out in advance and selected and used, but this is not practical because the number of read ports of the register file increases. As described above, in the configuration of FIG. 15, the delay until the register to be read is determined becomes large. In fact, GM
In the ICRO / 400, the stage immediately after the instruction decoding stage does not execute the operation, and the operand is read out.

Further, in the configuration of FIG. 15, as the parallelism increases and the number of units that can be simultaneously issued increases, the number of selectors increases and the control becomes complicated.

As described above, the parallel scheduling can be realized and the performance can be improved by the static scheduling, but there is a problem that the code size becomes large. Further, there is a variable length instruction method as a means for reducing the code size, but there is a problem that the hardware becomes complicated.

Then, the GMICRO / 4 shown in FIG.
In the example of 00, even if three instruction decoders are prepared, a maximum of two instructions cannot be executed at the same time, whereas if the instruction issue control method of the processor of the present invention is used, a maximum of three instructions can be executed by three instruction decoders. Can be executed simultaneously. On the contrary, in the present invention, when it is assumed that a maximum of two instructions are simultaneously issued, two instruction decoders can be used. A specific configuration around the instruction register is as shown in FIG. This can reduce hardware.

In the configuration of FIG. 15, the selectors 51g and 51h are used until the decoding of the first instruction decoder 53i is completed.
Control cannot be determined, and which decoding result of the second instruction decoder 53j or the third instruction decoder 53k is to be used as the second instruction cannot be determined. Therefore, the delay until the register that becomes the operand is determined becomes large. On the other hand, in the configuration of the processor of the present invention,
Since the register that becomes the operand can be determined without waiting for the decoding result of another decoder, the reading of the register that becomes the operand can be started in the first half of the decoding stage. As a result, at the completion of the decryption stage,
The reading of the register that is the operand can also be completed. As a result, the operation can be executed in the stage immediately after the decoding stage, and the execution efficiency can be improved.

Further, in the configuration of the present invention, even if the number of units that can be simultaneously issued increases, it is sufficient to simply increase the number of decoders, whereas in the configuration of FIG. 15, the number of units that can be simultaneously issued. However, there is a problem in that the number of selectors increases and the control becomes complicated as the number increases.

Then, there are the following differences due to the difference in instruction format. In the present invention, as shown in FIG.
Since only a part of the constant operand is arranged in the second unit of the 2-unit length instruction, the second unit is directly output as an operand without being input to the instruction decoder as shown in FIG. Therefore, all instruction decoders need only decode instructions that are one unit long. On the other hand, in the GMICRO / 400, since the operation code is also arranged in the second unit of the instruction of 2 unit length, the first instruction decoder 53i needs to decode the instruction of 2 unit length in the configuration of FIG. Yes, the hardware is increased compared to the configuration of the present invention. (Operation of Processor) Next, the operation of the processor of the present embodiment when a specific instruction is decoded and executed will be described.

FIG. 8 is a flow chart showing an example of processing for handling a 32-bit constant.

In the processing shown in the figure, the 32-bit constant "0x87665421" is transferred to the register R1 (step S100), the value stored in the register R5 is transferred to the register R0 (step S101), and the register R0 is stored. The value stored in the register R1 is added to the stored value (step S10).
2) The value stored in the register R2 is added to the value stored in the register R3 (step S103), and the value stored in the register R0 is stored in the memory at the address indicated by the value stored in the register R4 (step S104). The stored value is transferred to the register R6 (step S105), and finally the stored value of the register R3 is transferred to the register R7 (step S106).

FIG. 9 is a diagram showing an example of an execution code and an execution image of a program which causes this processor to perform the processing shown in FIG.

This program is composed of seven instructions, and three packets 70 to 7 are provided as an instruction supply unit.
It consists of two. The processing content of each instruction is represented by a mnemonic placed in each field of the execution code. Specifically, the mnemonic “mov” represents the transfer of the constant and the stored value of the register to the register, the mnemonic “add” represents the addition of the constant and the stored value of the register and the stored value of the register, and the mnemonic “add”. st ”
Represents the transfer of the value stored in the register to the memory.

The constants are represented by hexadecimal numbers.
In addition, “Rn (n = 0 to 31)” is the register file 4
3 shows one of the registers. The parallel execution boundary information 10 and the format information 11 of each instruction are also indicated by "0" or "1".

The operation of this processor for each execution unit in the processing shown in FIG. 8 will be described with reference to FIG. 9B. (Execution Unit 1) The packet 70 is supplied from the memory, and the units in the packet 70 are sequentially transferred to the instruction register 23. next,
The instruction issue control unit 31 sets the parallel execution boundary information 1 of each unit.
The issuing is controlled by referring to 0 and the format information 11.
Specifically, the format information 11 of the first unit
Is "1", the first unit and the second unit are connected and treated as one instruction. That is, the non-operation instruction flag of the second instruction decoder 34 is set to "1" to invalidate the decoding as an instruction. Further, the parallel execution boundary information 10 of the first unit is “0”, and 3
Since the parallel execution boundary information 10 of the second unit is "1", two instructions up to the third unit are issued.
Since all supplied units are issued, no units are stored in the instruction buffer 22.

In the execution section 40, the constant "0" is stored in the register R1.
x87654321 ″ is transferred, and the stored value of the register R5 is transferred to the register R0. (Execution unit 2) The packet 71 is supplied from the memory, and the units in the packet 71 are transferred to the instruction register 23 in order. Since the unit common format information 11 is "0",
Both units are 21-bit instructions. Also, the parallel execution boundary information 10 of the first unit is “0”,
Since the parallel execution boundary information 10 of the second unit is "1", two instructions up to the second unit are issued. The third unit remains unissued and is thus stored in the instruction buffer 22.

In the execution unit 40, the stored value of the register R0 is added to the stored value of the register R1 and stored in the register R0, and the stored value of the register R3 is added to the stored value of the register R2 and stored in the register R3. . (Execution Unit 3) The packet 72 is supplied from the memory, and the instruction buffer 22
1 in the packet and 2 in packet 72
The individual units are sequentially transferred to the instruction register 23.
Since the format information 11 of the three units is "0", all units are 21-bit instructions. In addition, since the parallel execution boundary information 10 of the first unit and the parallel execution boundary information of the second unit are “0” and the parallel execution boundary information 10 of the third unit is “1”, Issue 3 instructions up to the unit. Now, all the supplied units have been issued.

In the execution unit 40, the value stored in the register R0 is transferred to the address indicated by the value stored in the register R4 in the memory, the value stored in the register R0 is transferred to the register R6, and the value stored in the register R3 is transferred to the register R7. Transferred to.

As described above, the program for performing the processing shown in FIG. 8 is executed in three execution units in this processor. The execution code consists of one 42-bit instruction and two 42-bit instructions.
The code size is 168 bits because six 1-bit instructions are used. (Comparison with Conventional Fixed-Length VLIW System Processor) Next, assume that the processing shown in FIG. 8 is executed by a VLIW system processor with a fixed instruction length, which is one of the conventional techniques. , In comparison with the case of the processor according to the present invention.

In the simple VLIW method of issuing a fixed number of fixed length instructions every cycle, if the instruction length that can specify a 32-bit constant transfer instruction is one instruction, the code size becomes very large. Therefore, the instruction length is 32 bits, and the transfer of a 32-bit constant is divided into 2 instructions by 16 bits.

FIG. 10 is a diagram showing an example of an execution code and an execution image of a program which causes a processor of the VLIW system whose instruction length is fixed to 32 bits to perform the processing shown in FIG.

This program includes four packets 73-
It is composed of 76. The processing content of each instruction is represented by a mnemonic placed in each field, as in the code shown in FIG. However, the mnemonic "se
"thi" indicates that a 16-bit constant is stored in the upper 16 bits of the register, and the mnemonic "setl" is used.
“O” indicates that a 16-bit constant is stored in the lower 16 bits of the register, and the mnemonic “nop” indicates that the instruction does nothing.

As can be seen by comparing the execution code of FIG. 10A with the execution image of FIG. 10B, in the VLIW method, the instruction supplied in each cycle is issued as it is. That is, three 32-bit instructions are issued every cycle. If there is no instruction that can be executed in parallel, it is necessary to insert a “nop” instruction by software in advance. Therefore, in this example also, four "no
Since the p ″ instruction is inserted and the code size is 12 32-bit instructions, the code size is 384 bits, which is significantly larger than the code size in the case of the processor according to the present invention.

Since the transfer of the 32-bit constant to the register is divided into two instructions, a new dependency relationship is created, and the number of execution units is four. No matter how the instructions are rearranged, the number of execution units cannot be reduced. As a result, the number of execution cycles is increased by one cycle as compared with the case of the processor according to the present invention. (Comparison with a conventional processor having information on a parallel execution boundary in a fixed-length instruction) Next, the processing shown in FIG. Assuming a case where a processor having a method of having information on whether or not there is in an instruction is performed, a comparison is made with the case of the processor according to the present invention.

In this system, a model having an instruction length of 32 bits and a model having an instruction length of 40 bits are considered. In the model with an instruction length of 32 bits, as in the case of the VLIW method of FIG.
Transfer of a 32-bit constant to the register is performed in two instructions. On the other hand, in the model with an instruction length of 40 bits,
All kinds of operations including transfer of a 32-bit constant to a register can be designated by one instruction.

FIG. 11 shows an example of a program execution code and an execution image for executing the processing shown in FIG. 8 by a processor of a system having a fixed instruction length of 32 bits and having parallel execution boundary information in the instruction. FIG.

This program is composed of eight instructions, and three packets 77 to 7 are provided as an instruction supply unit.
It is composed of nine. The processing content of each instruction is represented by a mnemonic placed in each field of the execution code. Transfer of a 32-bit constant to a register is shown in FIG.
As in the case of the VLIW system in which the instruction length is fixed at 32 bits, the instruction is divided into two instructions of 16 bits each.

As can be seen from FIG. 11, in this model, as in the case of the VLIW system of FIG. 10, the transfer of the 32-bit constant to the register is executed by dividing it into two instructions. Occurs, and the number of execution cycles is increased by one cycle as compared with the case of the processor according to the present invention.

Regarding the code size, since the insertion of the "nop" instruction does not occur, the code size is reduced from the code size in the case of the VLIW system of FIG. 10 by exactly the "nop" instruction, and eight 32-bit instructions are used. It has 256 bits. However, it is still larger than the code size in the case of the processor according to the present invention.

Next, a comparison is made with a model in which the instruction length is fixed at 40 bits.

FIG. 12 shows an example of a program execution code and an execution image for executing the processing shown in FIG. 8 by a processor having an instruction length fixed to 40 bits and having parallel execution boundary information in the instruction. FIG.

This program is composed of seven instructions, and three packets 80 to 8 are provided as an instruction supply unit.
It consists of two. The processing content of each instruction is represented by a mnemonic placed in each field of the execution code. Transfer of a 32-bit constant to a register can also be specified by one instruction.

As can be seen from FIG. 12, since transfer of a 32-bit constant to a register can be designated by one instruction in this model, the number of execution units is three,
The number of execution cycles is the same as that of the processor according to the present invention.

Although the number of instructions is the same as in the case of the processor according to the present invention, in the case of the processor according to the present invention, an instruction which does not require a long number of bits can be designated by a 21-bit instruction, but in this model, all The code size is 4 because the instruction must be specified as a 40-bit instruction.
Seven 0-bit instructions are 280 bits, which is larger than that of the processor according to the present invention.

As described above, regarding the processor according to the present invention,
Although described based on the embodiments, it goes without saying that the present invention is not limited to these embodiments. That is, (1) In the above embodiment, static scheduling is assumed, but the present invention is not limited to this. In other words, it can also be applied to a processor that performs dynamic scheduling like the superscalar method. In this case, the parallel execution boundary information in the instruction format is eliminated, and a parallel execution propriety detection device for dynamically detecting whether or not parallel execution is possible is provided in the decoding unit. The control performed by referring to the parallel execution boundary information may be performed by referring to the output of the parallel execution propriety detection device. Even with such a configuration, the significance of the present invention that the hardware can be simplified in the variable length instruction system is maintained. (2) In the above embodiment, three instructions are simultaneously executed, but the present invention is not limited to this number of simultaneously executed instructions. For example, the configuration may be such that two instructions are issued simultaneously. In this case, the configuration around the decoding unit and the instruction register may be changed as shown in the block diagram of FIG. 16, and the configuration of the arithmetic unit of the execution unit may be appropriately changed. (3) In the above embodiment, as can be seen from the instruction format of FIG. 1, one instruction is composed of one or two units, but the present invention is not limited to this number of units. Absent. That is, an instruction format may be defined in which three or more units are connected to form one instruction. For example, when an instruction is composed of 1 to 4 unit instructions, the format information in the instruction may be 2 bits. (4) In the above embodiment, as can be seen from the instruction format of FIG. 1, one instruction is composed of one or two units, but an instruction that is composed of a single unit does not necessarily exist. There is no. For example, one instruction may be composed of two or three units. In this case, the wiring connecting the instruction register, the instruction decoder and the constant operand may be changed. (5) In the above-described embodiment, as can be seen from the instruction format in FIG. 1, the instruction has information indicating whether or not it is the boundary of parallel execution, but this information is not always necessary. That is, a method may be adopted in which only the information regarding the format is included in the instruction, and when there is no instruction that can be executed in parallel, the “nop” instruction is arranged.
Even in this case, the significance of the present invention that the instruction can be specified in the instruction format having the length necessary for specifying each instruction is maintained. (6) In the above embodiment, as can be seen from the instruction format in FIG. 1, only a part of the constant operand is arranged in the second unit of the two units forming the 42-bit instruction. However, you may place an opcode in this unit. For that purpose, the unit output as a part of the constant operand in FIG. 5 may be changed to be input to the instruction decoder, and the input bit width of the instruction decoder may be increased. (7) In the above embodiment, the structure of the instruction buffer is shown in FIG. 4, but the present invention is not limited to this structure and the size of the buffer. For example, a single instruction buffer having a simple queue structure may be used.

[0136]

As is apparent from the above description, when the processor of the present invention is used for parallel execution at the instruction level.
Improve performance while overcoming the problem of hardware complexity
It is possible to achieve both improvement of code efficiency.

[Brief description of drawings]

FIG. 1 is a diagram showing a structure of an instruction executed by a processor according to an embodiment of the present invention.

FIG. 2 is a diagram showing a concept of instruction supply and issue in the processor.

FIG. 3 is a block diagram showing a hardware configuration of the processor.

FIG. 4 is a block diagram showing a detailed configuration of an instruction buffer 22 of the processor.

FIG. 5 is a block diagram showing a configuration around an instruction register 23 of the processor.

FIG. 6 is a diagram showing a circuit configuration of an instruction issuance control unit 31 and its peripherals of the processor.

FIG. 7 is a diagram showing a combination of instruction lengths of instruction groups that can be issued simultaneously by the processor.

FIG. 8 is a flowchart showing an example of processing for handling a 32-bit constant.

9 is a diagram showing an example of an execution code and an execution image of a program that causes the processor of FIG. 3 to perform the processing shown in FIG.

FIG. 10 is a diagram showing an example of a program execution code and an execution image for causing the conventional processor of the VLIW system in which the instruction length is fixed to 32 bits to perform the processing shown in FIG. 8;

FIG. 11 is a diagram showing an example of an execution code of a program and an execution image for executing the processing shown in FIG. 8 by a conventional processor of a method in which an instruction length is fixed to 32 bits and information of a parallel execution boundary is provided in an instruction.

FIG. 12 is a diagram showing an example of an execution code of a program and an execution image for executing the processing shown in FIG. 8 by a conventional processor of a method in which an instruction length is fixed at 40 bits and information of a parallel execution boundary is provided in the instruction.

FIG. 13 is a block diagram showing a configuration around an instruction register in a conventional processor.

FIG. 14 is a block diagram showing a configuration around an instruction register in a conventional processor.

FIG. 15 is a GMICRO which is an example of a conventional processor.
Block diagram showing the configuration around the instruction register in the / 400

FIG. 16 is a block diagram showing a configuration around an instruction register 23 in a processor according to another embodiment of the present invention.

[Explanation of symbols]

10 Parallel execution boundary information 11 Format information 20 Command Supply Issuing Department 21 Instruction fetch section 22 Instruction buffer 23 Instruction register 30 Decoding section 31 Instruction issue control unit 32 instruction decoder 33 First instruction decoder 34 Second instruction decoder 35 Third Instruction Decoder 40 Execution unit 41 Execution control unit 42 PC section 43 register file 44 First Operation Unit 45 Second operation unit 46 Third operation unit 47 Operand access part 48, 49 data bus 50 unit queue 221 Instruction buffer A 222 Instruction buffer B 223 Instruction buffer control unit 224a-224d selector 231 Instruction register A 232 Instruction register B 233 Instruction register C 234 Instruction register D

─────────────────────────────────────────────────── ─── Continued front page (72) Inventor Shuichi Takayama 1006 Kadoma, Kadoma City, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. (72) Kensuke Otani 1006 Kadoma, Kadoma City, Osaka Matsushita Electric Industrial Co., Ltd. (56) Reference JP-A-9-26878 (JP, A) JP-A-3-147021 (JP, A) JP-A-3-53325 (JP, A) JP-A-5-289870 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) G06F 9/30-9/42

Claims (27)

(57) [Claims] 1. Included in run unit consisting of variable bit length
Unit instructions consisting of variable-length bit lengths can be executed in parallel.
A processor that An instruction supply and issue unit that sequentially fetches and outputs instructions, It is equipped with a plurality of decoding means and is output from the instruction supply and issue section.
A decoding unit that decodes the instructions And an execution unit that executes the instruction decoded by the decoding unit.
Prepare, Of the unit instructions, except the unit instruction with the minimum bit length,
The part to be decrypted by the decryption means and the decryption means
Has an undeciphered part, The maximum bit length of the execution unit depends on the plurality of decoding means.
A process characterized by being larger than the total bit length.
Sa. 2. When the execution unit has the maximum bit length,
The last unit instruction of the execution unit has the maximum bit length
The process according to claim 1, which is a unit instruction.
Sassa. 3. The unit instruction with the maximum bit length is
Operate with the same bit length as the unit instruction of bit length
It consists of a word element that contains only the included word element and a constant, The unit instruction is read by one decoding means regardless of the bit length.
Is characterized in that the portion of the minimum bit length is decoded.
The processor according to claim 1 or 2. 4. The processor further includes a decoding unit.
Therefore, the instruction register that stores the instruction to be decoded
Have There is a one-to-one correspondence between the instruction register and the decoding means.
4. The method according to any one of claims 2 to 3, characterized in that
Processor. 5. The decryption means is a unit of the maximum bit length.
When decoding the order command,
Characterized by disabling the decryption means corresponding to the command register
The processor according to claim 4, wherein: 6. The unit instruction is composed of one or more word elements.
6. The method according to any one of claims 1 to 5, characterized in that
On-board processor. 7. The instruction issue supply unit is a unit of a predetermined number of word elements.
, Output the command to the decoding unit, Each of the unit instructions is a place in the predetermined number of word elements.
Depending on which of the plurality of decoding means is input.
7. The process according to claim 6, wherein the process is uniquely determined.
Sa. 8. Information about the degree of parallelism is disclosed in the execution unit.
8. All of claims 1 to 7, characterized in that
Processor described there. 9. The information regarding the degree of parallelism is the execution unit
9. The information according to claim 8, which is information regarding a boundary of
On-board processor. 10. Information about the length of the unit instruction is given for each
Claims characterized by being explicitly given in a unit command
Item 10. A processor according to any one of items 1 to 9. 11. The length of the decoding result issued by the decoding unit
A command issuing control unit for controlling the device is further provided.
The processor according to claim 1, wherein 12. The method according to claim 12, Validate the decoding result of each of the decoding means
Further, an instruction issue control unit that determines whether to perform or invalidate
It is provided with any one of Claim 1 to 11 characterized by the above-mentioned.
On-board processor. 13. The instruction sequence executed by the processor is
A special feature is that it is statically scheduled into execution units.
The process according to any one of claims 1 to 12,
Sa. 14. Included in the execution unit consisting of variable-length bit length
The maximum number of unit instructions consisting of variable length bit length is N
A processor capable of executing (N: an integer of 2 or more) in parallel
I mean The bit length of the execution unit is the same as the instruction length for instruction fetch.
Is variable without limitation, Among the unit instructions, the one with the maximum bit length is executed in parallel.
Less than a predetermined bit length shorter than the bit length of the execution unit to execute
A process characterized by decoding only the execution units below
Sa. 15. A length longer than an instruction length for fetching the instruction.
Characterized by being able to decipher the execution unit
The processor according to claim 14. 16. Included in the execution unit consisting of variable-length bit length
The maximum number of unit instructions consisting of variable length bit length is N
A processor capable of executing (N: an integer of 2 or more) in parallel
I mean Information regarding the degree of parallelism is explicitly added to the execution unit.
Has been done, Among the unit instructions, the one with the maximum bit length is executed in parallel.
Less than a predetermined bit length shorter than the bit length of the execution unit to execute
A process characterized by decoding only the execution units below
Sa. 17. The processor is a decoding unit for decoding instructions
Have The decoding unit has the largest bit length of the unit instructions.
Shorter than the bit length of the execution unit that executes N objects in parallel
A bit length instruction is provided.
The processor according to any one of 4 to 16. 18. Included in the execution unit consisting of variable-length bit length
Up to N unit instructions with variable length bit length
A processor that can execute in series, The maximum length of the unit instruction is M bits (M: 2 or more
Number) , Instruction fetch is performed in units of the first fixed-length bit length,
Instruction supply that outputs the second fixed length bit length as a unit
Issuer, Of the second fixed length output from the instruction supply and issue unit.
Issue the decryption result of variable length bit length.
And a decoding section that The second fixed length is limited to a length shorter than M × N bits
A processor characterized by being. 19. The second fixed length is greater than the first fixed length
19. The process according to claim 18, which is longer than
Sa. 20. The single processor that the processor executes in parallel
The combination of the bit lengths of the order instructions meets the specified limit.
As such, the run unit is statically scheduled.
20. The processor according to claim 19, characterized in that: 21. The predetermined limit is the second fixed length
When issuing all bit lengths, the second fixed length
The bit length consists of M bits at the end of the bit length.
Claim characterized by being a restriction that unit instructions are arranged
Item 21. The processor according to Item 20. 22. The predetermined limit is output to the decryption unit.
Within the bit length that is
Characterized in that it is a restriction provided to be arranged
21. The processor according to claim 20, wherein: 23. Information on the degree of parallelism is included in the execution unit.
15. It is explicitly given, or
18. The processor according to 18. 24. Information on the degree of parallelism is the execution unit.
24. The professional according to claim 23, which is a boundary of positions.
Sessa. 25. Information about the length of the unit instruction is given for each
Claims characterized by being explicitly given in a unit command
Item 25. The processor according to any one of Items 14 to 24. 26. The length of the decryption result issued by the decryption unit
A command issuing control unit for controlling the device is further provided.
23. The processor according to any one of claims 17 to 22. 27. The instruction sequence executed by the processor is
A special feature is that it is statically scheduled into execution units.
27. The process according to claim 14, wherein
Sa.