JP3444907B2 - Photoelectric conversion device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a photoelectric conversion device,
For example, it is suitable for use in a device for controlling accumulation of photoelectric conversion elements used in a focus detection device of a camera or the like configured by a sensor including a plurality of photoelectric conversion elements.

[0002]

2. Description of the Related Art As is well known, a photoelectric conversion element is adapted to obtain an electric signal corresponding to the amount of light emitted.
However, when the amount of light applied to the photoelectric conversion element is very small, there is a large proportion that does not depend on the amount of light occupying the output of the photoelectric conversion element generated in the photoelectric conversion signal reading section or the like.

Further, the photoelectric conversion section is constantly irradiated with light to generate unnecessary photoelectric conversion output, or the photoelectric conversion output is saturated depending on the irradiation time depending on the irradiation light amount, and this is the photoelectric conversion signal. It leaks into the reading section, and only by initializing the photoelectric conversion section, the error between the above-mentioned irradiation light quantity obtained from the obtained photoelectric conversion output and the actual irradiation light quantity becomes large.

Therefore, if any object image is used as it is as the object image information which is the photoelectric conversion element output of the sensor formed of these photoelectric conversion elements, it is possible to use this for any processing using the photoelectric conversion element output. The information for satisfying the requirement is unreliable and insufficient.

Therefore, as a means for solving these problems and obtaining an accurate photoelectric conversion element output, an unnecessary photoelectric conversion element output is swept out in advance before accumulating and reading out the required photoelectric conversion element output. , Is initialized to a predetermined value. In general, when sweeping out unnecessary photoelectric conversion element output, the same drive as that for reading out the necessary photoelectric conversion element output is performed, which takes a long time.

[0006]

In the conventional storage control as described above, it is necessary to give a drive synchronization signal from the main controller in order to drive the sweep-out of the unnecessary photoelectric conversion element output every time. Despite the required signal, this requires a considerable amount of time. Further, in the recent trend of increasing the number of pixels, more time is required. Therefore, for example, not only the time required for processing using information from the photoelectric conversion element output such as focus detection, but also a problem that the function is deteriorated in the entire system having a photoelectric conversion device having a storage control function for them. was there.

In view of the above problems, it is an object of the present invention to reduce the load on the main control unit, shorten the time required for a series of processes, and improve the function of the entire system.

[0008]

A photoelectric conversion device of the present invention comprises a photoelectric conversion region having a plurality of photoelectric conversion portions for accumulating charges photoelectrically converted according to an incident light beam, and a main control device and a signal are provided. A photoelectric conversion device for controlling the drive of the photoelectric conversion region by communicating with the device, and generating a first drive signal for driving the photoelectric conversion region based on a drive synchronization signal sent from the main control device. The second means for driving the photoelectric conversion region asynchronously with the drive synchronization signal sent from the main control device based on the first means for performing the second conversion signal and the second signal generated in the photoelectric conversion device. A driving means having a second means for generating a driving signal;
When the means is set to drive, the first means drives the photoelectric conversion area in synchronization with the drive synchronization signal based on the drive synchronization signal sent from the main controller. When it is controlled and the second means is set to drive, the second drive signal generated by the second means is not synchronized with the drive synchronization signal sent from the main controller. It is characterized in that it is controlled so as to drive the photoelectric conversion region based on the above. Another feature of the present invention is that an unnecessary signal is swept from the photoelectric conversion region when the second means is set to be driven.

Another feature of the present invention is that it includes a photoelectric conversion region having a plurality of photoelectric conversion units for accumulating charges photoelectrically converted according to an incident light beam, and a signal is transmitted between the main controller and a signal. A photoelectric conversion device that communicates to control the drive of the photoelectric conversion region, and generates a first drive signal for driving the photoelectric conversion region based on a drive synchronization signal sent from the main control device. A second means for generating a second drive signal for driving the photoelectric conversion region asynchronously with the drive synchronization signal based on the first means and a second signal generated in the photoelectric conversion device. When the first means is set to drive, the first means controls the drive synchronization signal based on the drive synchronization signal from the main controller. Photoelectric conversion in synchronization with When the second means is set to be driven, it is generated by the second means without being synchronized with the drive synchronization signal from the main controller. The photoelectric conversion region is controlled to be driven based on the second drive signal, the drive mode is changed based on the information input from the main controller, and the drive speed is changed according to the change of the drive mode. It is characterized by doing so. Another feature of the present invention is that an unnecessary signal is swept from the photoelectric conversion region when the second means is set to be driven.

[0010]

The photoelectric conversion device described above has a function of driving the photoelectric conversion region without being synchronized with the drive synchronization signal from the main control unit, and is driven to sweep out an output from the unnecessary photoelectric conversion region. Sometimes, the photoelectric conversion region can be driven based on a signal in the photoelectric conversion device, so that the main control device is caused to perform other processing when the output from the unnecessary photoelectric conversion region is swept out. Is possible.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the photoelectric conversion device of the present invention will be described below with reference to the drawings. FIG. 1 shows an embodiment of the present invention and is a block diagram showing an embodiment implemented in a camera equipped with a photoelectric conversion device.

In FIG. 1, PRS is a control device of the camera, for example, a CPU (central processing unit), a ROM,
A one-chip microcomputer (hereinafter referred to as a computer) in which a RAM, an EEPROM (electrically erasable programmable ROM), an A / D conversion function, an input / output port, and the like are arranged.

The computer PRS performs a series of camera operations such as an automatic exposure control device, an automatic focus adjustment function, film winding and rewinding in accordance with a camera sequence program stored in the ROM. for that reason,
The computer PRS is for communication signals SO, SI, SCL
Signals such as K and communication selection signals CLCM and CSDR are used to communicate with peripheral circuits in the camera body and the control device in the lens to control the operation of each circuit and lens.

The communication signal SO is a data signal output from the computer PRS, SI is a data signal input to the computer PRS, and SCLK is a synchronous clock of these communication signals SO and SI. The LCM is a lens communication buffer circuit, which supplies power to the lens power supply terminal VL when the camera is in operation, and the selection signal CLCM from the computer PRS is at a high potential level (hereinafter abbreviated as “H”). Further, when the low potential level is "L", it serves as a communication buffer between the camera and the lens.

When the computer PRS sets the selection signal CLCM to "H" and sends out predetermined data from SO in synchronization with the synchronous clock SCLK, the buffer circuit LCM causes SCLK and SO via the communication contact between the camera and the lens. The respective buffer signals LCK and DCL are output to the in-lens control circuit LPRS. At the same time, the signal DLC from the in-lens control circuit LPRS is output to the buffer signal SI, and the computer PRS inputs the lens data from SI in synchronization with the selection signal CLCM.

DDR is a switch detection and display circuit, which is selected when a signal for controlling the display circuit DDR is "H", and communication signals SO, SI, S are selected.
CLK, and is controlled by the computer PRS. That is, the display of the display member DSP of the camera is switched based on the data sent from the computer PRS, or the computer PRS is notified of the on / off states of various operation members of the camera.

The switches SW1 and SW2 are switches interlocked with a relays button (not shown), and the switch SW1 is turned on when the relays button is pressed in the first stage,
Then, the switch SW2 is turned on by the second-stage depression. The computer PRS performs photometry and automatic focus adjustment when the switch SW1 is turned on, and exposure control and subsequent film winding are performed when the switch SW2 is turned on.

The switch SW2 is a computer PR
The switch SW1 is connected to the "interrupt input terminal" of S
Switch SW2 even when the program when it is on is running
When turned on, an interrupt occurs, and control can be immediately transferred to a predetermined interrupt program.

MTR1 is a film feeding motor, MTR2 is a motor for mirror up / down, and shutter spring charging, and forward and reverse control is performed by respective drive circuits MDR1 and MDR2. The signal M input from the computer PRS to the drive circuits MDR1 and MDR2
1F, M1R and M2R are signals for motor control.

Next, MG1 and MG2 are shutter front curtain and rear curtain running start magnets, respectively, and drive signal SM
G1 and SMG2 are given to the amplifying transistors TR1 and TR2, and the transistors TRI and TR2 operate to be energized, so that the shutter control by the computer PRS is performed. Since the switch detection and display circuit DDR, the motor drive circuits MDR1 and MDR2, and the shutter control operation are not directly related to the present invention, detailed description thereof will be omitted.

LPRS is an in-lens control circuit, and a signal DCL input to the in-lens control circuit LPRS in synchronization with the signal CLK is data of an instruction from the camera to the taking lens LNS, and the lens operation in response to the instruction. Is predetermined. The control circuit LPRS analyzes the command according to a predetermined procedure, and outputs the focus adjustment and diaphragm operation, and the operation status of each part of the lens (drive status of the focus adjustment optical system, diaphragm drive status, etc.) from the output DCL.

When a command for focus adjustment is sent from the camera, the focus adjusting motor LMTR is driven based on the control signal in accordance with the drive amount direction sent at the same time to move the focus adjusting optical system in the optical axis direction. Move to and adjust the focus.
The amount of movement of the optical system is detected by the photocoupler that detects the pattern of the pulse plate that rotates in conjunction with the optical system, and is monitored by the pulse signal SENCF of the encoder circuit ENCF that outputs a number of pulses according to the amount of movement. The counter in the control circuit LPRS counts, and when the count value matches the amount of movement sent to the control circuit LPRS, the control circuit LPRS itself controls the focus adjustment motor LMTR.

Therefore, after the focus adjustment command from the camera is once sent, the camera control device computer PR
S does not have to be involved in the lens driving at all until the driving of the lens is completed. Also, the contents of the counter can be sent to the camera when requested by the camera.

Reference numeral SPC denotes a photometric sensor for exposure control, which receives light from a subject through a photographing lens, and its output SSPC is input to an analog input terminal of a computer PRS. Then, the input output signal SSPC is A / D converted and then used for automatic exposure control according to a predetermined program.

The sensor drive circuit SDR is a computer P
Accumulation control of the sensor device SNS is performed according to each signal input from the RS. With the data signal SO, the sensor device SNS is driven in a predetermined mode from among several prepared drive modes. Further, at this time, the driving state is displayed on the computer PR by the data signal SI.
It is configured so that S can be notified.

The signals φV and φH are used as synchronization signals for reading the image signal SOUT of the sensor device SNS depending on the drive mode selected by the data signal SO. Further, the signal φSCON is used for storage control of the sensor device SNS.

From the sensor drive circuit SDR to the sensor device SN
The signals φV1 and φV2 applied to S are vertical register transfer clocks, and φH1 and φH2 are horizontal register transfer clocks. Further, φR is a reset signal for the reading system, φSTR is a storage time control signal, and φSH is a signal for transferring charges generated according to the light received by the photosensitive portion to the vertical register.

The output VOUT of the sensor drive circuit SDR is
The image signal SOUT from the sensor device SNS is an image signal amplified by an amplification degree determined by the data signal SO output from the computer PRS. The image signal output VOUT is
The signal is input to the analog input terminal of the computer PRS, and the computer PRS performs A / D conversion of this signal and performs a series of AF processing and calculation based on the digital value. The sensor device SNS has a plurality of photoelectric conversion elements arranged two-dimensionally, and is drive-controlled by the sensor drive circuit SDR as described above.

Next, the sensor drive circuit SDR will be described in detail with reference to FIG. The block COM exchanges data with the computer PRS and receives the SDR selection signal CSDR.
The communication signals SCLK and SO are input and SI is output. When CSDR is "H", SDR is selected. The communication signals SCLK, SO, SI at this time are valid. Further, when it is recognized that the data is transmitted / received abnormally, the received data is invalidated.

The data SO from the computer PRS is
If it is recognized as normal after being received, the block BU
It is transferred to F, and its contents are held until the next SO reception. The block BUF can also send the information from the block CNT to the block COM via the block MCT and send it as data SI to the computer PRS.

The block MCT controls the blocks VGE, HGE, CGE and VAMP based on the contents held in the block BUF and the information from the block CNT. The block CNT has a function of counting the timing signal for generating the sensor device SNS drive signal output from the block VGE and the block HGE, and when the predetermined number is counted, the block MCT is notified of the information.

The block VGE is synchronized with the signal from the block SEN according to the information from the block MCT, or
It has a function of asynchronously generating the timing of the vertical transfer clocks φV1 and φV2. Also, block HG
E is a block SE based on the information from the block MCT.
ΦH1, φ synchronously or asynchronously with the signal from N
It has a function of generating the timing of H2. Further, the block RGE has a function of generating the timing of the reset signal φR at the time of read driving of the block SEN.

The block CGE has a timing generation function for φSH and φSTR. The block SEN has a function of detecting the signals .phi.V, .phi.H and SCON from the computer PRS with a reference clock inside the sensor drive circuit SDR. Block LSF is block VG
Based on the timing generation signals from E, HGE, RGE, and CGE, it has a function of performing level conversion to a signal level that becomes an optimum signal for the sensor device to be driven.

The block VAMP takes the difference of the dark current output from the image signal output SOUT from the sensor device SNS, and then
The amplification degree information determined by the data signal SO from the computer PRS is given from the block MCT, the difference in dark current output is amplified by this, and this is output as the image signal VOUT. Note that the dark current is an output value of a pixel in a light-shielded portion in the sensor, and the sensor drive circuit SDR temporarily holds a predetermined pixel output in a storage device such as a capacitor, and outputs it as an image signal. Performs differential amplification.

Next, the computer PRS and the data signal S
O and SI will be described. Table 1 shows the received data signal S
The contents of O are shown.

[0036]

[Table 1]

In Table 1, SSYNC0, SSYNC1
Is used to select the drive synchronization mode, G0 and G1 are used to select the amplification degree, and NC is used when reading the output of the built-in counting function. Table 2 shows the contents of the transmission data SI.

[0038]

[Table 2]

Each bit of CN0 to CN6 represents the count value of the vertical transfer clock φV1 which is the output during the read drive of the sensor device SNS, which is counted by the counting function built in the sensor drive circuit SDR. With this function, the status can be known when the read driving is performed without the synchronization signal from the computer PRS. Table 3 shows the types of drive modes.

[0040]

[Table 3]

In Table 3, SSYNC0, SSYNC
1 drives the image signal reading shift register built in the sensor device SNS in any one of modes 0, 1, 2, 3, by the 2-bit information. In mode 0, the read operation is stopped, and in mode 1, the vertical transfer clocks φV1 and φV2 are output each time the signal φV is detected, and the horizontal transfer clocks φH1 and φH2 are output each time the signal φH is detected, thereby reading the signal charge. To do.

In mode 2, the vertical transfer clock φV
1 and φV2 are output each time the signal φV is detected, and the horizontal transfer clocks φH1 and φH2 are output from the sensor drive circuit SDR.
Output according to the operation reference clock of. In mode 3, both the outputs of the vertical transfer clocks φV1 and φV2 and the outputs of the horizontal transfer clocks φH1 and φH2 are output according to the operation reference clock of the sensor drive circuit SDR.

The sensor drive circuit SDR has a function of counting the number of read pixels of the image signal by the shift register, and detects the synchronization signal φV or φH from the computer PRS in the drive mode 2 or mode 3 described above. Even when the reading is performed by reading, the output of the vertical transfer clocks φV1 and φV2 or the horizontal transfer clocks φH1 and φH2 is stopped when a predetermined number is counted.
Table 4 shows the amplification degree selection signals G1 and G0 for amplifying the image signal SOUT of the sensor device SNS and the amplification degree determined by the amplification degree selection signals G1 and G0.

[0044]

[Table 4]

The image signal SOUT is 5 times, 10 times, 20 times,
The image signal V amplified by one of the amplification factors of 40 times
It is output from the sensor drive circuit SDR as OUT. By setting this bit to "1", all the information received by the data signal SO other than this bit is invalidated, and this can be performed without affecting the drive control of the sensor drive circuit SDR to the sensor device SNS. Here, the information that can be known inside the sensor drive circuit SDR is output as the transmission data SI.

Next, the sensor device SNS will be described with reference to FIG. FIG. 7 is a block diagram showing an interline type area sensor including vertical L pixels and horizontal N pixels. In FIG. 7, VSHIFT is a vertical transfer register, which is driven by vertical transfer clocks φV1 and φV2 input from the sensor drive circuit SDR. HSHIF
T is a horizontal transfer register, which is a sensor drive circuit SD.
It is driven by horizontal transfer clocks φH1 and φH2 input from R. The SPD is a device having a photoelectric conversion function such as a photodiode, and sends a signal generated here to the vertical transfer register VSHIFT by φSH.

Further, the SPD can control the discharge and accumulation of the signal generated here by φSTR. φR
When the signal is transferred by HSHIFT and the signal is output from SOUT in synchronization with this, SOUT
This is a signal for initializing the output for each pixel in the signal amplification SAMP so that the influence of the output of the previous pixel does not affect the next output pixel in the output order of.

Next, the output of the sensor drive circuit SDR for driving the sensor having two-dimensionally arranged photoelectric conversion elements shown in FIG. 7 will be described with reference to the timing charts of FIGS. 3, 4 and 5. FIG. 3 shows one vertical transfer operation and L horizontal transfer operation in the drive started after receiving the data SO from the computer PRS for which the mode 1 of Table 3 is selected in the sensor drive circuit SDR. Shows.

Since the driving timing is described here, the notation is represented by two values of "H" and "L", and the analog output level of each driving signal is not the same. First, at time t1, computer PR
The signal φV from S becomes “H”. Sensor drive circuit SD
The R detects the input of φV = “H” at the time t2 by the internal reference clock SDRCLK, and first, in order to perform the vertical transfer of the sensor device SNS, the R first sets the vertical transfer clock φV1 to “H”. And at time t3 φV
Set 2 to "L".

Then, at time t4 after a predetermined time, φV2
Is returned to “H”, and φV1 is returned to “L” at time t. This completes one vertical transfer. Subsequently, at time t6, a signal φH = “H” is input from the computer PRS, and this is detected at time t7, and the vertical transfer clock φH1 is set to “H” and the reset signal φR is set to “H” to perform horizontal transfer. , And φH becomes “L” at time t8.
At time t9, φR is set to “L”. At time t10, φH2 is set to “H”, and at time t11, φH1 is returned to “L”. Then, at time t12, one horizontal transfer is completed.

Similarly, when φV = “H” is input at time t13, the second horizontal transfer is performed from time t14,
When this is repeated N times, the transfer for one horizontal line is completed at time t15. Then, when φV = “H” is input at time t16, the same operation as from time t1 to time t15 when φV1 is input to “H” at time t17 is detected. In this way, by repeating the operation from time t1 to time t15 L times, the read drive for one screen is completed.

Since the sensor drive circuit SDR has a counting function inside, even if φV = “H” is input during driving of one line consisting of N times, this is not accepted. Further, even if an input of φH = “H” is made during one horizontal transfer drive, it is not accepted.

FIG. 4 shows one horizontal transfer operation in driving which is started after the mode 2 shown in Table 3 is selected in the sensor drive circuit SDR and the data SO from the computer PRS is received. First, at time t1, the signal φV from PRS becomes “H”. The SDR uses the internal reference clock SDRCLK for φ at time t2.
In order to detect that V = “H” is input and to perform vertical transfer of the sensor device SNS, first, the vertical transfer clock φV1 is set to “H”, and φV2 is set to “L” at time t3.

Then, at time t4 after a predetermined time, φV2
Is returned to “H”, and φV1 is returned to “L” at time t5. This completes one vertical transfer. Then, the horizontal transfer clock φH1 is set to "H" so as to perform the first horizontal transfer at time t6 after a predetermined time counted by the internal reference clock SDRCLK. In addition, reset signal φ
R is set to “H”, φH2 is set to “L” at time t7, and φR is set to “L” at time t8.

After a lapse of a predetermined time from time t6, φH2 is returned to “H” at time t9, φH1 is returned to “L” at time t10, and the first horizontal transfer is completed at time t11, but the second horizontal transfer is continued. Move on to horizontal transfer operation. Then, at time t12, the second horizontal transfer is completed. Similarly, set this to N
Repeated times, the transfer of one horizontal line is completed at time t13. Further, when φV = “H” is input at time t14, this is detected, and at time t15, the same operation as from time t1 to time t13 when φV1 is set to “H” is repeated. By repeating the operation from the time t1 to the time t13 L times, the read drive for one screen is completed.

Even in this driving mode, the SDR counting function does not accept the input of φV = “H” while driving for one line consisting of N times. Further, even if an input consisting of φH = “H” is made during one series of horizontal transfer driving, this is not accepted. Therefore,
The read drive of the sensor device SNS in this mode is
Reading in one horizontal direction consisting of N pixels can be performed regardless of the computer PRS.

FIG. 5 shows one horizontal transfer operation in the driving which is started after receiving the data SO from the computer PRS which is selected as the mode 3 in Table 3 in the sensor driving circuit SDR. First, at a time t1 of a predetermined time counted by the internal reference clock SDRCLK from the reception of the data SO from the computer PRS,
In order to perform the vertical transfer of the sensor device SNS, first, the vertical transfer clock φV1 is set to “H” and φV2 is set to “L” at the time t.

Then, at time t3 after a predetermined time, φV2
Is returned to “H”, and φV1 is returned to “L” at time t4. This completes one vertical transfer. Then, at time t5 after a predetermined time counted by the internal reference clock SDRCLK, the horizontal transfer clock φH1 is set to “H” and the reset signal φR is set to “H” in order to perform the first horizontal transfer. Further, φH2 is set to “L” at time t6, and φR is set to “L” at time t7. At time t8, which is a predetermined time after the time t5, φH2 is set to “H”, and at time t9, φH1 is returned to “L”, and the first horizontal transfer is completed at time t10, but the second horizontal transfer is continued. Move to transfer operation. Then, at time t11, the second horizontal transfer is completed.

Similarly, this is repeated N times at time t.
At 12, the transfer for one horizontal line is completed. Further, when φV1 is set to “H” at time t13 after the lapse of a predetermined time,
The same operation is repeated until time t12. By repeating the operation from the time t1 to the time t12 L times, the read drive for one screen is completed. In this drive mode, even if an input of φV = “H” or φH = “H” is made, it is not accepted. Then, the reading drive of the sensor device SNS in this mode is performed in the two-dimensionally arranged photoelectric conversion element composed of vertical K pixels and horizontal N pixels, after receiving data from the computer PRS, regardless of the computer PRS. be able to.

FIG. 6 shows the timing of outputting the storage signals φSTR and φSH in the sensor drive circuit SDR. First, at time t1, the storage signal SCON = “H” from the computer PRS is input. Then, at the time t2, this is detected, and φSTR is set to “L” in order to start the accumulation of the sensor device SNS.

After that, when the accumulation signal SCON becomes "L" at time t3 and the end of accumulation is sent, this is detected at time t4, and φSH is set to "H", and the sensor device SNS. The accumulated signal is transferred to the vertical transfer register. At time t5, φSH is returned to “L” to complete the transfer. Further, at time t6, φSTR is set to “H” to end the accumulation. Therefore, even during storage, control can be performed from the computer PRS only by the signal SCON, and the load on the computer PRS is reduced.

That is, in the photoelectric conversion device of this embodiment,
By communicating with the computer PRS and selecting the driving method of mode 3 described above by the data signal SO, the unnecessary photoelectric conversion element output of the sensor device SNS is swept out to the synchronizing signals φV and φH from the computer PRS. No matter what, it is stored in the EEPROM during that time,
Parameters necessary for a series of AF processing are stored in a predetermined address on the RAM to prepare for AF processing.

8 to 10 show specific operation block diagrams. 8 is a specific operation block diagram of the device of the present invention in the camera shown in FIG. 7, FIG. 9 is a block diagram showing operations other than FIG. 8, and FIG. 10 is an operation block diagram in the conventional technique. In the example of FIG. 8, the computer P
Unnecessary output is swept out during the period in which the RS is transferring parameters, and thereafter, it is accumulated during communication.

In the example of FIG. 9, the computer PRS is used.
The unnecessary output is swept out and the storage is controlled regardless of the operation. On the other hand, in the conventional technique shown in FIG. 10, even if the unnecessary output is swept out, it is performed based on the read synchronization signal from the computer PRS. Therefore, since the computer PRS cannot perform other processing while sweeping out unnecessary outputs, there is a limit in reducing the time required for a series of operations, but the present invention causes such an inconvenience. Can be solved satisfactorily.

Next, a second embodiment of the present invention will be described in detail with reference to FIGS. In the above-described first embodiment, the time required for read driving is the same even for unnecessary signals, and the main control unit can perform other processing during that time, which results in a series of processing times. Was only able to shorten. By the way, the factor that governs the read time is the A / D conversion device for converting the output of the photoelectric conversion element into a digital value taken in by the main control device.

However, if the unnecessary pixel outputs that do not require A / D conversion are driven in the same time as when A / D conversion is performed, in order to increase the functions of the main controller and increase the number of pixels of the photoelectric conversion element, for example, Not only the time required for the processing using the information from the photoelectric conversion element output for focus detection, but also the function deterioration in the entire system using those storage control devices. The second embodiment solves such an inconvenience.

First, the situation in which the sensor drive circuit SDR in the second embodiment is operating will be described with reference to FIG. In FIG. 11, communication with the computer PRS is performed at time t1, and the driving method of the above-mentioned mode 3 is selected by the data signal SO. Then, from time t2, unnecessary photoelectric conversion element output of the sensor device SNS is swept out. This unnecessary sweeping of the photoelectric conversion element output is performed regardless of the synchronization signals φV and φH from the computer PRS.

The computer PRS has the EEPR in the meantime.
The parameters required for the series of AF processes stored in the OM are stored in a predetermined address on the RAM to prepare for the AF process, and this is finished at time t3. When the unnecessary output is read at time t4, the sensor drive circuit SDR continuously starts accumulation. On the other hand, the computer PRS communicates the signal output in the mode 3 shown in Table 3 during this period, and terminates this at time t5. Time t
At the same time when the accumulation is completed in 6, read signals φV and φH
The sensor drive circuit SDR starts
V1, φV2, φH1, and φH2 are output to read the signal output. Then, the reading is completed at time t7.

Next, referring to FIG. 11, the sensor drive circuit SD
The signal given by R to the sensor device SNS will be described with reference to the timing chart of FIG. In FIG. 12, the mode 2 in Table 3 is selected in the sensor drive circuit SDR,
It shows one horizontal transfer operation in the drive started after receiving the data SO from the computer PRS.

First, the data signal SO from the computer PRS is received. Then, the internal reference clock SDRC
At a predetermined time t1 counted by LK, the sensor device S
To perform NS vertical transfer, first, the vertical transfer clock φ
V1 is set to “H”, and φV2 is set to “L” at time t2. Then, after a lapse of a predetermined time, φV2 is returned to “H” at time t3, and φV1 is returned to “L” at time t4.

This completes one vertical transfer. Then, at time t5 after a predetermined time counted by the internal reference clock SDRCLK, the horizontal transfer clock φH1 is set to “H” to perform the first horizontal transfer, and the reset signal φ
R is set to “H”, and φH2 is set to “L” at time t6. At time t7, which is a predetermined time after time t5, φH2 is set to “H” and φR is set to “L”, and at time t8, φH1 is returned to “L”, and the first horizontal transfer is completed at time t9. The second horizontal transfer operation.

Similarly, this is repeated N times at time t.
At 10, the transfer for one horizontal line is completed. Further, when φV1 is set to “H” at time t11 after the lapse of a predetermined time,
The same operation from time t1 to time t10 is repeated.
In this way, by repeating the operation from time t1 to time t11 L times, the read operation for one screen is completed.

Even in this driving mode, the SDR counting function does not accept the input of φV = “H” while driving for one line consisting of N times. Further, even if an input consisting of φH = “H” is made during one series of horizontal transfer driving, this is not accepted. Therefore, the reading drive of the sensor device SNS in this mode can perform reading in one horizontal direction consisting of N pixels irrespective of the computer PRS.

Next, another embodiment will be described with reference to FIG. In this embodiment, the driving mode 2 shown in Table 3 is performed in units of horizontal 1 line. The vertical transfer clocks φV1 and φV2 are output each time the signal φV derived from the computer PRS is detected, and the horizontal transfer clocks φH1 and φH2 are output in accordance with the operation reference clock of the sensor drive circuit SDR, so that the horizontal 1 You can have line units.

In FIG. 13, first, at time t1, the signal φV from the computer PRS becomes "H". The sensor drive circuit SDR uses the internal reference clock SDRCLK,
This is detected at time t2, and the sensor device SN is detected.
In order to perform the vertical transfer of S, first, the vertical transfer clock φV
1 is set to "H", and the vertical transfer clock φV2 is set at time t3.
To "L".

Then, at the time t4 after the lapse of a predetermined time, the vertical transfer clock φV2 is returned to "H", and the time t4
At 5, the vertical transfer clock φV1 is returned to "L". This completes one vertical transfer. Then, in order to perform the first horizontal transfer at time t6 after the lapse of a predetermined time counted by the internal reference clock SDRCLK, the horizontal transfer clock φH1 is set to “H” and the reset signal φR is set to “H”,
At time t7, φH2 is set to “L”.

At a time t8 after a predetermined time has elapsed from the time t6, the horizontal transfer clock φH2 is set to "H" and φR is set to "L". Then, at time t9, the horizontal transfer clock φH1 is returned to "L", and at time t10, the first horizontal transfer is completed, but subsequently the second horizontal transfer operation is resumed.

Similarly, this is repeated N times at time t.
At 11, the transfer for one horizontal line is completed. Furthermore, when φV = “H” is input at time t12, when this is detected and φV1 is set to “H” at time t13, the same operation as from time t1 to time t11 is repeated. in this way,
By repeating the operation from the time t1 to the time t11 L times, the read operation for one screen is completed. Therefore,
Also in the case of the read drive of the sensor drive circuit SDR in this drive mode, the read in one horizontal direction consisting of N pixels can be performed regardless of the operation of the computer PRS.

[0079]

As described above, the present invention provides the first means for driving the photoelectric conversion region on the basis of the drive synchronization signal from the main controller when the photoelectric conversion region is controlled by the photoelectric conversion device. Since the second means for driving the photoelectric conversion region based on the signal generated in the photoelectric conversion device without being synchronized with the drive synchronization signal from the main control device is provided, the main control device is Processing other than the control can be performed during the readout period of the photoelectric conversion region, and the time required for a series of operations can be shortened. This is very effective in the recent increase in the number of pixels, and the load on the main controller can be minimized. Therefore, not only can the time required for the operation of the processing system using the information from the photoelectric conversion area output for focus detection to be shortened, but the function of the entire system can be improved. Further, the read time of the output of the photoelectric conversion region can be significantly shortened, which makes it possible to further improve the function of the entire system.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a photoelectric conversion device of the present invention.

FIG. 2 is an optical system and electrical block diagram showing a specific configuration when a device for realizing the device shown in FIG. 1 is incorporated in a camera.

FIG. 3 is a diagram showing an operation timing of the device of the present invention.

FIG. 4 is a diagram showing an operation timing of the device of the present invention.

FIG. 5 is a diagram showing an operation timing of the device of the present invention.

FIG. 6 is a diagram showing an operation timing of the device of the present invention.

FIG. 7 is a block diagram showing an interline type area sensor.

FIG. 8 is a block diagram for explaining a specific operation when applied to a camera.

FIG. 9 is a block diagram for explaining another example of a specific operation when applied to a camera.

FIG. 10 is a specific operation block diagram of a camera according to the related art.

FIG. 11 is a block diagram for explaining a specific operation when applied to the camera of the second embodiment.

FIG. 12 is a diagram showing operation timing of the second embodiment.

FIG. 13 is a diagram showing operation timing of the second embodiment.

[Explanation of symbols]

PRS computer SNS sensor device SDR sensor drive circuit LPRS control circuit SPC photometric sensor

Claims (4)

(57) [Claims] 1. A photoelectric conversion region having a plurality of photoelectric conversion units for accumulating charges photoelectrically converted according to an incident light beam, and controlling the drive of the photoelectric conversion region by communicating a signal with a main controller. Which is a photoelectric conversion device, which is based on a drive synchronization signal sent from the main control device,
A drive synchronization signal sent from the main controller based on a first means for generating a first drive signal for driving the photoelectric conversion region and a second signal generated in the photoelectric conversion device. And a driving means having a second means for generating a second driving signal for driving the photoelectric conversion region asynchronously with, and the first means is set to drive. ,
Setting is made such that the first means is controlled to drive the photoelectric conversion region in synchronization with the drive synchronization signal based on the drive synchronization signal sent from the main control device, and the second means is driven. If
The photoelectric conversion region is controlled so as to drive the photoelectric conversion region based on the second drive signal generated by the second means without being synchronized with the drive synchronization signal sent from the main control device. apparatus. 2. The photoelectric conversion device according to claim 1, wherein when the second means is set to be driven, an unnecessary signal is swept out from the photoelectric conversion region. 3. A photoelectric conversion region having a plurality of photoelectric conversion units for accumulating charges photoelectrically converted according to an incident light flux, and controlling the drive of the photoelectric conversion region by communicating a signal with a main controller. Which is a photoelectric conversion device, which is based on a drive synchronization signal sent from the main control device,
Based on the first means for generating a first drive signal for driving the photoelectric conversion region and the second signal generated in the photoelectric conversion device, the drive synchronization signal is asynchronous with the drive synchronization signal. A drive means having a second means for generating a second drive signal for driving the conversion region, wherein the first means is set to drive,
Based on the drive synchronization signal from the main controller, the first
When the means is set to drive the photoelectric conversion region in synchronization with the drive synchronization signal and the second means is set to drive,
Without synchronizing to the drive synchronization signal from the main controller,
The photoelectric conversion area is controlled to be driven based on the second drive signal generated by the second means, and the drive mode is changed based on the information input from the main control unit. A photoelectric conversion device characterized in that the driving speed is changed according to the change. 4. The photoelectric conversion device according to claim 3, wherein an unnecessary signal is swept out from the photoelectric conversion region when the second means is set to be driven.