JP3441086B2 - Clock Recovery Method for Wireless Local Area Network Station - Google Patents

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION The present invention relates to local area networks (LANs).

[0002]

2. Description of the Related Art A local area network (LAN) in which a plurality of network stations are interconnected by a cable is widely used. However, wired LANs have the drawback of requiring a large amount of cables to interconnect the stations. Providing such a cable is generally inconvenient and inflexible when trying to change the physical location of a station. Therefore, it has been proposed to use a wireless radio link for a LAN. However, there are some problems with using radio communication links. LAN used especially in indoor environment
Has this problem. One of the problems is multipath attenuation. This is mitigated by spread spectrum communication technology. Another problem that arises with wireless LANs is the problem of providing an accurate receiver clock suitable for timing the received data as the wireless LAN experiences various disturbing effects. For example, when a plurality of wireless LANs are provided in close proximity to each other, a signal transmitted in one wireless LAN may be received in another wireless LAN, which causes timing problems at the station. .

[0003]

SUMMARY OF THE INVENTION It is an object of the present invention to provide a local area network station suitable for a wireless LAN, which station can provide a recovered clock signal in which interference effects are minimized. .

[0004]

SUMMARY OF THE INVENTION The present invention therefore provides a digital representation of a received signal at a local area network station which receives a data symbol transmitted on a radio channel encoded in a spread spectrum code. Analog / digital converter of
A correlator device coupled to the analog / digital converter for providing a plurality of signal samples, an integrator / storing device including a plurality of storage registers for storing integrated values of the plurality of signal samples, and in the storage register There is provided a local area network station, characterized in that it comprises a peak determining device for determining the maximum value stored in the device and a clock generating device for providing a recovered clock signal at a time corresponding to the sample giving the maximum value.

The invention also provides a method of recovering a clock signal from data symbols transmitted on a radio channel by encoding into a spread spectrum code, the method comprising the steps of: (a) converting the received signal into a digital representation. When,
(B) correlating the digital representation to give a plurality of signal samples; (c) integrating the signal samples; (d) determining a maximum value of the integrated value;
(E) providing a recovered clock signal at a time corresponding to the sample providing the maximum value.

Another advantage of the present invention is that it switches from one source antenna to another as the mobile station moves in an environment where more than one antenna is transmitting the same information. This is the case.

Preferred embodiments of the present invention will be described below with reference to the accompanying drawings.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT Referring initially to FIG. 1, there is shown a local area network (radio LAN) 10 including a plurality of stations 12 individually designated 12-1 to 12-N. Each station has an antenna 14, designated 14-1 through 14-N, respectively. Although not shown in FIG. 1, it should be understood that a distribution system (relay unit) having two or more antennas may be provided to increase the effective area of the radio LAN 10.

Communication between stations 12 is carried over a single radio channel and uses spread spectrum communication technology (spread).
spectrum communication technology). In the indoor radio LAN of the preferred embodiment, 902-928
The MHz band is used. Another suitable frequency band is 2.
It is around 5 MHz. In the preferred embodiment, the information is 11
Transmitted using the chip's spread spectrum code. This code consists of 2 bits per symbol quadrature modulation and 4 phase different phase shift keying code system.
ial phase shift keying coding). However, it is also possible to use a number of different chips and other modulation types.

Referring to FIG. 2, the data and clock recovery circuit 20 included in each station 12 is shown. The signal received by the antenna 14 is sent to the bandpass filter 22. The outputs are mixers 24 and 26.
Applied to. The mixer 26 has a local oscillator 2
8 is directly coupled and further coupled to the mixer 24 via the 90 degree phase shifter 30. Mixers 24 and 26 provide in-phase, quadrature signal components. These are I
Corresponds to plane and Q plane signals.

The outputs of the mixers 24 and 26 are applied to analog / digital converters 32 and 34, respectively. The analog to digital converters 32, 34 are also provided with the sample clock pulse on the sample clock line 37 generated by the sample clock generator circuit 36. The sample clock generator circuit 36 generates a clock signal at twice the spread spectrum chip rate. In the preferred embodiment, this sample clock generator circuit 36 operates at 22 MHz. Therefore, for the 11 chip code used in the preferred embodiment, for each data symbol the sample clock generator circuit 36
A sample clock pulse is generated. However, other sample speeds are possible, for example the speed of the tip may be left unchanged,
It may be a multiple other than double.

The outputs of the analog / digital converters 32, 34 are applied to the respective digital correlators 42, 44 via 4-bit lines 38, 40. These digital correlators 42,44 provide digital output signals on their respective 6-bit lines 46,48. These digital correlators 42, 4
4 is applied to the IQ / polar coordinate converter 50 composed of a reading table. It should be understood that the short diagonal lines across some signal lines in the figure are the number of conductors in the signal line. IQ
The / polar coordinate converter 50 converts the phase / quadrature signal representation IQ into an amplitude / phase representation Z, 0 of the correlated signal vector and provides it on lines 52,54, respectively.

Line 52 is connected to symbol clock recovery circuit 60. The symbol clock recovery circuit 60 provides the recovered symbol clock signal (RXCLK) on the output line 62. Line 54 is connected to shift register 64 and the summing input of adder 66. Shift register 64 is line 6
A 22 sample delay is provided under the control of the sample clock applied to the shift register 64 via 8. The output of shift register 64 is coupled to the subtract input of adder 66 via 8-bit l line 70. Adder 66 provides a one symbol time delay between its input and its output.

Phase compensation circuit 72 has an output connected to the subtract input of adder 66 via 8-bit line 74. The input end of the phase compensation circuit 72 is connected to the addition output end of the adder 66 via the feedback line 75. The phase compensation circuit 72 is adjusted during the preamble of the received data frame. The phase compensation circuit 72 includes a register that stores an adjusted compensation value for correcting the phase of the received signal. Therefore, adder 66 provides a value on the 8-bit output line 76 which represents the compensated difference between the current phase sample and the phase sample delayed by one symbol (ie, the absolute phase sample). This is because the differential phase encoding is performed as described above. Line 76
Is connected to the sample selector circuit 78. Sample selector circuit 7
8 is applied the RXCLK signal on line 62. Therefore, when the clock signal RXCLK is active, one of the 22 phase signal values is selected. When the phase signal value thus selected is applied to the decision circuit 80, the output data signal R is output on the line 81 according to the quadrature modulation adopted in this example.
Give DATA.

Referring now to FIG. 3, a block diagram of the symbol clock recovery circuit 60 (FIG. 2) is shown. The 5-bit input lines 52 are 90-1 to 90-22, respectively.
22 integration-register circuit modules 9
0 connected in parallel. Since these integration-register circuit modules 90 have the same configuration, only the circuit 90-1 will be described. Input line 9 connected to line 52
2 is connected to the addition input terminal of the adder 94. Register 9
6 stores the value Z ₁ in the circuit module 90-1, whose 10-bit output line 98 is further coupled to the adder input of the adder 94. Line 98 is also coupled to the input of multiplier 102. The multiplier 102 receives the input value 104, which is given a constant value 1/32. The output of multiplier 102 is coupled to the subtract input of adder 94. The 10-bit output line 106 of the adder 94 is the feedback line 10
8 to the input of register 96. Register 96 is enabled by the signal on line 109. The adder 94, the multiplier 102 and related circuits collectively represent a leaky integrator circuit 110.
cuit).

Sample clock input line 37 (FIG. 3) is line 12
It is connected via 0 to the free running sample counter 122.
This sample counter 122 iteratively counts the values 0 to 21 and outputs the current number of samples (0-21) on the output line 124.
And a further output signal on line 126 when the count goes from 21 to 0.
The sample clock input line 37 is also connected via line 128 to line 1
Connected via 32 to a demultiplexer 130 which receives the sample output count on line 124. Demultiplexer 1
It should be understood that 30 provides the enable signals in sequence to the registers 96 of the circuit modules 90-1 to 90-22. This enable signal is given via the line 109 to the register 9 of the first circuit module 90-1.
An enable signal to 6 is included.

The 10-bit output line 106 (FIG. 3) of the adder 94 is connected to one input terminal of the 22-input type multiplexer 140. The multiplexer 140 also receives the respective inputs from the other circuit modules 90-2 to 90-22. The multiplexer 140 has a 5-bit selection input line 142
, Which is connected to the output line 124. The multiplexer 140 also has a 10-bit output line 144 connected to the bit removal circuit 146. Bit deletion circuit 1
46 deletes the two least significant bits and outputs an 8-bit output to line 1
Give to 48. This output line 148 is the peak value register 1
50 and one input end of the comparator 52. The 8-bit output line 154 of the register 150 is connected to the second input terminal of the comparator 152. The output of comparator 152 is connected via line 156 to a set of inputs of register 150. The reset input of register 150 is connected to line 126.

The output line 156 (FIG. 3) of the comparator 152 is also connected to a set of inputs of the peak sample count register 160. The register 160 has an input connected to the count output line 124 of the sample counter 122 via line 162. The 5-bit output line 164 represents the number of samples of the peak value in the symbol, which is the symbol clock generator circuit 16
Is combined with 6. Another input of the symbol clock generator circuit 166 is connected to the sample count output line 124 via a 5-bit line 168. Symbol clock generator circuit 16
6 is the output symbol clock pulse RXCL on line 62 at a time corresponding to the number of samples stored in register 160.
This is a logic circuit that generates K.

The symbol clock recovery circuit 60 (FIG. 3) operates as follows. For each sample applied via the 5-bit input line 52, the value calculated by the leakage integration circuit 110 is stored in the corresponding register 96 of the circuit module 90. This value is a value obtained by dividing 1/32 of the previous value from the sum of the previously stored value and the newly applied value. Therefore, each sample position within a symbol is integrated separately from the corresponding previous sample position. As a result, 22
The contents of register 96 represent these integrated values. The peak value (maximum value) of these values is confirmed by the register 150 and the comparator 152 as follows. Register 150
Is cleared (reset) via line 126 when the sample counter 122 returns from a count of 21 to a count of 0. The comparator 152 sequentially compares the contents of the multiplexer 140. Whenever the latter value of the comparison is higher than the former value, comparator 152 provides an output signal on line 156 to cause register 150 to store the multiplexer output value (but with the two least significant bits removed). . This signal on line 156 also causes register 160 to store the corresponding peak sample number (sample number). Therefore, at the end of one complete cycle of the sample counter 122 corresponding to one symbol period, the peak sample number register 160 contains the sample number giving the highest value of 22 samples. This value is applied to the symbol clock generator circuit 166 to provide the symbol clock signal RXCLK on line 62 at the time corresponding to the maximum sampled value.

In the modified design example of the symbol clock recovery circuit shown in FIG.
Instead of the two integrator circuit 110, a single leaky integrator circuit can be used. This can be accomplished by using a cycling RAM or a delay line with 22 single sample delays connected in series and coupling a single leaky integrator circuit to the RAM or delay line. In this design modification, multiplexer 140 and demultiplexer 130 are of course not needed and therefore can be omitted from the circuit.

The circuit described above allows desired peak identification within a very short time, for example within about 4 symbol times. Another advantage is that the effect of noise can be minimized and thus high stability can be achieved.

The radio LAN of FIG. 1 does not operate on an ideal radio channel, and multipath characteristics are involved. This is particularly characteristic for indoor use. Therefore, the signal received at antenna 14 is the sum of the analog signals that have traveled along paths of varying lengths. Some paths cancel out, but other path signals are superimposed, resulting in amplitude enhancement. This is a phenomenon known as "multipath".

Referring to FIGS. 4A-4D, time intervals T0 to T1, T1 to T2, and T2 to T.
A typical correlator output amplitude signal is shown after performing an amplitude / phase representation z, 0 for three consecutive symbol periods of three. FIG. 4 (a) shows the three correlator output signals 200, 202, and 204 that would be produced when the multipath effect was minimal in the radio channel. Figure 4
(B) is a radio channel with a strong multipath effect, but with three correlator output signals 206, 208, and 21 that appear to occur when there is visibility between the transmitter and receiver.
Indicates 0. FIG. 4 (c) shows three correlator output signals that are likely to occur when the view between the transmitter and the receiver is obstructed with moderate multipath effects on the radio channel. . The signals in each of FIGS. 4A, 4B, and 4C occur at the sampling time represented by the vertical dashed line. These sampling times are the same as the symbol clock signal RXCL as described above.
Suitable for giving K.

Referring to FIG. 4 (d), there is shown the correlator output signal that would be obtained if the signals were received from two transmitters. Signals 218, 220, and 2
22 is derived from the first transmitter and has signals 224, 226,
And 228 are derived from the second transmitter. The clock recovery circuit described with reference to FIGS. 2 and 3 provides the symbol clock signal R recovered at the times represented by the vertical dashed lines for the signals 218, 220 and 222 from the first transmitter.
Give XCLK. Therefore, the data from the first transmitter is recovered and the data from the second transmitter is ignored. This is an advantage over clock recovery methods that use phase locked loops. Because the phase locked loop method uses signal 218
And 224 tend to be synchronized to an intermediate point in time between peaks, since there is no information-bearing signal at this intermediate point. Thus, the clock recovery circuit described above continues to be synchronized with the more strongly received signal, even if a slightly weaker signal is received shortly after the strong signal. Therefore, an obstructive L located near the LAN 10 in FIG.
The signal transmitted from the AN is reduced when received.

Another advantage of the clock recovery circuit described above is that the mobile station 12 is always synchronized to the most strongly detected signal, so that even when the transmission from the designated antenna is lost due to temporary blockage of the transmission path. In a LAN with a distribution system in which multiple transmit antennas are used, the mobile station can always be kept in sync with the transmissions of the other antennas. Further, the clock recovery circuit can continue to be synchronized with the signal even when the channel characteristics are not constant due to a moving obstacle entering the transmission path.

Although the case where the transmission in the radio frequency band, that is, the band of 10 KHz to 3000 GHz is used is described as the preferred embodiment, the infrared frequency of 3000 is used.
It should be appreciated that frequencies above GH can also be employed.

[Brief description of drawings]

FIG. 1 is a diagram showing a radio LAN.

FIG. 2 is a block diagram of a portion of a receiver included in a LAN station.

FIG. 3 is a block diagram of a clock recovery circuit included in the circuit shown in FIG.

FIG. 4 is a waveform diagram of a correlator output signal useful for understanding the operation of the present invention.

[Explanation of symbols]

10 Local Area Network 12-1 to 12-N Network Station 14 antenna 20 receiver circuit

Continuation of the front page (56) Reference JP-A-2-14635 (JP, A) JP-A-53-46062 (JP, A) JP-A-56-35531 (JP, A) British Patent Application Publication 2203303 (GB, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) H04L 12/28 H04J 13/00 H04L 27/22

Claims (2)

(57) [Claims] 1. A local area network station for receiving data symbols encoded in a spread spectrum code and transmitted over a wireless channel, the analog to digital conversion means for providing a digital representation of the received signal. A correlator means coupled to the analog / digital converting means for providing a plurality of signal samples; and an integrator / storage register means including a plurality of storage registers for storing integrated values of the plurality of signal samples. A local area network station comprising peak determining means for determining a maximum value stored in the storage register and clock generating means for providing a recovered clock signal at a time corresponding to the sample giving the maximum value. 2. A method of recovering a clock signal from data symbols encoded in a spread spectrum code and transmitted over a wireless channel, the method comprising: (a) converting the received signal into a digital representation. , (B) providing a plurality of signal samples by correlating the digital representation, (c) integrating the signal samples, (d) determining a maximum value of the integrated value, e) providing a recovered clock signal at a time corresponding to the sample providing the maximum value.