JP3439177B2 - How to calculate yield loss - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for obtaining a yield loss due to a symbol, and more particularly to a method for more accurately obtaining a loss caused by a symbol with respect to a yield of a semiconductor chip.

[0002]

2. Description of the Related Art Yield is one of the important indexes for factories that carry out mass production. While yield represents the manufacturing technology of a factory, it also reflects the cost required to produce a product. Among other things, for manufacturers of semiconductor chips, yield is directly related to their overall profits. Therefore, how to improve the yield is an important issue in mass production.

Each chip on a semiconductor wafer is divided into a normal chip and a failure chip after undergoing a product test. Yield is determined by this. FIG. 1 is a diagram showing chips arranged on a semiconductor wafer and the quality of these chips.
As shown in FIG. 1, the chips are arranged in rows on the semiconductor wafer 10. Each dark chip 12 represents one failed chip and each white chip 14 represents one normal chip.

Failed chips on semiconductor wafers are sometimes
Create some special patterns. Moreover,
The designs often appear on different semiconductor wafers. These designs are called signatures. For example, as shown in FIG. 1, a Swedish-like pattern is formed in the central region of the wafer, and there are edge effects and misalignment in the peripheral region of the wafer. The repeated appearance of a single sign indicates that one or several processes are in an abnormal state throughout the manufacturing process, and that the yield is constantly decreasing due to the sign. .

The total yield loss that different symbols have caused to yield within a certain observation time must be identified. That way, priorities for correction adjustments in the production process can be provided. For example, if the total yield loss caused by the Swedish symbol in a month is greater than the total yield loss caused by the other symbols, the manufacturing process associated with the Swedish symbol should be prioritized and adjusted. As a result, yield and profitability improvements can be obtained more quickly.

Conventionally, the method for calculating the yield loss by one symbol consists of the following steps.

Step 1: Provide a yield table for all relevant wafers. Each yield table shows one wafer and information whether the wafer is symbol sensitive. For example, when there are two types of symbols (S1 and S2) and five wafers (W1 to W5), all possible yields are shown in Table 1.

[0008]

[Table 1] The symbol V in Table 1 indicates that the corresponding wafer is symbol S1 or symbol.
It shows that it was affected by S2.

Step 2: The regression method is used to find the yield loss that occurs when the symbol appears once. When referring to Table 1, the regression equation is the following equation (1). Y _average −I _S1 × S1−I _S2 × S2 = Y _real (1) Among them, the unknowns are Y _average , I _S1 , and I _S2 . table
The information about wafer W1 shown in 1 is (S1, S2, Y _real ).
= (0,0,95%), and the information about wafer W2 shown in Table 1 can provide (S1, S2, Y _real ) = (1,0,92%). By obtaining five equations with three unknowns, S1 and S2 are independent variables, and Y _real is a dependent variable (d
ependentvariable) and the closest plane equation is obtained. As shown in FIG. 2, the distribution areas D ₀ , D ₁ , D ₂ and D
₁₂ are (S1, S2) = (0, 0), (1, 0),
The chip yield distributions at (0, 1) and (1, 1) are shown.
On the other hand, the plane P is the distribution area obtained by the regression method.
The plane closest to D ₀ , D ₁ , D ₂ and D ₁₂ is shown. Estimating from Table 1, (Y _average , I _S1 , I _S2 ) = (96%, 4%, 7
%) Is obtained. As shown in the right part of FIG. 2, I _S1 and I _S2 indicate the yield loss of a single wafer caused by the single appearance of S1 and S2, respectively.

Step 3: Determine the total yield loss affected by each symbol based on the probability that the symbol appears. Table 1
For example, the total yield loss caused by the symbol S1 is I _s1 × _2/5 = 1.6% due to the symbol S1 appearing on two of the five wafers. Similarly,
The total yield loss caused by the symbol S2 is I _s2 × _2/5 = 2.8
%. With this, the total yield loss caused by each symbol can be known.

[0011]

However, due to the statistical uncertainty, when two or more symbols appear on the same wafer, for example, wafer W4 shown in Table 1, the conventional method is used. Cannot distinguish the effect that individual symbols have on the wafer. As a result, the total yield loss induced by such materials naturally has a relatively large uncertainty.

On the other hand, if only one symbol can be identified from the test result of one wafer and the yield of this wafer is considerably lower than the yield of a general wafer having only one symbol, this It is shown that the wafer, other than its identified symbol, also caused other unknown factors to yield loss. However, according to conventional methods, this wafer yield loss is attributed to the total yield loss introduced by the symbol. As a result, the total yield loss caused by the symbol, which was finally calculated, is inaccurate.

In view of the above-mentioned problems, the main object of the present invention is to provide a method for more accurately obtaining the total yield loss introduced in a symbol by clarifying the relationship between the yield loss and the symbol. To do.

[0014]

SUMMARY OF THE INVENTION To achieve the above object, the method of obtaining total yield loss provided by the present invention comprises a chip array on a treated wafer surface to define a plurality of adjacent regions. And yielding a yield table for multiple wafers, each yield table having a plurality of area yields for a corresponding area of an associated wafer, and indicating whether the associated wafer was affected by the symbol. A symbol column, providing at least one region that can be affected by the symbol, and using a linear regression method, based on the yield tables, at least one effect when the symbol appears once. By calculating the area yield loss of the affected area and summing the yield loss based on the ratio of the affected area to the chip array. Calculating the single sheet yield loss that results for a single wafer when appearing once Eha, wafers affected by the single sheets yield loss and said symbol is based on the percentage of the plurality of wafers,
It is characterized by having each step of estimating the total yield loss.

In order to achieve the above-mentioned object, the method for obtaining the total yield loss provided by the present invention provides a multiple yield table of a plurality of wafers, and each yield table has a test with an associated wafer. At least one test condition that can be influenced by the symbol, having a plurality of characteristic yields under the condition, and having a symbol column that indicates whether the related wafer is influenced by the symbol. Then, using a linear regression method, based on the plurality of yield tables, calculate the characteristic yield loss of at least one affected test condition when the symbol appears once, and sum the characteristic yield loss. By calculating the single-wafer yield loss, the total yield is calculated based on the single-wafer yield loss and the ratio of the wafers affected by the previous term to the plurality of wafers. And having each step of determining the loss.

In order to achieve the above-mentioned object, the method for obtaining the total yield loss provided by the present invention is to dice a chip array on a processed wafer surface to define a plurality of adjacent regions, Providing multiple yield tables for multiple wafers, each yield table having multiple regional bin yields under certain test conditions with one corresponding region of the associated wafer; and And a symbol column indicating whether the related wafer is affected by a symbol, providing at least one region and a test condition that can be influenced by the symbol, and using a linear regression method to the yield tables. Calculating the area characteristic yield loss caused by the affected test condition for at least one affected area when the symbol appears once, and Accordance percentage area occupied on the chip sequence, by summing the area characteristic yield loss, when the symbol appears once
Calculate the single-yield loss brought to one wafer, based on the ratio of the single-yield loss and wafers affected by the previous term symbol to the plurality of wafers, each step to obtain the total yield loss It is characterized by having.

The object of the present invention to achieve the above object,
In order to make the symbols and advantages clearer, detailed description will be given below with reference to the drawings and embodiments.

[0018]

BEST MODE FOR CARRYING OUT THE INVENTION The gist of the present invention is to classify wafer yields into a plurality of partial yields and define whether each symbol affects the partial yields. Therefore, when calculating the total yield loss by one symbol by statistical calculation, it is possible to exclude the symbols that did not affect the partial yield loss,
The results obtained will be more accurate.

[0019]First embodiment Figure 3 shows a chip placed on the surface of a processed wafer.
It is a figure which shows the area | region after dicing the line of groups of a group. Figure
Each grid shown in 3 represents one chip. Finished processing
The surface of the wafer 20 has a plurality of regions from inside to outside.
Formed in a substantially annular shape, A, B, C, D, and E, respectively
It is named.

Then, a yield table for a plurality of wafers can be obtained from the data after the chip test. FIG. 4 shows a plurality of yield tables provided by the present invention. Figure 4
Shows a wafer yield table 21 (W1 to W21). The yield table of each wafer is the yield information 30.
And symbol information 32.

The yield information 30 has a plurality of regional bin yields. Each area characteristic yield is the yield obtained under the test conditions in which the corresponding area of the associated wafer is associated. The test conditions are so-called conditions for verifying whether or not a certain chip is a passing chip. These conditions may be, for example, a DC voltage / current condition, an AC voltage / current condition, a material writing capability, or the like. Further, FIG. 4 shows three different test conditions of T1, T2, and T3. YT1-A represents the yield of chips that passed the T1 test condition in the A region. YT2-A represents the yield of chips that have passed the T1 test condition and the T2 test condition in the A region. By this analogy.

The symbol information 32 has three symbol columns S1, S2, and S3. The entry of the symbol V in the S1 symbol column indicates that the wafer test result diagram (for example, the test result shown in FIG. 1) has the pattern of the symbol S1. In other words, the wafer was affected by the symbol S1. Therefore, wafer W1 is not affected by any symbols, but wafer W2 is affected by symbols S2 and S3. By this analogy.

Next, we define at least one region and test conditions that the symbol can affect.

Test experience shows that each symbol affects only some areas and is only washed out under certain test conditions. Therefore, it is possible to define at least one area and test conditions in which the symbol can influence. Table 2 shows one definition result according to the present invention.

[0025]

[Table 2] It can be seen from Table 2 that the symbol S1 appears only in the areas D and E and only under the test condition T1. This can be analogized.

Then, using the mathematical method of linear regression, based on these multiple yield tables, the area that the test condition yields for at least one affected area when the symbol appears once. Calculate the characteristic yield loss.

For example, the yield loss I _T1-D-S1 brought to the area D when the symbol S1 is the test condition T1 is obtained by the following equation (2) and linear regression. YT1-D _average -IT1-D _-S1 x S1 = YT1-D _real (2) From the 21 yield table shown in Fig. 21, 21 sets (S1, YT1-
D _real ) value can be obtained. And put it in equation (2),
In addition, the coefficients YT1-D _average and I
Values for _T1-D-S1 can be obtained. I _T1-D-S1 is the region characteristic yield loss that may occur under T1 test conditions in the D region when the symbol S1 appears once. In a similar manner, _IT1-E-S1 can be obtained.

It can be seen from Table 2 that the symbol S1 only affects the yield under the T1-D and T1-E conditions. Therefore, in addition to I _T1-D-S1 and I _T1-E-S1 , the region characteristic yield loss associated with other symbols S1, for example, I _T
T1-A-S1 , I _T2-D-S1 , and I _T3-E-S1 are all 0. With the same concept, the yield loss I
_{cont-region -sig} can be sought.

Then, in one wafer, the symbol S1
The yield loss of a single product caused by the occurrence of can be obtained by the following equation (3). I _0-S1 = (C _A I _T1-A-S1 + C _B I _T1-B-S1 + C _C I _T1-C-S1 + C _D I _T1-D-S1 + C _E I _T1-E-S1 + C _A I _T2-A-S1 + C _B I _T2-B-S1 + ……) / C _TOTAL (3) Of these, C _X is the number of chips in region X, and C _TOTAL is the total of one wafer. The number of chips. Equation (3) shows the sum of the proportions occupied by all the region characteristic yields regarding the symbol S1.

Finally, the total yield loss caused by the symbol S1 within a certain observation time can be calculated using the probabilities that I _{0 -S1} and S1 appear, as shown in the following equation (4). it can. I _impact-S1 = I _0-S1 × W _S1 / W _total (4) Of these, W _S1 indicates the number of wafers having the symbol S1, and W _total indicates the number of all wafers.

Similarly, the total yield loss introduced by the symbols S2 and S3 can be obtained by the method described above.

In this way, the total yield loss caused by all the symbols can be arranged in order. FIG. 5 shows the symbol S1,
It is a figure which compares the total yield loss which S2 and S3 brought. From FIG. 5, it can be seen that the total yield loss caused by the symbol S2 is the largest. Therefore, in order to improve the yield, the manufacturing process in which the symbol S2 is generated should be improved first.

[0033]Second embodiment According to the concept of classifying wafer yield, the present invention
Has another implementation method. How to do that,
It is to classify the yield results by area. First
Classification according to both area and test conditions of one embodiment
Method is different.

The second embodiment simply comprises the following steps.

Step 1: The array of chips arranged on the surface of the processed wafer is diced as shown in FIG.

Step 2: Provide multiple yield tables for multiple wafers. Each yield table has a plurality of regional yields and a plurality of symbol columns. The yield table shows the result of the yield of each wafer classified by area, and information on whether the yield of each wafer has a relation that can be influenced by a symbol.

Step 3: Provide the area where each symbol can affect.

Step 4: Using the linear regression method, determine the area yield loss caused for each individual area when each individual symbol appears once.

Step 5: Calculate the sum of all area yield losses caused by one symbol according to the ratio of each area to one wafer.

Step 6: Determine the total yield loss caused by the individual symbol according to the rate of occurrence of the individual symbol.

[0041]Third embodiment The present invention is based on the concept of classifying wafer yields.
Has yet another implementation method. That is, its implementation
The method is to classify yield results according to test conditions.
And. According to both the area of Example 1 and the test conditions
Different from classification.

The third embodiment simply comprises the following steps.

Step 1: Provide multiple yield tables for multiple wafers. Each yield table has a plurality of characteristic yields and a plurality of symbol columns. The yield table shows a result in which the yield of each wafer is classified by a test condition, and information on whether or not there is a relation that can be influenced by a symbol.

Step 2: Provide test conditions that each symbol can affect.

Step 3: Using a linear regression method, determine the area yield loss that can occur for each individual test condition when each individual symbol appears once.

Step 4: Sum all the characteristic yield losses caused by one symbol.

Step 5: Determine the total yield loss caused by the individual symbols according to the rate of appearance of the individual symbols.

In the yield table of the present invention, the yields are properly classified. The classification can be done by region, by test condition, or by both region and test condition. As a matter of course, the user may perform the classification under other conditions according to his or her preference. Since the yields are properly classified, the effect of each symbol on the yield of chips can be more clearly discerned. Therefore, the total yield loss due to each symbol can be calculated more accurately because the interference on the yield between symbols can be reduced.

The above-described preferred embodiments of the present invention are not intended to limit the present invention. Any person skilled in the art can make various changes and modifications within the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the claims.

[0050]

Since the present invention is as described above, it has the following effects.

Since the yield of the present invention can be classified by region, property, or both region and property conditions, the yield loss contributed by the region or property not affected by the symbol is eliminated when statistics are made. can do.
Therefore, the total yield loss based on the symbol can be calculated more accurately.

[Brief description of drawings]

FIG. 1 is a diagram showing the position and quality of chips arranged on a semiconductor wafer.

FIG. 2 is a diagram showing the closest plane obtained by induction.

FIG. 3 is a diagram showing a region after dicing a chip array arranged on the surface of a wafer which has been processed according to the present invention.

FIG. 4 shows a plurality of yield tables provided by the present invention.

FIG. 5 is a diagram comparing the total yield loss caused by the symbols S1, S2 and S3.

[Explanation of symbols]

10, 20 wafers 12 failed chips 14 Normal chip 30 Yield information 32 Symbol information

─────────────────────────────────────────────────── ─── Continuation of the front page (73) Patent holder 599116362 Mosel Viteric Incorporated Mosel Vitic Inc. Taiwan, Xinchu, Science-Based Industrial Park, Lee Shin Road, 19th (73) Patent holder 500269978 Infineon Technologies Ins. Incorporated Federal Republic of Germany, 81541 München, Sankt-Martin-Strasse 53 (72) Inventor Michael Retterbach, Taiwan, Xin-Tu, Science-Basd Industrial Park, Rein-Road 19 (56) Bibliography JP-A-9-27531 (JP, A) JP-A 2000-91178 (JP, A) JP-A 2001-15564 (JP, A) (58) Fields investigated (Int. Cl. ⁷⁾ , DB name) H01L 21/02 G01R 31/26 H01L 21/66

Claims (13)

(57) [Claims] 1. To define a plurality of adjacent regions,
Dicing the chip array on the processed wafer surface, providing a multiple yield table of multiple wafers, each yield table having a plurality of area yields of the corresponding region of the related wafer, and said related wafer A symbol column showing whether or not the symbol is affected, providing at least one region that can be affected by the symbol, and using the linear regression method, the symbol appears once based on the plurality of yield tables. When calculating the area yield loss of at least one affected area, when the affected area totals the yield loss based on the percentage occupied by the chip array, the symbol is once on the wafer. When the wafer appears, calculate the yield loss of a single wafer, and the wafer affected by the single wafer yield loss and the previous term Based on the percentage of the plurality of wafers, a method of obtaining a total yield loss due symbols having each stage to estimate the total yield loss. 2. The single-yield loss is calculated by the following equation: [Equation 1] Of which I_0-SigIs a window when the Sig symbol appears once.
The yield loss of a single wafer brought to the wafer
_RegionIs the number of chips arranged in the Region area, I
_Region-SigIs the Region region when the Sig symbol appears once
Area characteristic yield loss brought to the chips of
C_totalIndicates the total number of chips on one wafer
The method of claim 1, as determined by: 3. The total yield loss is calculated by the following equation: I_impact-Sig = I_0-Sig× W_Sig/ W_total Of which I_impact-SigIs the total yield loss due to the Sig symbol
, W_SigIs the number of wafers bearing the Sig symbol, W_totalIs
Calculated by showing the number of all wafers, respectively
The method according to claim 1, wherein . 4. The method of claim 1, wherein the plurality of adjacent regions are substantially annular in appearance. 5. A multi-yield table for multiple wafers, each yield table corresponding to a yield of a related wafer under certain test conditions, and a plurality of characteristic bin yields, and the related wafers. Has a symbol column indicating whether or not the symbol is affected, and provides at least one test condition that can be influenced by the symbol, using the linear regression method, based on the plurality of yield tables, the symbol is Calculating the characteristic yield loss of at least one affected test condition when it appears once, and calculating the single yield loss by summing the characteristic yield loss, affecting the single yield loss and the previous term symbol. To obtain the total yield loss by the symbol having each step of obtaining the total yield loss based on the ratio of the number of wafers to the plurality of wafers Law. 6. The yield loss of a single wafer is expressed by the following equation: Of these, I _0-Sig represents the single-wafer yield loss that occurred for one wafer when the Sig symbol appeared once.
The method of claim 5, wherein _Bin-Sig is determined by indicating the characteristic yield loss introduced under the Bin test condition when the Sig symbol appears once. 7. The total yield loss is expressed by the following equation: I_impact-Sig = I_0-Sig× W_Sig/ W_total Of which I_impact-SigIs the total yield loss due to the Sig symbol
, W_SigIs the number of wafers bearing the Sig symbol, W_totalIs
Calculated by showing the number of all wafers, respectively
The method according to claim 5, wherein . 8. The method according to claim 5, wherein the test conditions include a DC voltage / current condition, an AC voltage / current condition, and a material writing capability. 9. To define a plurality of adjacent regions,
Dicing the chip array on the processed wafer surface, providing a multi-yield table for multiple wafers, each yield table having a region characteristic yield under test conditions with one corresponding region of the associated wafer ( regional bin y
and a symbol column indicating whether or not the related wafer is influenced by a symbol, and providing at least one region and a test condition that can be influenced by the symbol. Using, based on the yield table, to calculate the area characteristic yield loss that the affected test conditions brought to the at least one affected area when the symbol appears once, Based on the percentage of the affected area occupying the chip array, by summing the area characteristic yield loss, calculate the single-wafer yield loss that resulted for one wafer when the symbol appeared once. A step of obtaining a total yield loss based on the single-wafer yield loss and a ratio of the wafers affected by the previous term to the plurality of wafers How to obtain a total yield loss due symbols and. 10. The yield loss of a single wafer is expressed by the following formula: [Equation 3] Of which I_0-SigIs a window when the Sig symbol appears once.
The yield loss of a single wafer brought to the wafer
_RegionIs the number of chips arranged in the Region area, I
_{Bin-Region-Sig}Region when the Sig symbol appears once
Brought under the Bin test conditions for the area chip
Area characteristic yield loss is C_totalIs the total for one wafer
10. The number of chips is obtained by indicating each of them.
The method described in. 11. The total yield loss is calculated by the following equation: I_impact-Sig = I_0-Sig× W_Sig/ W_total Of which I_impact-SigIs the total yield loss due to the Sig symbol
, W_SigIs the number of wafers with the Sig symbol, W_totalIs all
The number of all wafers
The method according to claim 9. . 12. The method of claim 9, wherein the plurality of adjacent regions are substantially annular in appearance. 13. The method according to claim 9, wherein the test conditions include a DC voltage / current condition, an AC voltage / current condition, and a material writing capability.