JP3439096B2 - Terminating resistance controlled bus system - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bus system that requires a terminating resistor and an information processing apparatus including the bus system.

[0002]

2. Description of the Related Art As the speed of information processing devices has increased, it is common to connect terminating resistors to both ends of bus wiring in the device. As the termination resistor, a resistor having the same value as the characteristic impedance of the bus wiring is used. If the terminating resistor is not connected, the output signal is reflected at both ends of the bus wiring, and the waveform distortion of the signal occurs due to the superposition of the reflected signal and the output signal. This waveform distortion increases as the bus transmission speed increases, and normal signal transmission cannot be performed in some cases.

A method of connecting a terminating resistor to both ends of a bus wiring is, for example, DIGITAL BUS HANDBO.
OK Magazine (1990, Joseph Di Giacomo, McGraw-Hill P
Published by the ublishing Company, pages 14.6-14.13).

According to this conventional example, when a bus system as shown in FIG. 7 is present, the resistance value of the terminating resistor is the impedance of a portion where both the bus wiring and the stub wiring are combined (hereinafter referred to as "bus It is calculated based on the impedance of only the wiring), the capacity of the input / output circuit of the functional circuit connected to the bus, the capacity of the stub wiring, and the capacity of the bus wiring.

Specifically, the characteristic impedance of only the bus wiring is Zo, the capacity of the functional circuit per unit length (the sum of the capacity of the input / output circuit and the capacity of the stub wiring).
The effective impedance Z of the bus wiring can be expressed by the following (Equation 1), where C1 is the total sum of the above and C2 is the capacitance of the bus wiring per unit length.

[0006] Z = Zo / √ (1 + C1 / C2) (Equation 1)

[0007]

The functional circuits connected to the bus are not limited to those fixedly provided in the apparatus body. The functional circuit may be mounted on a substrate that can be attached to and detached from the apparatus body. Rather recently,
Various boards are usually added by the user. If the number of boards (that is, functional circuits) mounted on the device body changes, as can be seen from (Equation 1),
Naturally, the effective impedance of the bus wiring also changes.

However, in the conventional information processing apparatus, no measures have been taken regarding this point.

If the capacity of the input / output circuit of the functional circuit connected to the bus is small, the effective impedance of the bus wiring, that is, the resistance value of the terminating resistor becomes almost the same as the characteristic impedance of only the wiring, and no particular problem occurs. But
In an actual system, the capacity of this input / output circuit becomes so large that it cannot be ignored.

For example, when the impedance Zo of only the wiring is 50Ω, the capacitance of the input / output circuit is 15 pF, the length of the stub wiring is 2 cm, the length of the bus wiring is 30 cm, and the capacitance per 1 cm of the wiring is 1 pF. The total of the capacitance of the circuit and the capacitance of the stub wiring is 15pF + 1pF / cm × 2c
It is 17 pF in m. When four functional circuits are connected to the bus wiring, the total is 68 pF. The capacitance of the bus wiring is 30 pF at 1 pF / cm × 30 cm. When Zo = 50, C1 = 68, and C2 = 30 are applied to (Equation 1), the effective impedance Z of the bus wiring is 27Ω.

Here, if the number of functional circuits connected to the bus wiring is reduced to one, the total capacity of the functional circuits becomes 17 pF. When this is applied to (Equation 1) again with C1 = 17, the effective impedance of the bus wiring becomes 39Ω.

That is, although a terminating resistor of 39Ω should be used originally, it has been 27Ω in the past.

Such impedance mismatch of the transmission line increases the reflection coefficient as shown in (Equation 2).
Z is the resistance value of the termination resistor to be set.

Ρ = (γ−Z) / (γ + Z) (Equation 2) For example, in the above case, γ is 27Ω, Z is 39Ω, and the reflection coefficient ρ is −0.18.

This means that the reflection generated at the end of the bus wiring reaches 18% of the total signal level. If the signal level is 1V, the signal level after reflection is 0.82V. Become.

COMPUTER CIRCUITS ELECTRICAL DES
IGN magazine (1995, Ron K. Poon, Prentice-Hall,
In Table 3.5 described on page 82), the noise margin in the C-MOS circuit is 1250 mV, of which the maximum 800 mV is the noise component due to reflection. This indicates that it occupies 65% of the entire noise margin.

As described above, in the related art, when the circuit board is inserted and removed, mismatching of the terminating resistors occurs and reflection noise occurs, which has been a major obstacle to speeding up the system.

The object of the present invention is to solve the above-mentioned problems of the prior art, and even if the number and types of functional circuits connected to the bus wiring are changed, signal waveform distortion does not occur, resulting in data transfer. It is to provide a bus system capable of increasing the speed.

[0019]

According to one aspect of the present invention for achieving the above object, there is provided a bus system in which a plurality of circuit boards having the same degree of influence on the characteristic impedance of bus wiring are inserted and removed. A control circuit for changing the resistance value of the bus wiring, the terminating variable resistor connected to the end of the bus wiring, and the terminating variable resistor according to the number of circuit boards mounted in the bus system. There is provided a terminating resistance control type bus system characterized by comprising:

According to another aspect of the present invention for achieving the above object, there is provided a bus system including a plurality of circuit boards and a back panel into which the circuit boards are inserted and removed, wherein the back panel includes: Is provided with a bus line, a terminating variable resistor connected to the end of the bus line, and a control circuit capable of changing the resistance value of the terminating variable resistor,
Each of the circuit boards is provided with a storage circuit that stores component information regarding components mounted on the circuit board that affect the characteristic impedance of the bus wiring, and the control circuit is mounted on the back panel. A termination resistance control type bus system is provided, wherein the component information is extracted from the storage circuit of each circuit board and the resistance value of the termination variable resistor is changed based on the extracted component information.

According to still another aspect of the present invention for achieving the above object, there is provided a bus system comprising a plurality of circuit boards and a back panel into which these circuit boards are inserted and removed, wherein the back panel is provided. To determine the resistance of the data transmission bus line, the first terminating variable resistor connected to the end of the data transmission bus line, and the first terminating variable resistor. A test bus wire used, a second termination variable resistor connected to an end of the test bus wiring, a resistance value of the first termination variable resistor, and the second termination. A control circuit capable of changing each of the resistance values of the variable resistors for use is provided, and each of the circuit boards includes:
An output circuit that outputs a test signal to the test bus wiring and an input circuit that receives a test signal output from another circuit board via the bus wiring are provided, and the control circuit is the second circuit. The resistance value of the terminating variable resistor is sequentially changed, the test signal is output by the output circuit and the test signal is received by the input circuit each time, and the second terminating end is obtained based on each reception result. An optimal resistance value is selected from the resistance values sequentially set in the variable resistor for use in the terminal resistance control type bus system, and the selected resistance value is set in the first variable resistor for termination. Provided.

[0022]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Various embodiments of a bus system according to the present invention will be described below with reference to the drawings.

FIG. 1 is a schematic diagram showing the outline of the first embodiment of the present invention. In the figure, a back panel 102 fixed to a housing of the information processing apparatus and a functional circuit 105a are shown.
There are shown a circuit board 103a on which is mounted and a circuit board 103b on which the functional circuit 105b is mounted. Circuit board 10
3a is connected to the back panel 102 by the connector 104a.
It is removable with respect to. The circuit board 103b is
It can be attached to and detached from the back panel 102 by the connector 104b. Connectors 104a, 104b
Are each composed of both a circuit board side connector component and a back panel side connector component. On the back panel 102, in addition, a functional circuit 106, a bus wiring 101 including a plurality of signal lines, terminating resistors 111a and 111b connected to both ends of the bus wiring 101, and resistors of the terminating resistors 111a and 111b, respectively. A termination resistance control circuit 112 that changes the value is provided. Circuit board 103
Functional circuit 105a of a, functional circuit 1 of circuit board 103b
05a and the functional circuit 106 of the back panel 102
Are circuits having the same degree of influence on the characteristic impedance of the bus wiring 101. That is, in each functional circuit, the input / output circuit and the stub wiring (see FIG. 7) have the same specifications. The connector 107a is provided with a detection circuit 107a for detecting attachment / detachment of the circuit board 103a to / from the back panel 102. When the circuit board 103a is mounted on the back panel 102, the functional circuit 105a on the circuit board 103a and the bus wiring 101 on the back panel 102 are connected, and further, from the detection circuit 107a to the termination resistance control circuit 112. , A signal indicating that the circuit board 103a is mounted is output. Connector 10
4b is provided with a detection circuit 107b for detecting attachment / detachment of the circuit board 103b to / from the back panel 102. When the circuit board 103b is mounted on the back panel 102,
The functional circuit 105b on the circuit board 103b and the bus wiring 101 on the back panel 102 are connected, and further, from the detection circuit 107b to the termination resistance control circuit 112,
A signal indicating that the circuit board 103b is mounted is output. The termination resistors 111a and 111b are variable resistors. One end of the termination resistor 111a is connected to the bus line 101, and the other end is connected to a setting unit that sets the termination voltage (Vtt). The termination voltage (Vtt) may be the supply voltage of the power supply of the present information processing apparatus, or may be other voltage (for example, 0V (ground)). The same applies to the termination resistor 111b. Further, in the drawings, for simplification of description, the terminating resistors 111a, 11a
Although only 1b is shown in the figure, actually, not only this one set but the bus width of the bus wiring 101 is provided. For example, if the bus width is 16 bits, 16 sets of terminating resistors will be provided.

Then, the termination resistance control circuit 112 detects the number of circuit boards mounted on the back panel 102 from the detection signals of the detection circuits 107a and 107b, and the termination resistors 111a and 111a are detected in accordance with the number. Change each resistance value of 111b. At this time, the termination resistors 111a and 111a
Each resistance value of b is set to the same value.

In the present embodiment, the number of functional circuits connected to the bus wiring 101 via the connector is two, and the number of functional circuits directly connected to the bus wiring 101 without the connector is one. However, the number of these may be arbitrarily determined according to the scale of the apparatus. Detection circuits 107a, 1
For example, 07b is configured so that a dedicated pin is provided in each of the connectors 104a and 104b to form a loop wiring, and a signal can be output depending on the presence / absence of the connection. Instead of the detection circuits 107a and 107b, a switch that can be operated by the user may be provided so that the state of the switch can be detected as whether or not the circuit board is connected.

Next, the structure of the terminating resistor 111a will be described with reference to FIG. The terminating resistor 111b
Has the same structure.

In FIG. 2, 201, 202, 203
Are fixed resistors having different resistance values.
211, 212, and 213 are in a conductive state (on state) and a cutoff state (off state) in accordance with a given switching signal.
It is a switch that is set to either. Switch 21
1, 212, and 213 may be configured by relays or field effect transistors. Resistor 201,
202, 203 and the switches 211, 212, 213,
Each is connected in series. Further, as shown in FIG. 14, instead of the switch 211 and the resistor 201, a field effect transistor 1401 having an on-resistance of the same value as the resistance value of the resistor 201 may be used. Similarly, resistor 20
2 and field effect transistor 1 instead of switch 212
The field effect transistor 1403 can be used instead of the resistor 203 and the switch 213 (the field effect transistor 1404 is not provided when applied to this embodiment). Details of FIG. 14 will be described later.
In the figure, three sets of resistors and switches are provided, the number of which is determined based on the maximum number of circuit boards to be mounted. Reference numeral 220 denotes a decoding circuit, which turns on one of the switches 211, 212, and 213 according to the control signal output from the termination resistance control circuit 112 in FIG. In the present embodiment, this control signal is a signal indicating the number of circuit boards mounted on the back panel 102.

Next, the relationship between the number of circuit boards mounted on the back panel 102 and the operation of the terminating resistor 111a will be described. The terminating resistor 111b operates similarly to the terminating resistor 111a.

In this embodiment, there are the following four states depending on the combination of the connection between the back panel 102 and the substrates 103a and 103b.

The first state is a state in which two substrates 103a and 103b are connected, and the second state is a state in which only one substrate 103a is connected.
In this state, only one of the substrates 103b is connected, and in the fourth state, both of the substrates 103a and 103b are not connected.

The decode circuit 220 receives a control signal from the termination resistance control circuit 112, which indicates the number of circuit boards mounted, and as a result, the switch 2 in the first state.
11 is turned on, switch 212 is turned on in the second or third state, and switch 2 is turned on in the fourth state.
13 is turned on. Note that the resistance value of the resistor 201 is the bus wiring 101 when two circuit boards are connected.
It is determined so that the waveform distortion of the signal flowing through is minimum. This value may be calculated using (Equation 1). Similarly, the resistance value of the resistor 202 is a waveform of a signal flowing through the bus wiring 101 when one circuit board is connected, and the resistance value of the resistor 203 is when no circuit board is connected. The distortion is determined to be the smallest.

For example, the characteristic impedance Zo of only the wiring of the bus wiring 101 is 50Ω, the functional circuits 105a, 1
Assuming that each of the capacitors 05b and 106 has a capacitance of 17 pF and the bus wiring 101 has a capacitance of 30 pF, the following results are obtained.

Circuit boards 103a, 10 are provided on the bus wiring 101.
When both 3b are connected, the total capacitance of the functional circuits is 51 pF. Zo = 50Ω, C1 = 51 pF,
If these are applied to (Equation 1) with C2 = 30 pF, the effective impedance Z of the bus wiring 101 becomes 30Ω, so the value of the resistor 201 may be set to 30Ω.

Circuit boards 103a, 10 are provided on the bus wiring 101.
When either one of 3b is connected, the total capacitance of the functional circuits is 34 pF. In this case, since Z is 34Ω according to (Equation 1), the value of the resistor 202 is 34Ω.
It should be done.

When neither of the circuit boards 103a and 103b is connected to the bus line 101, the capacity of the functional circuit is only 17 pF of the functional circuit 106. In this case, since Z is 39Ω from (Equation 1), the resistor 20
The value of 3 may be 39Ω.

During the period in which the resistance values of the terminating resistors 111a and 111b are changed by the terminating resistance control circuit 112, while the data transfer by the bus wiring 101 is not executed (for example, the power of the bus system is turned on). Since then
After a reset signal is sent to the bus system until data is actually transmitted to the bus wiring 101,
This is performed while the bus system is in operation until data is transmitted to the bus wiring 101 and while the bus wiring 101 is waiting for data transfer.

As described above, according to the present embodiment, even if the number of functional circuits connected to the bus wiring 101 changes, the resistance value of the terminating resistor is set to the optimum value accordingly. Therefore, the reflection of the signal at each end of the bus line 101 is suppressed and the distortion of the signal waveform is reduced, as compared with the related art. If the signal waveform distortion can be reduced in this way, the data transfer rate between the functional circuits can be increased in the system design stage.

The bus system of this embodiment may be one in which hot plugging of the circuit board is possible.

When the circuit board is hot-swapped, first, all bus access and control signal transmission / reception performed via the bus wiring 101 are stopped. After that, the operator removes or adds the circuit board. The change in the number of circuit boards is detected by the detection circuit described above. The termination resistance control circuit 112 sets each resistance value of the termination resistors 111a and 111b according to the change in the number of circuit boards. When the setting of the resistance value is completed, the bus access and the transmission / reception of the control signal are restarted.

Next, a second embodiment of the present invention will be described with reference to FIG.

The present embodiment differs from the first embodiment in that the information storage circuits 301a and 301b are replaced by circuit boards 103a and 10b instead of the detection circuits 107a and 107b.
3b, the information storage circuit 302 is provided on the back panel 102, the information storage circuit 301a,
(Equation 1) is executed using each information of 301b and 302,
Depending on the calculation result, the terminating resistors 311a, 311b
That is, the termination resistance control circuit 312 for changing each resistance value is provided. The resistance values of the terminating resistors 311a and 311b are set to the same value as in the first embodiment. In addition,
The information storage circuits 301a, 301b, and 302 may be, for example, Philips PCF8522E, and the termination resistance control circuit 312 may be, for example, Philips PCF8544, to be connected to each information storage circuit. May be. According to this structure, information transmission between each information storage circuit and the termination resistance control circuit 312 can be realized by two signal lines.

The information storage circuit 301a includes the circuit board 103.
The information about the functional circuit 105a on a (in this embodiment, the capacitance of the stub wiring and the capacitance of the input / output circuit regarding the functional circuit 105a) is stored. The stub wiring and the input / output circuit are components mounted on the circuit board 103a and have an effect on the effective impedance of the bus wiring 101. This effect is as in (Equation 1). The information storage circuit 301b is the functional circuit 105b on the substrate 103b.
The information (in the present embodiment, the capacitance of the stub wiring and the capacitance of the input / output circuit regarding the functional circuit 105b) is stored. If the circuit boards 103a and 103b are, for example, memory boards, the information storage circuits 301a and 301b.
In addition, the memory capacity and access time may be stored.

The information storage circuit 302 includes a back panel 1
Information about the functional circuit 106 directly mounted on the H.02 (in this embodiment, the capacitance of the stub wiring and the capacitance of the input / output circuit regarding the functional circuit 106), the characteristic impedance of only the wiring of the bus wiring 101, and the capacitance of the bus wiring 101. Remembered

In this embodiment, two functional circuits are connected to the bus wiring 101 via the connector,
There may be one, or there may be three or more. Further, two or more functional circuits directly connected to the bus wiring may be present or may not be present.

The termination resistors 311a and 311b are connected to both ends of the bus wiring 101. Termination resistor 311
The other ends of a and 311b are connected to a setting unit that sets a termination voltage (Vtt). The termination voltage (Vtt) may be the supply voltage of the power supply of the information processing apparatus, or
It may be 0 V (ground). Also, the terminating resistor 3
Although only one set of 11a and the terminating resistor 311b is illustrated, actually, the terminating resistor is connected to all the bits of the signal line of the bus width.

The termination resistance control circuit 312 stores information stored in the information storage circuit 301a (capacity of stub wiring and input / output circuit regarding the functional circuit 105a) and information stored in the information storage circuit 301b ( Functional circuit 10
5b capacity of stub wiring and capacity of input / output circuit)
Information stored in the information storage circuit 302 (capacitance of the stub wiring and capacitance of the input / output circuit regarding the functional circuit 106, characteristic impedance of only the wiring of the bus wiring 101,
And (capacity of the bus wiring 101) is substituted into (Equation 1),
Depending on the calculation result, the terminating resistors 311a, 311b
Set each resistance value of. Termination resistors 311a, 311b
Each resistance value of is set to the same value as described above.

Next, the structure of the terminating resistor 311a will be described with reference to FIG. The terminating resistor 311b
Has a similar structure.

In FIG. 4, 401, 402, 403,
422, 423 and 424 are fixed resistors having a predetermined resistance value. 411, 412, 413, 431, 43
Reference numerals 2, 433 and 434 are switches that are set to either a conductive (on) state or a cutoff (off) state in accordance with a given switching signal. A decoding circuit 441 turns on one of the switches 411, 412, and 413 and sets the other two off according to the content of the control signal output from the termination resistance control circuit 312. The decoding circuit 442 switches the switches 431, 432, and 4 according to the content of the control signal output from the termination resistance control circuit 312.
One of 33 and 434 is turned on, and the other three are turned off. In the figure, resistors 401, 40
2, 403, the switches 411, 412 and 413, and the decoding circuit 441 constitute a rough setting circuit 451 that roughly sets the terminating resistor 311a. Also, resistors 422, 423, 424, switches 431, 432, 4
33, 434 and the decoding circuit 442 constitute a fine setting circuit 452 for fine setting the terminating resistor 311a.

In the rough setting circuit 451, as described above,
One of the resistors 401 to 403 is the decoding circuit 44.
In the fine setting circuit 452, one of the ends of the resistors 422 to 424 connected in series is selected by the decoding circuit 442.
Selected by one of 434b. For example, when the switch 431 is selected and turned on, all the resistors 422, 423, and 424 are bypassed, and the resistance value of the fine setting circuit 452 becomes almost zero. Also,
When the switch 432 is selected and turned on, the resistance value of the fine setting circuit 452 becomes equal to the resistance value of the resistor 422. When the switch 433 is selected, the resistance values of the fine setting circuit 452 are the same as those of the resistors 422 and 423.
When the switch 434 is selected, the resistance value of the fine setting circuit 452 is equal to that of the resistor 422 and the resistor 42.
3 and the resistance value of the resistor 424.

Here, the resistance value of only one resistor selected in the rough setting circuit 451 is Sa, and the fine setting circuit 4
In S52, if the resistance value of the resistor not bypassed is Sb and the termination resistance value is Rtt, Rtt and S
The relationship between a and Sb can be expressed using the following (formula 2).

Rtt = Sa + ΣSb (Equation 3) b = 422, 423, 424 For example, the resistance values of the resistors 401, 402, 403 are set to 20Ω, 30Ω, 40Ω, and the resistors 422, 4 are used.
When all the resistance values of 23 and 424 are 2.5Ω, when the switches 411 and 432 are turned on, Sa = 20,
Since ΣSb = 2.5, Rtt is 22.5Ω.

The terminating resistance control circuit 312 first executes (Equation 1) using each information of the information storage circuits 301a, 301b and 302, and then combines the coarse setting circuit 451 and the fine setting circuit 452. From a plurality of feasible set values, the one closest to the calculation result of (Equation 1) is selected and set to the termination resistor 311a. Similarly, this value is also set to the termination resistor 311b.

As described above, according to the present embodiment, even if the number of functional circuits connected to the bus wiring 101 and the type thereof are changed, it is possible to cope with them without difficulty.

The period during which the termination resistance control circuit 312 switches the resistance values of the termination resistors 311a and 311b is
As in the first embodiment, after a reset signal is sent to the bus system after the bus system is powered on and before data is transmitted to the bus wiring 101, the bus wiring 1
Before the data is transmitted to 01, the bus system is in operation, and is performed while the bus wiring 101 is waiting for data transfer.

A third embodiment of the present invention will be described with reference to FIG.

This embodiment is different from the first embodiment in that the test bus wiring 520 is wired in parallel with the bus wiring 101, and the detection circuits 107a, 1
Test signal input / output circuits 501a and 501b instead of 07b
Is provided on the circuit boards 103a and 103b,
The test signal input / output circuit 502 and the termination resistance control circuit 512 are provided on the back panel 102. Each of the test signal input / output circuits 501a, 501b, 502 is configured to include an output circuit that outputs a test signal and an input circuit that receives a test signal output from another test signal input / output circuit. . Test bus wiring 520
As with the bus wiring 101, both ends of the
a and 521b are connected. Termination resistance control circuit 51
2 is a test signal input / output circuit 501a, 501b, 502
And the test bus wire 520 are used to narrow down the termination resistance value to be set, and the resistance value most suitable for the bus system is set to the termination resistors 511a and 511 of the bus wiring 101.
Set to b. Here, the test bus wiring 520 is used.
A pair of terminating resistors 521a and 521b is shown in FIG.
Although one set of 1b is illustrated, the terminating resistor is connected to all the signal lines forming the bus, as described above. In addition, the termination resistors 511a, 511b, 521a, 521
The other end of b is set in the terminal voltage (Vtt) setting section, as described above. The test bus wiring 520 has the same form as the bus wiring 101, but it is not necessary to provide the same number of signal lines as the bus width of the bus wiring 101. For example, the bus width of the test bus wiring 520 may be 1 bit.
The termination resistors used in the first embodiment (or the second embodiment) are used as the termination resistors 511a, 511b, 521a, 521b.

Next, the operation of the termination resistance control circuit 512 until the respective resistance values of the termination resistors 511a and 511b are determined will be described.

The termination resistance control circuit 512 first sets the termination resistors 52a and 521b to the termination resistors 52a and 52b.
Any resistance value included in the variable range (variable range) of 1a and 521b is set. At this time, the functional circuits 105a, 105b, 106 connected on the wiring 101.
If it is assumed that the capacity due to is the smallest, the highest value in the variable range is set. For example, when the variable range is as shown in FIG. 9, the termination resistors 521a and 521 are initially set to 50Ω. Termination resistors 521a, 5
The resistance value of 21b is the same as that described above.

Next, the termination resistance control circuit 512 selects one of the test signal input / output circuits 501a, 501b and 502. The selected test signal input / output circuit outputs the test signal to the test bus line 520. FIG. 8 shows how the test signal is output from the test signal input / output circuit 502. This test signal is transmitted to another test signal input / output circuit (here, the test signal input / output circuit 5
01a, 501b). Each of the test signal input / output circuits 501a and 501b determines whether or not the state of the received test signal is as expected, and when the signal is poor, it is judged as failure, and when it is good, it is judged as success and is terminated. Notify the resistance control circuit 512. Termination resistor 521a,
If the resistance value of 521b is inappropriate, the termination resistor 52
Impedance mismatch between the 1a and 521b and the test bus line 520 occurs, causing waveform distortion of the signal. If this distortion is large, the test signal input / output circuit cannot input a correct test signal. On the other hand, the termination resistance control circuit 512
Is provided with a management table as shown in FIG. The management table is filled with each item based on the test result sent from the test signal input / output circuit. Specifically, if one of the two test signal input / output circuits on the input side also fails, the resistance value item is
"X" is set, and if both are successful, "○" is set.

Then, the termination resistance control circuit 512 changes the test signal input / output circuit on the output side, and outputs the test signal to the test bus wiring 520 again from the test signal input / output circuit.

The above series of operations is performed by the variable termination resistor 52.
In the variable range of 1a and 521b, the resistance value is gradually lowered and repeated.

Finally, the termination resistance control circuit 512 sets the value of the center of the range in which the test signal can be normally transmitted (40 Ω which is the center of the range A in FIG. 9) to the termination resistors 511a and 511.
11b.

The above-mentioned test signal corresponds to the bus wiring 101.
It is preferable that the signal has the shortest rise time and the shortest period that can be transmitted by. The output of the test signal is
It is preferable to carry out a plurality of times.

The switching period of the resistance values of the variable terminating resistors 511a and 511b by the terminating resistance control circuit 512 is the same as in the first and second embodiments. Until after the reset signal is sent to the bus system,
It is preferable that the bus system is in operation before data is transmitted to the bus line 101, and is performed while the bus line 101 is waiting for data transfer.

As described above, according to this embodiment, even if the number or the configuration of the functional circuits connected to the bus wiring 101 changes, the signal can be suppressed from being reflected at both ends of the bus wiring 101. Furthermore, by conducting an automatic test regularly,
The termination resistance is optimized even when there is a change in the environment (for example, a change in power supply voltage or a change in drivability due to a change in temperature).

A fourth embodiment of the present invention will be described with reference to FIG.

FIG. 6 shows an example in which the first to third embodiments described above are applied to a fault tolerant computer.

In this fault tolerant computer, units of the same structure are duplicated and a shared unit is provided between them to improve fault tolerance.

Specifically, a unit having CPUs 601, 602, a main memory 521, a bus bridge 611, and connectors 653, 654, a CPU 603,
604, the main memory 622, the bus bridge 612, and the unit having the connectors 651 and 652 are
AID (Redundant Arrays of Inexpensive Disks) disks 641 and 642 and communication function modules 651 and 6
Share the unit with 52.

The bus bridge 611 includes the CPUs 601 and 6
02 and the main memory 521 are connected to the connectors 653, 6
It is connected to the system buses 681 and 682 via 54.
A bus bridge 631 is provided for the system buses 681 and 682.
Are connected, and the connectors 655 and 657 of the shared unit are connected to the other end via the IO bus 691.

The bus bridge 612 includes the CPUs 603 and 6
04 and the main memory 622 to the connectors 651, 6
It is connected to the system buses 681 and 682 via 52.
A bus bridge 632 is provided for the system buses 681 and 682.
Are connected, and the connectors 656 and 658 of the shared unit are connected to the ends thereof via the IO bus 692.

The RAID disks 641 and 642 are provided between the connector 655 and the connector 656, and the communication function modules 651 and 652 are provided between the connector 657 and the connector 658.

Further, in the present embodiment, the bus 6 is further added.
Termination resistor 700 in which the first embodiment (or the second embodiment) is used for each termination of 81, 682, 691, 692.
Is provided and its control circuit (not shown) is added.

According to this structure, even if the defective module is attached or detached or a new function is added while the system is energized and operating, the waveform distortion due to the change in the capacitance of the bus wiring can be suppressed, and the system Improves reliability. Also,
This system can be applied to an accounting system, an automatic ticketing / reservation system, an exchange, etc., in which system down is not allowed.

The fifth embodiment will be described below.
The same applies to the sixth embodiment.

Next, regarding the fifth embodiment of the present invention,
This will be described with reference to FIGS. 10, 11, 12, and 14.

FIG. 10 is a block diagram of the first to third embodiments described above, showing the SSTL (Stub Series Terminated Logic, EI).
AJ ED-5512) It is a block diagram showing an example applied to a bus system.

In the figure, a back panel 1002 fixed to the housing of the information processing apparatus, a memory module 1003a having a memory 1005a mounted therein, and a memory 1005b.
And a memory module 1003b equipped with
05c mounted memory module 1003c and memory 1005d mounted memory module 1003d
And are shown.

In this embodiment, the memory module corresponds to the circuit board (for example, 103a in FIG. 1) in the first to third embodiments, and the memory and the memory controller are in the first to third embodiments. Functional circuit in the form (for example, the memory is 105a, b of FIG. 1,
The memory controller corresponds to 106) in FIG.

In this embodiment, only one memory is shown for each memory module, but a plurality of memories may be mounted on one memory module. For example, if the number of data lines of the memory module is 64 and the number of data lines per memory is 8, the memory module 1
The number of memories mounted in each is eight. Further, in addition to the memory, the information storage circuit described in the second embodiment may be mounted.

The memory module 1003a has stub wiring between the bus wiring 1001 and the memory 1005a, and the matching resistor 1022a is inserted in the stub wiring section. Similarly, the memory modules 1003b-
Matching resistors 1022b to 1022d are also inserted in the stub wiring 1003d, respectively.

In this embodiment, the matching resistor 1
022a to 1022d are inserted in positions near the bus wiring 1001 in the stub wiring section, and the short stub wiring between the matching resistors 1022a to 1022d and the bus wiring 1001 is omitted, that is, the matching resistor 1022a. 1022d directly to the main bus wiring 10
01 may be connected.

The memory module 1003a can be attached to and detached from the back panel 102 by a connector 1004a. Similarly, the memory module 1003b
To 1003d are connectors 1004b to 1040, respectively.
By 04d, it is removable from the back panel 1002.

In this embodiment, the connector 1004a
Reference numeral 1004d denotes an edge connector on the back panel side. Memory modules 1003a-1003
A wiring pattern (not shown) for contacting the contact pin provided on the edge connector is provided at d.

On the back panel 1002, in addition, a memory controller 1006, a bus wiring 1001 composed of a plurality of signal lines, terminating resistors 1011a and 1011b connected to both ends of the bus wiring 1001, and a terminating resistor 1 are provided.
A terminating resistance control circuit 1012 for changing each resistance value of 011a and 1011b and a matching resistor 1021 are provided.

The matching resistor 1021 is inserted in the stub wiring section between the memory controller 1006 and the bus wiring 1001.

Matching resistors 1021 and 1022a
Reference numerals -1022d are provided for impedance matching (taking impedance matching) between the bus wiring 1001 and the stub wiring on the memory module.

In the present embodiment, the matching resistor 1
022a to 1022d are memory modules 1003a
Although provided on the side of 1003d, the back panel 10
It may be provided on the 02 side.

Memory modules 1003a-1003d
Is configured such that the load capacitance of the input / output circuit of the memory, the length of the stub wiring, and the characteristic impedance of the wiring are the same.

The connector 1004a has a back panel 1
A detection circuit 1007a for detecting attachment / detachment of the memory module 1003a to / from the memory module 002 is provided. When the memory module 1003a is attached to the back panel 1002, the memory 1005a on the memory module 1003a
And the bus wiring 1001 on the back panel 1002 are connected. Further, from the detection circuit 1007a toward the termination resistance control circuit 1012, the memory module 1003a
A signal indicating that the is attached is output.

Similarly, the connectors 1004b to 1004d
Also, detection circuits 1007b to 1007d for detecting attachment / detachment of the memory module to / from the back panel 1002 are provided, and when the memory module is attached to the back panel 1002, the detection circuits 1007b to 1007d cause the termination resistance control circuit 1012 to change. Towards the memory module 1
A signal indicating that 003b to 1003d are attached is output.

The termination resistors 1011a and 1011b are variable resistors.

One end of the terminating resistor 1011a is connected to the bus line 1001 and the other end is connected to a terminating voltage source (Vtt). The same applies to the termination resistor 111b.

Further, in the drawings, in order to simplify the explanation,
Although only the terminating resistors 1011a and 1011b are shown, actually, not only this one set but also the bus wiring 1001.
It is provided for the width of the bus. For example, if the bus width is 64 bits, 64 sets of terminating resistors will be provided.

Then, the termination resistance control circuit 1012 detects the number of memory modules mounted on the back panel 1002 by the detection signals of the detection circuits 1007a to 1007d, and the termination resistor 1011 is detected according to the number.
The resistance values of a and 1011b are changed. At this time, the resistance values of the termination resistors 1011a and 1011b are set to the same value.

In this embodiment, the number of memories connected to the bus wiring 1001 via the connector is four, and the number of memory controllers directly connected to the bus wiring 101 without the connector is one. However, these numbers are
It may be arbitrarily determined according to the scale and configuration of the device.

The detection circuits 1007a to 1007d are provided with, for example, dedicated pins for detecting connection to the connectors 1004a to 1004d, and further, the memory module 1003 is provided.
It is advisable to connect the wiring pattern, which is provided in a to 1003d, that comes into contact with the dedicated pin to the power supply wiring.

With this configuration, when the memory modules 1003a to 1003d are connected to the back panel 1002, power is supplied to the dedicated pins of the connectors 1004a to 1004d, and this is used as a detection signal for the termination resistance control circuit. 1012 can be sent.

Further, instead of the detection circuits 1007a to 1007d, a switch that can be operated by the user may be provided so that the state of the switch can be detected as whether or not the memory module is connected.

In this embodiment, the back panel 100 is used.
2 and the memory modules 1003a to 1003d are connected in combination with each other.
If at least one of 3d is connected to the back panel 1002, there are the following four states.

The first state is the memory module 1003.
Only one of a to 1003d is the back panel 1002
In the second state, only two of the memory modules 1003a to 1003d are connected. The third state is a state in which three of the memory modules 1003a to 1003d are connected, and the fourth state is a state in which the memory module 100 is
This is a state in which all four of 3a to 1003d are connected.

The effective impedance of the bus wiring 1001 in the first state is Ze1, the effective impedance of the same bus wiring in the second state is Ze2, the effective impedance of the same bus wiring in the third state is Ze3, and the effective impedance in the third state is Ze3. The effective impedance of the bus wiring is represented by Ze4, and these effective impedances are calculated. Ze1 to Ze4 indicate impedance reduction with respect to the characteristic impedance Zo of the bus wiring 1001.
It is the effective impedance.

The impedance Zo of the wiring only is 50Ω,
Input / output circuit capacity is 5 pF, stub wiring length on the memory module is 2 cm, and bus wiring 1001 length is 5 c.
m, and the capacitance per 1 cm of wiring is 1 pF, the total capacitance of the input / output circuit and the stub wiring is 5 pF + 1 p
It is 7 pF at F / cm × 2 cm. The capacitance of the bus wiring is 5 pF at 1 pF / cm × 5 cm.

In the first state, since the number of memories connected to the bus wiring 1001 is 2, Zo =
Applying these to (Equation 1) with 50Ω, C1 = 14 pF, and C2 = 5 pF, the effective impedance Ze1
Is 26Ω. Similarly, in the second state, the bus wiring 1
The number of memories connected to 001 is 3, and the effective impedance Ze2 is 22Ω. In the third state,
The number of memories connected to the bus wiring 1001 is 4, and the effective impedance Ze3 is 19Ω. In the fourth state, the number of memories connected to the bus wiring 1001 is 5, and the effective impedance Ze4 is 18Ω.

In any of the above states, the effective impedance is lower than the characteristic impedance Zo.

Next, a configuration example of the termination resistor 1011a will be described with reference to FIG.

The terminating resistor 1011b has a similar structure.

In FIG. 11, 1101, 1102a ...
1102c are resistance values Ro, Ra, Rb, and R, respectively.
It is a fixed resistor having c and Rd.

Reference numerals 1112a to 1112c are switches that are set to either a conductive state (on state) or a cutoff state (off state) according to a given switching signal.
In the present embodiment, this switch is composed of a field effect transistor, but it may be composed of a relay instead. The structure of the switch will be described later.

Fixed resistors 1101 and 1102a ...
1102c is connected in series. Further, the fixed resistor 1102a and the switch 1112a are connected in parallel. Similarly, the fixed resistor 1102b and the switch 1112b are connected in parallel, and the fixed resistor 1102c
And the switch 1112c are connected in parallel.

In the figure, three sets of switches are provided, the number of which is determined based on the maximum number of memory modules to be mounted.

Reference numeral 1141 denotes a decoding circuit, which is shown in FIG.
Of the fixed resistors 1102a to 1112c by switching the on / off states of the switches 1112a to 1112c in accordance with the control signal output from the terminal resistance control circuit 1012.
Bypass 02c.

The operation of the terminating resistor 1011a will be described.

The terminating resistor 1011b operates similarly to the terminating resistor 1011a.

A control signal corresponding to the number of connected memory modules is sent from the termination resistance control circuit 1012 to the decoding circuit 114 provided in the termination resistor 1011a.
Sent to 1.

The decoding circuit 1141 turns on / off the switches 1112a-1112c according to the control signal sent thereto.

When the number of memory modules mounted on the back panel 1002 is 4, the decoding circuit 1141
Turns on all the switches 1112a to 1112c. At this time, the resistance value of the termination resistor 1011a is
It has the same value as the effective impedance Ze4 in the above-mentioned fourth state.

When the number of memory modules mounted on the back panel 1002 is 3, the decoding circuit 1141
Turns off the switch 1112a and switches 1112a
b, 1112c is turned on. The resistance value of the terminating resistor 1011a at this time is the same value as the effective impedance Ze3 in the third state.

When the number of memory modules mounted on the back panel 1002 is 2, the decoding circuit 1141
Turns off the switches 1112a and 1112b and turns on the switch 1112c. The resistance value of the terminating resistor 1001a at this time is the same as the effective impedance Ze2 in the second state.

When the number of memory modules mounted on the back panel 1002 is 1, the decoding circuit 1141
Turns off all the switches 1112a to 1112c. At this time, the resistance value of the termination resistor 1011a is
It has the same value as the effective impedance Ze1 in the first state.

Fixed resistors 1101, 1102a to 110
The resistance value of 2c is expressed using the following equations (Equations 4, 5, 6, 7).

Ro = Ze4 (Equation 4) Ra = Ze3-Ze4 (Equation 5) Rb = Ze2-Ze3 (Equation 6) Rc = Ze1-Ze2 (Equation 7) (where Ze1>Ze2>Ze3> Ze4) Effective impedances Ze1, Ze2, Ze obtained earlier
From 3 and Ze4, the resistance value of each fixed resistor is Ro
= 18Ω, Ra = 1Ω, Rb = 3Ω, Rc = 4Ω.

By setting the resistance value of each fixed resistor in this way, the relationship between the effective impedance of the bus wiring 1001 and the terminating resistors 1011a and 1011b can be optimized.

Next, a configuration example of the switch 1112a will be described.
This will be described with reference to FIG.

The switches 1112b and 1112c have the same structure.

Reference numeral 1201a is an N-channel field effect transistor (hereinafter referred to as FET), which has three terminals of a source terminal (S1), a drain terminal (D1) and a gate terminal (G1). The same applies to 1201b (S2, D
2, G2).

Source terminals (S1, S2) of the FETs 1201a, 1201b are connected to each other, and gate terminals (G1, G2) are
2) Connect each other. D1 and D2 of the FETs 1201a and 1201b are connected to the terminals of the fixed resistor 1102a, respectively.

This structure is one of the general methods used for bidirectionally passing a current between the source and drain terminals of an FET. By applying a voltage to the gate terminals (G1, G2) of the FETs 1201a, 1201b, the drain terminals (D1, D2) are turned on.

In the present embodiment, the FET 1201
N channel FET is used for a and 1201b.
P-channel FETs may be used for the ETs 1201a and 1201b. When using a P-channel FET, applying a voltage to the gate terminal causes the drain terminal (D1,
D2) is turned off.

In the SSTL bus system, the direction of the current flowing through the terminating resistor is bidirectional.
By connecting T in series, a current can flow in both directions.

Next, another configuration example of the terminating resistor 1011a will be described with reference to FIG.

The termination resistor 1011b can be similarly constructed.

Reference numerals 1401 to 1404 are switches composed of FETs, each having a gate terminal (G) and two drain terminals (D1, D2).

In the present embodiment, the switches 1401-14
As shown in FIG. 12, 04 is configured by connecting two FETs in series, but any switching element capable of bidirectionally passing a current may be used.

By applying a voltage to the gate terminals (G) of the switches 1401 to 1404, the drain terminals are switched to the ON state (low resistance state). Switch 1401
1404 has a resistance value (ON resistance) in the ON state, and these resistance values are respectively Ron1, Ron2, and Ron.
It is represented by on3 and Ron4.

A control signal corresponding to the number of connected memory modules is sent from the termination resistance control circuit 1012 to the decoding circuit 144 provided in the termination resistor 1011a.
Sent to 1. The decode circuit 1441 turns on one of the switches 1401-1404 depending on the number of memory modules mounted on the back panel 1002.

Here, when the number of memory modules mounted on the back panel 1002 is 1, the decoding circuit 1441 turns on the switch 1401 and turns off the switches 1402-1404. Here, the on-resistance Ron1 of the switch 1401 is set to be the same as the effective impedance Ze1 obtained above.

When the number of memory modules mounted on the back panel 1002 is 2, the decoding circuit 1441
Turns on the switch 1402,
1, 1403, and 1404 are turned off. Switch 1
The on-resistance Ron2 of 402 is set to be the same as the effective impedance Ze2 obtained above.

When the number of memory modules mounted on the back panel 1002 is 3, the decoding circuit 1441
Turns on the switch 1403, and the switch 140
1, 1402, and 1404 are turned off. Switch 1
The on-resistance Ron3 of 403 is set to be the same as the effective impedance Ze3 obtained above.

When the number of memory modules mounted on the back panel 1002 is 4, the decoding circuit 1441
Turns on the switch 1404 and turns on the switch 140.
1 to 1403 are turned off. The on resistance Ron4 of the switch 1404 is set to be the same as the effective impedance Ze4.

As in this embodiment, the termination resistor 1011
Even if a and 1011b are configured, the relationship between the effective impedance of the bus wiring 1001 and the terminating resistors 1011a and 1011b can always be optimized.

As described above, according to this embodiment, in the memory system using the SSTL bus, even if the effective impedance is reduced with respect to the characteristic impedance of the bus wiring due to the mounting of the memory module, the terminating resistor is used. By matching the resistance value of the signal with the effective impedance, the signal reflection and the signal waveform distortion at each end of the bus wiring can be reduced, and the data transfer rate between the memory and the memory controller can be increased.

Further, by using the configuration described in the second embodiment above in the memory system using the SSTL bus, the characteristic impedance and load capacity of the memory module mounted on the back panel can be changed for each memory module. Even if they are different from each other, the same effect can be obtained.

In summary, an information storage device is provided in the memory module, the characteristic impedance of the memory module and the load capacity of the input / output circuit of the memory are stored in the information storage device, and the termination is performed based on this information. The resistance value of the resistor may be set.

Further, by using the configuration described in the above-mentioned third embodiment in the memory system using the SSTL bus, the characteristic impedance and load capacity of the memory module mounted on the back panel can be changed for each memory module. Even if they are different from each other, the same effect can be obtained.

In summary, a test bus wiring having the same structure as the original bus wiring is provided on the back panel, and a test input / output circuit is further provided on the memory module or the back panel. The test signal may be transmitted to the input terminal to set the resistance value of the terminating resistor capable of transmitting the test signal between the input / output circuits.

Next, a sixth embodiment of the present invention will be described with reference to FIG.

FIG. 13 is a block diagram showing another example in which the present invention is applied to the SSTL bus system.

This embodiment is different from the fifth embodiment in that matching resistors 1021 and 102 are used.
2a to 1022d are replaced by matching resistors 1321 and 1322a to 1322d having variable resistance values, and both the matching resistor and the terminating resistor are controlled in place of the terminating resistance control circuit 1012. The resistance control circuit 1312 is provided.

In this embodiment, the matching resistor 1
322a to 1322d are provided on the back panel 1002 side.
It may be provided on the 1003d side.

The termination resistance control circuit 1312 is equivalent to the detection circuit 1
Each of the detection signals 007a to 1007d detects the number of memory modules mounted on the back panel 1002, and the terminating resistors 1011a and 101 are detected according to the number.
1b and matching resistors 1321, 1322a-132
Each resistance value of 22d is changed. At this time, the resistance values of the matching resistors 1321, 1322a to 1322d are
Set all to the same value.

In this embodiment, the matching resistors 1321 and 1322a to 1322d have the same resistance value, but the memory modules mounted on the back panel 1002 have different characteristic impedances. In this case, different values may be set for each memory module.

Matching resistors 1321, 1322a ...
1322d has the same configuration as the terminating resistors 1011a and 1011b described in the fifth embodiment (FIGS. 11 and 12).
However, the resistance value of the fixed resistor that constitutes the terminating resistor and the resistance value of the fixed resistor that constitutes the matching resistor are not the same value.

In the present embodiment, the resistance control circuit 13
Reference numeral 12 is a terminating resistor 1101a, 1101b and matching resistors 1321, 1322a to 1322d.
Although the resistors of various types are controlled, the control of the terminating resistor and the control of the matching resistor may be configured by independent control circuits.

The resistance value Rm of the matching resistor can be obtained using the following equation (Equation 8), where Zs is the characteristic impedance of the stub wiring and Z is the characteristic impedance of the bus wiring 1001.

Rm = Zs−Z / 2 (Equation 8) With the characteristic impedance of the stub wiring set to Zs = 60Ω, the characteristic impedance Ze1, Ze2, Z of the bus wiring for each connection state of the memory module obtained in the above embodiment.
By substituting e3 and Ze4 into Z in (Equation 8), the resistance value Rm of the matching resistor in each connection state
1, Rm2, Rm3, Rm4 can be obtained. Resistance values Rm1, Rm2, R of the matching resistors at this time
m3 and Rm4 are 38Ω, 41Ω, 44Ω, and 4 respectively.
It is 6Ω.

Further, fixed resistors 1101 and 1102 are provided.
a, 1102b and 1102c, the resistance value of
~ Equation 12) can be used.

Ro = Rm1 (Equation 9) Ra = Rm2-Rm1 (Equation 10) Rb = Rm3-Rm2 (Equation 11) Rc = Rm4-Rm3 ... (Equation 12) (However, Rm4>Rm3>Rm2> Rm1) From the resistance values Rm1, Rm2, Rm3, and Rm4 obtained above, the resistance values of the fixed resistors constituting the matching resistor are Ro = 38, Ra = 2, Rb = 3, and Rc =, respectively.
2.

As described above, according to this embodiment, the distortion of the signal waveform is reduced and the data transfer rate between the memory and the memory controller is reduced by keeping both the termination resistance and the matching resistance at optimum values. Can be raised.

Further, in the memory system using the SSTL bus, even if the effective impedance is lowered with respect to the characteristic impedance of the bus wiring due to the mounting of the memory module, the resistance value of the terminating resistor is adjusted to the effective impedance and further matching is performed. By setting the resistance value of the resistor to the optimum value, signal reflection and signal waveform distortion at each end of the bus wiring can be reduced, and the data transfer rate between the memory and memory controller can be increased. .

By using the configuration described in the second embodiment in the memory system using the SSTL bus, the characteristic impedance and load capacity of the memory module mounted on the back panel can be changed for each memory module. Even if they are different, the same effect can be obtained.

An outline will be described. An information storage device is provided in the memory module, the characteristic impedance of the memory module and the load capacity of the input / output circuit of the memory are stored in the information storage device, and the termination is performed based on this information. The resistance value of the resistor and the resistance value of the matching resistor connected to each memory may be set.

Further, by using the configuration described in the third embodiment in the memory system using the SSTL bus, the characteristic impedance and load capacity of the memory module mounted on the back panel can be changed for each memory module. Even if they are different, the same effect can be obtained.

In summary, a test bus wiring having the same structure as the original bus wiring is provided on the back panel, and a test input / output circuit is further provided on the memory module or the back panel. A test signal may be transmitted to the input terminal to set the resistance value of the terminating resistor and the resistance value of the matching resistor that allow the test signal to be transmitted between the input / output circuits.

[0165]

According to the present invention, even if the number and types of functional circuits connected to the bus wiring are changed, the terminating resistance is optimized according to the change.
The waveform distortion of the signal flowing through the bus is significantly reduced. Also,
If the waveform distortion of the signal can be suppressed, it is possible to provide a bus system capable of high-speed data transfer.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing an outline of a first embodiment of the present invention.

FIG. 2 is a configuration diagram of a termination variable resistor used in the first embodiment.

FIG. 3 is a configuration diagram showing an outline of a second embodiment of the present invention.

FIG. 4 is a configuration diagram of a terminating variable resistor used in the second embodiment.

FIG. 5 is a configuration diagram showing an outline of a third embodiment of the present invention.

FIG. 6 is a configuration diagram showing an outline of a fourth embodiment of the present invention.

FIG. 7 is a configuration diagram of a conventional bus system.

FIG. 8 is a configuration diagram of a test signal input / output circuit used in a third embodiment of the present invention.

FIG. 9 is an explanatory diagram related to a test method according to a third embodiment of the present invention.

FIG. 10 is a configuration diagram showing an outline of a fifth embodiment of the present invention.

FIG. 11 is a configuration diagram of a termination variable resistor used in a fifth embodiment.

FIG. 12 is a configuration diagram of a switch in a terminating variable resistor used in the fifth embodiment.

FIG. 13 is a configuration diagram showing an outline of a sixth embodiment of the present invention.

FIG. 14 is a configuration diagram of a terminating variable resistor used in the fifth embodiment.

[Explanation of symbols]

101, 1001 ... Bus wiring, 102, 1002 ... Back panel, 103a, 103b ... Circuit board, 104a, 104b, 1004a, 1004b, 100
4c, 1004d ... Connector, 105a, 105b, 106 ... Functional circuit, 107a, 107b, 1007a, 1007b, 100
7c, 1007d ... Detection circuit, 111a, 111b, 311a, 311b, 511a,
511b, 521a, 521b, 1011a, 1011
b ... Variable termination resistor, 112, 312, 512, 1012 ... Termination resistance control circuit, 201, 202, 203, 401, 402, 403, 4
22, 423, 424, 1101, 1102a, 110
2b, 1102c ... Resistors, 211, 212, 213, 402, 412, 413, 4
31, 432, 433, 434, 1112a, 1112
b, 1112c, 1401, 1402, 1403, 14
04 ... Switch, 220, 441, 442, 1141, 1441 ... Decode circuit, 301a, 301b ... Information storage circuit, 451 ... Coarse setting part, 452 ... Fine setting part, 501a, 501b, 502 ... Test signal input / output circuit, 520 ... Test bus wiring, 601, 602, 603, 604 ... CPU, 611, 612, 631, 632 ... Bus bridge, 621, 622 ... Main memory, 641, 642 ... RAID disk, 651, 652 ... Communication function module, 681 , 682 ... System bus, 691, 692 ... I / O bus, 1003a, 1003b, 1003c, 1003d ... Memory module, 1005a, 1005b, 1005c, 1005d ... Memory, 1006 ... Memory controller, 1021, 1022a, 1022b, 10 2c, 10
22d ... Matching resistor, 1201a, 1201b ... Field effect transistor, 1312 ... Resistance control circuit, 1321, 1322a, 1322b, 1322c, 13
22d ... Variable matching resistor

─────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor Atsushi Hara 1099 Ozenji, Aso-ku, Kawasaki-shi, Kanagawa Hitachi, Ltd. System Development Research Laboratory (72) Inventor Toshiro Takahashi 2326 Imai, Ome-shi, Tokyo Hiritsu Manufacturing Co., Ltd. In device development center (56) Reference JP-A-7-245543 (JP, A) JP-A-7-38580 (JP, A) JP-A-7-264218 (JP, A) JP-A-8-286793 (JP , A) JP-A-7-250104 (JP, A) JP-A-7-202947 (JP, A) JP-A-7-202620 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB) Name) G06F 3/00 H03H 7/38 H04L 12/40

Claims (8)

(57) [Claims] 1. A plurality of circuit boards and these circuit boards are inserted.
It is a bus system with a back panel that can be removed.
The back panel includes a data transmission bus line and a data transmission bus line.
A first terminating variable resistor connected to the end;
The test used to determine the resistance of the terminating variable resistor.
Test bus wiring and connected to the end of the test bus wiring
A second terminating variable resistor and the first terminating variable resistor
Value of resistor and resistance value of variable resistor for the second termination
And a control circuit capable of changing each of the above, and each of the circuit boards is connected to the test bus wiring according to an instruction from the control circuit.
Connect the output circuit that outputs the test signal and the test bus wiring
Receive the test signal output from the other circuit board via
And an input circuit for notifying the control result of the reception result.
The control circuit has a range in which the resistance value of the second terminating variable resistor can be changed.
The process of setting the value to one of the
Output a test signal to the output circuit provided in one of them
And the rest of the plurality of circuit boards
Obtain the test signal reception result from the input circuit provided
And the process of determining the reception state and the determination result
Corresponds to the resistance value of the terminating variable resistor in the management table
The process of registering, and the series of processes including
Repeat the procedure by changing the resistance value of the second variable resistor for termination.
No, as a result, for each resistance value registered in the management table
Registered in the management table based on the judgment result
From among the resistance values, the resistance value of the first variable resistor for termination.
And selecting the selected resistance value as the first termination variable resistor.
Resistance control type bus system characterized by being set in the
Tem. 2. A terminating resistance control type bus system according to claim 1.
And a bus system for connecting the bus wiring and the bus wiring to the bus wiring.
Impedance between the I / O circuit that inputs and outputs signals
SSTL (Stub Series Te with a matching resistor inserted)
rminate Logic) bus system
Termination resistance control type bus system. 3. A termination resistance controlled bus system according to claim 1.
And a bus system for connecting the bus wiring and the bus wiring to the bus wiring.
Impedance between the I / O circuit that inputs and outputs signals
SSTL (Stub Serie with a matching variable resistor inserted)
s Terminate Logic) bus system that controls the resistance value of the variable resistor for impedance matching.
Terminating resistor, which is further provided with a resistance control circuit
Anti-control bus system. 4. A termination resistance controlled bus system according to claim 3.
The impedance matching variable resistor is a field effect transistor.
Termination resistance control type bus characterized by being composed of transistors
system. 5. The terminating resistor according to claim 1, 2, 3 or 4.
In the control type bus system, the control circuit sets the resistance value of the first terminating variable resistor to
Reset the bus system after powering on the system.
After the transmission of the bus signal and the bus system is operating.
Data transfer waiting state
A terminating resistance control type bus system characterized in that 6. A terminating resistor according to claim 1, 2, 3 or 4.
In the control type bus system, the control circuit sets the resistance value of the first terminating variable resistor to
If the number of the circuit boards mounted on the
Termination resistance control characterized by having
Type bus system. 7. The method according to claim 1, 2, 3, 4, 5 or 6.
Characterized by having a terminating resistance controlled bus system
Computer. 8. The method according to claim 1, 2, 3, 4, 5 or 6.
Termination resistance control type bus system and through the bus system
And a redundant circuit connected in parallel with each other.
Fault-tolerant computer.