JP3434772B2 - DA converter - Google Patents

Description

Description BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a DA converter.
In particular, a DA converter using an R-2R ladder type ladder circuit
About inverter. 2. Description of the Related Art The most promising method for realizing a DA converter is described.
A typical circuit using an R-2R ladder circuit that is a typical circuit
Referring to FIG. 5, which shows a block diagram of a DA converter,
The first DA converter of the related art is an n-bit converter for DA conversion.
Captures and holds digital input signal DI
H) latch circuit 1, switches S1 to Sn and dummy
-Of the latched digital input signal having the switch Sd
Contact with the reference voltage VR corresponding to each bit level (value)
Switch signal corresponding to one of ground GND
a switch circuit 3 that outputs each of s1 to sn;
Ladder resistance R and resistance 2R
(Ladder) -connected switch signals s1 to sn
R-2R ladder that generates a conversion voltage VA corresponding to each of
-Type ladder circuit 4 and buffer-amplifies the converted voltage VA.
An output buffer 5 for outputting an analog voltage VO
You. The configuration of the ladder circuit 4 is the same as that of the switch circuit 3.
Referring to FIG. 3 which is shown only in a circuit diagram, the ladder circuit 4
The outputs of the switches S1, S2,..., Sn-1, Sn
Resistance 2R with one end connected to the input end
For the sake of clarity, two resistors having a resistance value R are connected in series).
Anti-R21, R22,... R2n-1, R2n and Dami
The resistor Rd, the resistors R21, R22,.
・ One end is connected to the other end of R2n-1 and the other end
The other end of the stage resistor Rn-1 is connected to the other end of the resistor R2n and the output buffer.
Resistors R1, R2, R3 connected to the input end of the
.. Rn-1. The switches S1 and S1 of the switch circuit 3
2,... Reference to the first input terminal of each of Sn-1, Sn
The voltage VR is connected to the ground GND at the second input terminal.
You. Note that the dummy switch Sd and the dummy
-The resistance Rd is such that the switches S1 to Sn are directly connected to the resistance R.
Because it is connected to the column, to ensure the specific accuracy
Is to be added to Next, referring to FIG. 5 and FIG.
The operation of the D / A converter will be described.
The switch S1 of the circuit 3 is connected to the first digital input signal DI.
Bit or least significant bit (least signific
cant bit: LSB), switches S2 to Sn
-1 are the second to (n-1) th bits of the digital input signal value.
The switch Sn is connected to the n-th bit of the digital input signal DI.
Or most significant bit (most significant)
nt bit: hereinafter each controlled by MSB)
You. When the input value of each bit is 0, the corresponding switch
The output is at the GND level. Conversely, when the input value is 1,
The output of the switch is at the VR level. Digital input input to latch circuit 1
The switches S1 to S1 according to the values of the LSB to MSB of the signal DI
The switch signals s1 to sn, which are the outputs of Sn, change.
A ladder circuit corresponding to the switch signals s1 to sn
4 outputs the converted voltage VA. The output buffer 5
The voltage VA is buffer-amplified and an analog voltage VO is output. As is known, a DA converter has n bits.
In the case of 2, ⁿ , For example, a 12-bit DA
2 for inverter ¹² = Resolution of 4096
Will be. Further, when the reference voltage VR is 5V, 5V /
4096 = 1.22 mV corresponds to 1 LSB. Toes
When the 12 bits of the digital input signal DI are all 0,
In this case, VO outputs 0V. Then, from the LSB side,
Output about 1.22mV every time the digital signal increases by 1.
The voltage VO rises and 12 bits of the digital input signal DI
When all the signals become 1, the output VO becomes 5V. One of the performances of a DA converter is output power.
Monotonicity of pressure is raised. Very simple explanation of monotonicity
Is added as the digital input signal DI increases.
Indicates that the output analog voltage VO increases monotonically.
You. An example of a conversion characteristic of a DA converter is shown in a graph.
Referring to FIG. 6 shown in FIG. 6, the ideal conversion characteristic is shown in FIG.
It is a 45-degree straight line as shown in the figure, but the actual one is enlarged
Then, the result is as shown in FIG. (B)
Although it is unavoidable in principle to have a step shape like this, digital
Output analog voltage VO in accordance with the increase of the input signal DI.
Increases monotonically, and this state is said to have monotonicity.
U. However, as shown in FIG.
Or it is inconvenient to have protrusions and is monotonic
Not really. [0010] In general, those using a ladder circuit are bit
The monotonicity may be lost when the number of
You. In particular, code switching with MSB carry / carry
The phenomenon is likely to appear in the part. The most monotonic
Switching to n-bit code, which is most likely to be lost
A point, ie, a carry / carry portion, and then (n-1)
Bit code, (n−2) bit code...
It is. The biggest cause is the semiconductor wafer (hereinafter referred to as
This is the relative accuracy of the resistance value of the resistor formed on the plate. Having a resistance value R to be manufactured on a semiconductor wafer
In practice, the resistor can accurately produce the absolute value of the resistance value R.
Is not possible, and the relative value of each resistor is
If it is, there is no problem. However, between adjacent resistors
Also have different resistance values, that is,
You. An example of a layout of resistors formed on a substrate is shown below.
Referring to FIG. 7 shown, the strip-shaped area shown in FIG.
.., Rn−
1 and resistors R21, R22, ..., R2n-1, R2n
Is equivalent to As is well known, this type of resistance is
A conductive film such as polysilicon of a predetermined conductivity is deposited on the
And the resistance value is set according to the width and length. However
In this type of conductive film formation process,
Slightly guided by directions such as near the center and periphery, or vertically and horizontally
It is known that the electric power varies. Therefore, if the number of resistors is small, for example,
By forming them collectively at the center of
It is possible to equalize the relative values of the resistance. But resistance
As the number of resistors increases, these resistors occupy a large area of the board.
Therefore, the above-mentioned variation factors have an effect. For example, to realize an 8-bit DA converter
Therefore, as described above, the resistance having the resistance value 2R is equal to the resistance value R.
, R7,... R7
, And 8 × 2 of resistors R21, R22,.
16 resistors and 2 dummy resistors Rd for a total of 25 resistors
is necessary. From experience, if this is about 25, the resistance value
The relative error of the
It is known to fit in the enclosure. However, for example, a 12-bit DA
In order to realize an inverter, resistors R1, R2,.
R11 and R21, R22,... R21
2 × 12 × 2 24 and dummy resistor Rd
37 resistors are required. Current semiconductor manufacturing process
At the technical level, the resistance values of these 37 resistors vary.
That is, the relative error is within the range where monotonicity can be secured.
It is extremely difficult to remove the
The dust spreads to a range where monotonicity cannot be secured. One
That is, despite the increase in digital input signals
Phenomenon that the output analog voltage VO decreases
Occurs. Due to the change of the carry / carry portion,
Patent No. 25800 for Solving the Problem of Monotonic Loss
13 and FIG. 4 of the conventional second DA converter.
Common components have common reference letters / numbers and
Referring to FIG. 8 shown by blocks, the conventional
The second DA converter is a conventional first DA converter.
, A switch circuit 3, and a ladder
In addition to the circuit 4 and the output buffer 5, a DA converter
Mask the digital input signal on the input side of
A mask circuit 101 for controlling the mask circuit.
Control circuit 102 and the most significant bit of the digital input signal.
And a detection circuit 103. Referring to FIG. 8, a conventional second DA converter
The operation of the data bit will be described first.
The output circuit 103 outputs the n-bit digital input signal DI.
Detects the most significant bit in which the first 1 on the most significant side is set,
It is supplied to the control circuit 102. The control circuit 102 includes a mask
The circuit 101 is controlled as follows. The mask circuit 101
M (m <n) bits continuous from the most significant bit
As it is, the remaining nm is up to the most significant bit
Is unchanged and the lower bit of the m bits is
The remaining bits nm-1 are all set to 0 or 1, and the DA conversion is performed.
To the conversion circuit. Thus, an n-bit digital input is provided.
Even if the consecutive m bits including the most significant bit are DA
And the lower bits of the m bits are truncated (or
By rounding up, the switch corresponding to these lower bits
Switch is fixed to 1 or 0, and simultaneous at carry / borrow
No longer switch to
And monotonicity can be guaranteed. However, this conventional second DA converter
The verters consist of the added mask circuit, mask control circuit and
The circuit scale of the upper significant bit detection circuit is large and the entire circuit
It is a factor of increasing the scale. For example, a 15-bit DA converter
In the case of the inverter, the most significant bit detection circuit uses two sets of 8 bits.
Encoders, 16 inverters, and 3 2-input
Requires a power NAND gate. 8-bit encoder
Have eight 2-input AND gates and one 8-input
Power NAND gate, four 4-input AND gates,
Two 2-input NAND gates and three 4-input NOR gates
And 12 inverters. Similarly, the mask circuit and its control circuit
This 8-input NAND gate and one 1-input to 7-input each N
AND gate, 1 inverter, 15 2 inputs
AND gate and two of almost the same size as the above encoder
And an 8-bit decoder. Note that the logic circuit operates as the number of inputs increases.
It goes without saying that the road scale becomes large. [0024] The above-mentioned first conventional technique is as follows.
The D / A converter operates in the lower voltage range of the output voltage range.
Even if only high resolution is required, a multi-bit DA
When using a barter, it loses its monotonicity and
Handling is very troublesome, and a small bit of D
Using the A-converter gives the required high resolution
There was a disadvantage that it was not. The conventional second DA which solves the above-mentioned drawbacks
The converter consists of an added mask circuit, mask control circuit and
And the most significant bit detection circuit
There was a drawback that this would increase the circuit scale. An object of the present invention is to provide a low output voltage range.
High resolution only in the voltage range and circuit scale
To provide a DA converter that suppresses the increase in
You. A DA converter according to a first invention is provided.
Data is a digital input signal of n (positive integer) bits.
Capture and hold and output the corresponding n-bit latch signal
Circuit, a resistor having a resistance value R and a resistor having a resistance value 2R
Are connected in the form of a ladder (ladder).
Switch that generates an analog voltage corresponding to each of the switch signals.
R-2R ladder type ladder circuit, and the latch signal
The ladder by supplying the switch signal according to the signal value
A D / A converter circuit with a switch circuit for switching circuits
Receiving the n-bit latch signal,
The most significant bit of the bit whose latch signal bit value is 1
The most significant bit that is
A predetermined integer m (a positive integer smaller than n)
Number) effective bit value and the most significant bit
If all the bit values 0 on the upper side of the
Both are lower-order bits of the m effective bits.
The values of the truncated bits are all set to a constant value of 0 or 1,
The switch is used as a switch control signal for controlling the switch circuit.
The lower bit control circuit that supplies the
Have been. Further, the lower bit control circuit is configured to
(N−m) bits including the most significant bit of the switch signal.
When the most significant bit is present in the
Most significant bit which is m bits lower than the most significant bit
Set the lower bits from the discarded bits to the truncated bits.
A circuit for setting a truncated bit may be provided. Further, the truncation of the lower bit control circuit
A bit setting circuit including a most significant bit of the latch signal.
Based on the value of each of the upper (nm) bit signals,
Lower (nm) bit including the least significant bit of the latch signal
Bit signal is set to the most significant bit.
May be provided. The DA converter according to the second invention has a 12 bit
Captures and holds the digital input signal of
A latch circuit that outputs a 2-bit latch signal and a resistance value
Connect the resistance of R and the resistance of 2R in a ladder (ladder) shape
Corresponding to each of the 12-bit switch signals.
12-bit R-2R ladder that generates analog voltage
Type ladder circuit and the switch according to the digital signal value.
Switch for supplying the switch signal to switch the ladder circuit
A D / A conversion circuit comprising:
And the bit value of this latch signal
Is the most significant bit of the bit whose is 1.
Bit from the most significant bit to the lower 8 bits.
The value of each of the significant bits of the bit and the most significant bit
If all higher bit values 0 are output as they are
It is a lower-order bit of the eight effective bits.
Assuming that the value of the truncation bit is a constant value of 0 or 1,
Switch control signal for controlling the switch circuit.
And a lower bit control circuit for supplying the
ing. The lower bit control circuit is configured to control the latch signal
The upper 4-bit signal including the most significant bit of the signal
When the upper significant bit is present, 8
Bits lower than the most significant truncated bits
Truncation bit setting to set the most significant bit to the above truncation bit
A constant circuit may be provided. Further, the truncated bit of the lower bit control circuit is
The bit setting circuit includes the most significant bit of the latch signal.
The latch signal based on the value of each
Any of the lower 4-bit signals including the least significant bit of
A plurality of logic circuits for setting one as the most significant truncated bit
May be provided. Further, the truncated bit setting circuit is provided
The 12th bit, which is the most significant bit of the latch signal, and below
Logical OR with the 11th bit of the digit and outputs the first OR signal
A first OR circuit to be activated, and a tenth bit of the latch signal.
And the ninth bit and the first OR signal.
A second OR circuit for outputting a second OR signal;
The OR of the fourth bit of the first signal and the first OR signal.
A third O which generates the fourth bit of the interlock switch control signal
R circuit, a third bit of the latch signal and the first O
The third OR of the switch control signal is calculated by taking the logical sum with the R signal.
A fourth OR circuit for generating a latch signal, and a fourth OR circuit for generating the latch signal.
The logical sum of 2 bits and the second OR signal is calculated, and
Fifth OR circuit for generating second bit of switch control signal
And a first bit of the latch signal and the second OR signal
And the first bit of the switch control signal
And a sixth OR circuit for generating. Next, an embodiment of the present invention will be described.
This will be described in detail with reference to the drawings. The DA converter of this embodiment has n (positive
Captures and holds a digital input signal of
Circuit for outputting a corresponding n-bit latch signal
Ladder (ladder)
Each of the n-bit switch signals.
N-bit R-2 for generating corresponding analog voltages
R ladder type ladder circuit and the front depending on the value of the latch signal
Switch that supplies the switch signal to switch the ladder circuit.
In a DA conversion circuit having a switch circuit, n bits
And the bit value of this latch signal
Is the most significant bit of the bit whose is 1.
Bit is detected, and the lower-order bit is
Valid m (positive integer less than n) bits
Bit value and all bits higher than the most significant bit
Output the value 0 as it is, and
All the values of the truncated bits that are the lower bits of the effective bit are set to 0.
Or a switch as a switch control signal with a constant value of 1
The lower bit control circuit that supplies the circuit
If the value of the input signal is m bits (digits) or more,
In addition to performing m-bit resolution operation for
When the value of the digital input signal is m bits or less, the original n bits
By performing operations equivalent to the resolution of
It is characterized by guaranteeing performance. Next, an embodiment of the present invention will be described with reference to FIG.
Components are identified by common reference letters / numbers and
With reference to FIG.
The state-of-the-art D / A converter is the same as the conventional first D / A converter.
N-bit digital input signal D to be subjected to common DA conversion
I is latched, and the corresponding n-bit latch is latched.
Latch circuit 1 for outputting switch signals l1-ln, and a switch
It has S1-Sn and dummy switch Sd, and is described later.
Bit levels of the switch control signals c1 to cn
Either reference voltage VR or ground GND corresponding to (value)
Each of the switch signals s1 to sn connected to one
The output switch circuit 3 and the resistance value R
Connect a resistor and a resistor with a resistance value of 2R in a ladder (ladder) shape
Conversions configured and corresponding to each of the switch signals s1 to sn
R-2R ladder type ladder circuit 4 for generating voltage VA
And amplifies the converted voltage VA with a buffer to convert the analog voltage VO
Output buffer 5 for output, plus n-bit latch
Receiving the signals l1 to ln and latching the signals l1 to ln
(N−m) bits (m is a positive integer less than n)
Each bit value of ln, ln-1,... ln-m + 1
, The lower (nm) bits ln-
m, ln-m-1,..., l1 are set as truncated bits
And the most significant bit of the bit whose bit value of the latch signal is 1
From the most significant bit lv, which is the bit of
The value of the defined effective bit, m bits, and the most significant bit
Output all bit values 0 higher than triv as they are
And the lower bits of the m effective bits.
Fixed all the values of the truncation bits to 0 or 1
The lower bits that output corresponding switch control signals c1 to cn
Control circuit 2. The structure of the lower bit control circuit 2 is shown in a circuit diagram.
Referring to FIG. 2, the lower bit control circuit 2
(Ln) bits ln,
According to each bit value of ln-1,... ln-m + 1
And the lower (nm) bits ln-m, l of the latch signal
.. to set nm-1,... l1 to the truncated bits
Bit setting circuit to be described later, comprising a plurality of OR gates
21. For convenience of explanation, the DA converter of the present embodiment
The data is n = 12, that is, a 12-bit DA converter.
And m = 8 bits. Therefore,
In the description, the latch signal ln is set to 112 and the switch control signal c
n is c12, (nm) is 4, switch Sn is S12,
And so on. Therefore, the truncated bit setting circuit 21
4 bits l12, l1 on the upper side of the H signals l1 to l12.
Latch signal according to each bit value of 1, l10, l9
The lower 4 bits l4, l3,... L1 of the
The logic of the latch signals l12 and l11
An OR gate G21 that sums and outputs an OR signal g1;
The logical sum of the latch signals 110 and 19 and the OR signal g1 is
An OR gate G22 for outputting an OR signal g2 and a latch
Switch control by taking the logical sum of signal l4 and OR signal g1
OR gate G23 for outputting signal c4, and latch signal l
3 and the OR signal g1 are ORed to obtain the switch control signal c.
3 and an OR gate G24 for outputting a latch signal
Performs a logical OR operation with the R signal g2 to output the switch control signal c2.
OR gate G25, latch signal 11 and OR signal
OR with g2 and output switch control signal c1
An OR gate G26. The configuration of the ladder circuit 4 is the same as that of the switch circuit 3.
Referring to FIG. 3 which is shown only in a circuit diagram, the ladder circuit 4
Controlled by each value of switch control signals c1 to c12
The outputs of the switches S1, S2,... S11, S12
Resistance 2R with one end connected to the input end
For the sake of clarity, two resistors having a resistance value R are connected in series).
R21, R22, ..., R211, R212 and Dami
The resistor Rd, the resistors R21, R22,.
The other end of R21, one end of which is connected to the other end
The other end of the resistor R11 is connected to the other end of the resistor R212 and the output buffer.
5, the resistors R1, R2,.
R11 is provided. The switches S1, S of the switch circuit 3
2,... Reference to the first input terminal of each of S11 and S12
The voltage VR is connected to the ground GND at the second input terminal.
When the value of each of the switch control signals c1 to c12 is 1,
If it is 0, select the reference voltage VR. If it is 0, select the ground GND.
The switch signals s1 to s12 are output. The dummy switch Sd and its connection
The switches S1 to S12 are connected to the dummy resistor Rd.
Is connected in series with the
It is added to maintain. The output buffer 5 has, for example, a feedback rate of 1
Comprising a voltage follower consisting of an operational amplifier
It is. Next, referring to FIG. 1, FIG. 2 and FIG.
The operation of the embodiment will be described.
1 receives the input 12-bit digital input signal DI.
And latches the corresponding latch signal l12
~ L1 is output. In the following description, for convenience of explanation,
Unless otherwise specified, all digital signals must be in the first bit or
Most significant bit (most significant bi)
t: MSB) to first bit or least significant bit (le
ast significant bit: LS
It shall be expressed in the order of B). Therefore, the latched
All bit values of the digital input signal DI are 0, that is, “0”.
000000000000 ", the latch circuit
1 holds this DI “00000000000000”,
In response to the supply of a predetermined read control clock (not shown),
Switch signals l1 to l12 "00000000000000"
It is supplied to the lower bit control circuit 2. The lower bit control circuit 2 receives the supplied
Since all bits of the switch signals l1 to l12 are 0,
Switch value "00000000000000" as it is
It is output as control signals c12 to c1. That is, the cut-off bit of the lower bit control circuit 2
The setting circuit 21 is configured to output the upper 8 bits of the latch signals 112 to 15.
Pass the bit value "00000000" of the bit as it is
Then, they are output as switch control signals c12 to c5.
In addition, all the inputs of the OR gates G21 and G22 are 0.
Therefore, the OR outputs g1 and g2 also become 0. OR game
G23-G26 also have their inputs all zero, so
Switch control signals c4 to c1 of lower 4 bits as output
Also becomes 0, and "0000" is output. The switches S12 to S1 of the switch circuit 3 are
The switch control signals MSBc12 to LSBc1
Each is controlled. Corresponds when the input value of each bit is 0
Switch output is GND (L) level, and conversely
When the input value is 1, the switch output is VR (H) level
It becomes. Therefore, the values of the switch control signals c12 to c1 are
"00000000000000", that is, all bits
0, the switches S12 to S1 output the switches.
The switch signals s12 to s1 are all at L level. The ladder circuit 4 receives the supplied switch signal.
In response to all L levels of signals s12 to s1,
Outputs analog conversion voltage VA and supplies it to output buffer 5
I do. The output buffer 5 stores the L-level conversion voltage VA.
Amplify the buffer and output the corresponding L-level analog voltage VO
Power. As described in the prior art, the DA converter
If the data is n bits, 2 ⁿ This implementation has a resolution of
2 in the case of a 12-bit DA converter of the form ¹² = 40
It has a resolution of 96. The reference voltage VR is set to 5V.
Then, 5V / 4096 = 1.22mV is equivalent to 1LSB
I do. That is, the 12-bit switch control signal c12 to
If all bits of c1 are 0, VO outputs 0V
You. Then, the digital signal increases by 1 from the LSB side.
Each time, the output voltage VO increases by about 1.22 mV,
Bit values of the switch control signals c12 to c1 are all 1
In this case, the output analog voltage VO becomes 5V. The digital input signal DI and the analog voltage
Referring to FIG. 4, which schematically illustrates the relationship,
Thus, the digital input signal DI is "00000000".
0000 ", the output signal VO becomes 0V (A
point). Next, the digital input signal DI changes to the twelfth
Bit value of bit to ninth bit is 0, bit 8 to bit 1
The bit value of the bit is 1, ie, “000011111”
1111 ". Output latch of the latch circuit 1
The signals 112 to 111 become "0000011111111".
(Point B). The number of times the lower bit control circuit 2 sets the cutoff bits
The path 21 is a high-order 8-bit video of the latch signals 112 to 15.
The switch value “00001111” as it is.
Output as the switch control signals c12 to c5. At the same time, O
The R gates G21 and G22 have 0
The R outputs g1 and g2 also become 0. On the other hand, OR gate G23,
G24 indicates that one of the input OR signals g1 is 0 but the other is
Since the latch signals l4 and l3 are 1, the switch control signal
1 is output as signals c4 and c3, respectively, and the OR gate G
25 and G26 have one input OR signal g2 of 0,
Since the other latch signals l2 and l1 are 1, the switch
Since 1 is output as each of the control signals c2 and c2,
Each bit of switch control signals c4 to c1 of lower 4 bits
The value becomes 1, and “1111” is output. Therefore, all
Switch control signals c12 to c1 are "000011111".
1111 ", which is the same as the latch signals 112 to 111.
One. At this time, the ladder circuit 4 has a 12-bit precision.
Conversion voltage corresponding to the case where all the lower 8 bits are 1
Outputs AV. That is, the analog voltage VO is 5.0
× 2 ⁸ / 2 ¹² = 312.5 mV. That is, the digital input signal DI, that is,
That is, the latch signals 112 to 111 are "000000000000".
Fields that change from 00 "to 000011111111"
In this case, the switch control signals c12 to c1
12 to 11 and the analog voltage VO during this period.
Is equivalent to the lowest latch signal 11, that is, one step
1/4096 × VR (= 1.22 m
V, represented by the thickness of the graph in the figure).
Therefore, it operates with 12-bit precision with 8 effective bits
I do. As described in the background art, the ladder circuit
4 is the required number of resistors for 8 bits, about 25
For example, the relative error of the resistance value,
It is possible to manufacture it within the range that can be maintained.
Therefore, monotonicity is sufficiently maintained in this output voltage range.
Can be done. Next, the ninth or digital input signal DI
The tenth bit, that is, the latch signal l9 or l10
The case of 1 will be described first.
The cut-off bit setting circuit 21 of the control circuit 2 includes an OR gate G2
Since 1 is input to one of the two input terminals, the OR signal
The number g2 becomes 1. Therefore, the OR gates G25, G2
6 is O regardless of the values of the corresponding latch signals l2 and l1.
The output switch control signals c2 and c1 are generated by the R signal g2.
Set to 1, that is, fixed to 1. So switch times
The switch signals s2 and s1 of the road switches S2 and S1 are H
The level is supplied to the ladder circuit 4. That is, the digital
Input signal DI from "00010000000000"
“001111111111” (VO = 1248.8 m
Up to V) (point C), the output analog voltage VO
8-bit operation in the range of latch signals 110 to 13
U. The lower two bits of the signal are ignored, and the
The pressure increase step width corresponds to one bit of the latch signal 13.
Corresponding to 1/1024 × VR (= 4.88 mV). Also in this case, the ladder circuit 4 has 8 bits.
Because only 25 resistors are used,
Monotonicity can be sufficiently maintained. Further, the twelfth digital input signal DI
(MSB) or the eleventh bit, that is, the latch signal l
The case where 12 or l11 is 1 will be described below.
The cut-off bit setting circuit 21 of the significant bit control circuit 2
1 is input to one of the input terminals of the gate G21.
Therefore, the OR signal g1 becomes 1. Therefore, the OR gate G
22, the output OR signal g2 becomes 1, and these OR signals g2
The lower 4 bits of the OR gate G2
Switch control signals c4 to c1 output from 3 to G26 correspond
Fixed to 1 irrespective of the values of the latch signals l4 to l1
It is. Therefore, the switches of the switches S4 to S1 of the switch circuit are switched.
Switch signals s4 to s1 supply the H level to the ladder circuit 4.
You. That is, when the digital input signal DI is "01000"
"00000000" to "111111111111"
(VO = 5000 mV) until the output analog voltage V
O is an 8-bit signal in the range of the corresponding latch signal 112 to 115.
Perform a reset operation. The lower 4 bits are ignored, so
The voltage increase step width during this time is equal to one voltage of the latch signal 15.
1/256 × VR (= 23.4 mV) corresponding to the cost
It becomes. Also in this case, the ladder circuit 4 has 8 bits.
Because only 25 resistors are used,
Monotonicity can be sufficiently maintained. The lower bit control circuit of the present embodiment
As described above, the truncated bit setting circuit 21 of 2
Consists of only five force OR gates and one 3-input OR gate
As a result, the increase in circuit scale can be minimized. As described above, the DA converter of the present invention
The converter converts the most significant bit of the n-bit latch signal
From the most significant bit to the lower m bits.
The value of the valid bit and all higher bits
Bit value 0 is output as it is, and m bits
The value of the truncated bit, which is the lower bit of the
Switch as a switch control signal with a constant value of 0 or 1.
A lower bit control circuit for supplying the
For example, a 12-bit D / A converter
By operating on bits, for example 8 bits,
12 bits in the low output voltage range corresponding to 8 bits
It is possible to obtain small increments of the corresponding high resolution.
There is an effect that. The upper (nm) bit signal is
Accordingly, the lower (nm) -bit switch control signal is
By controlling, it is possible to substantially guarantee monotonicity.
All digital inputs by limiting
There is an effect that monotonicity can be guaranteed for the signal value. Furthermore, the lower bit control circuit is
Since the circuit can be configured with only logic circuits,
This has the effect of requiring only a small amount.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of a DA converter according to the present invention. FIG. 2 is a circuit diagram showing a configuration of a lower bit control circuit of FIG. 1; FIG. 3 is a circuit diagram showing a configuration of a ladder circuit and a switch circuit of FIG. 1; FIG. 4 is a characteristic diagram schematically showing the relationship between a digital input signal and an analog voltage in the DA converter of the present embodiment in a graph. FIG. 5 is a block diagram illustrating an example of a conventional first DA converter. FIG. 6 is a characteristic diagram showing an example of a conversion characteristic of a DA converter in a graph. FIG. 7 is a layout diagram illustrating an example of a layout of resistors formed on a substrate. FIG. 8 is a block diagram showing an example of a second conventional DA converter. [Description of Signs] 1 Latch circuit 2 Lower bit control circuit 3 Switch circuit 4 Ladder circuit 5 Output buffer 21 Truncated bit setting circuits S1 to S12, Sn switch Sd Dummy switches G21 to G26 OR gates R1 to R11, Rn-1, R21 to R212, R2n
resistance

Claims (1)

(57) [Claim 1] A digital input signal of 12 bits is taken.
And the corresponding 12-bit latch signal.
Circuit for outputting a signal, a resistor having a resistance value R and a resistance value 2
The resistance of R is connected by connecting the resistance in the form of a ladder.
And the analog corresponding to each of the 12-bit switch signals.
12-bit R-2R ladder type ladder that generates
Circuit and a circuit corresponding to the 12-bit digital input signal value.
The ladder circuit by supplying the same switch signal.
A switch circuit for changing the state of the latch circuit,
Bit to set the truncation bit for the latch signal of
A setting circuit; and a switch of the switch circuit.
A lower bit control circuit for outputting a control signal,
The truncated bit setting circuit of the lower bit control circuit,
The twelfth bit which is the most significant bit of the signal from the latch circuit
OR the lower 11 bits with the first OR signal.
And a first OR circuit for outputting a signal from the latch circuit.
10th and 9th bits of the signal and the first OR
A second signal for ORing the signals and outputting a second OR signal
An OR circuit, and a fourth bit and a signal of the signal from the latch circuit.
And the logical sum of the first OR signal and the switch
A third OR circuit for generating a fourth bit signal of the circuit;
A third bit of the signal from the latch circuit and the first bit;
The OR of the OR signal is calculated, and the third bit of the switch circuit is calculated.
A fourth OR circuit for generating a reset signal;
Logic of the second bit of these signals and the second OR signal
Take the sum to generate a second bit signal for the switch circuit
A fifth OR circuit, and a first signal from the latch circuit.
OR the bit and the second OR signal,
Sixth OR operation for generating the first bit signal of the switch circuit
A DA converter comprising: a path ;