JP3431677B2 - Video printer - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video printer for producing a hard copy from a video signal, and more particularly to a video printer for preventing a defective image from being printed. 2. Description of the Related Art In a video printer for producing a hard copy from a video signal of the NTSC format or the like, an input terminal for inputting a video signal from a video camera or the like and an output terminal for outputting the video signal to a monitor are provided. Have. When a video signal is taken into the memory, when a freeze button of the video printer is pressed, a video signal of one screen is written to the memory as image data. When the screen switching button is pressed, the image data taken into the memory is sent to the monitor as a video signal, and the image is displayed. When the print button is pressed, the image data is read from the memory, and printing is performed in the printing unit. [0003] However, in the above-mentioned video printer, even when the power is turned on or when a disturbed image is stored in the memory, pressing the print button causes printing to be performed, and recording paper is wasted. It may be. In a video printer that does not have a monitor output terminal, there is a problem that recording paper is wasted due to test printing because it is only possible to confirm whether image data has been loaded into the memory without actually printing it. . [0004] The present invention has been made in view of the above problems, and has as its object to provide a video printer capable of preventing printing when a defective image is stored in a memory. [0005] In order to solve the above problems, a video printer according to the present invention comprises a synchronizing separation means for separating a synchronizing signal from a video signal, and whether or not the obtained synchronizing signal is normal. And a memory controller that clears the memory when the synchronization signal is not normal and generates a print prohibition signal. The synchronizing signal is separated from the video signal by the synchronizing signal separating means, and whether or not the synchronizing signal is normal is determined by the synchronization determining means. This synchronization determination means determines that the image is a defective image when the video signal is disturbed or when there is no video signal. For this defective image, the memory controller clears the memory and generates a print inhibit signal. When a normal image is loaded into the memory, the print inhibit signal is cleared. FIG. 2 shows an electric circuit of a video printer embodying the present invention. A video tape recorder, a video camera, a still video player, and the like are connected to the input terminal 2, and a video signal of a gradation image is transmitted to the selector 3, the analog signal processing circuit 4, and the synchronization separation circuit 5 via the input terminal 2. Is entered. The operation panel 7 is provided with a power button 10, a freeze button 11, a print button 12, and the like in addition to the screen switching button 8. In addition to the operation buttons, a display unit 13 on which various information is displayed by a liquid crystal or the like is provided. The selector 3 is provided with terminals 3a and 3b. When the terminal 3a is set to the terminal 3a side, the video signal from the input terminal 2 is sent directly to the monitor 9 via the selector 3, and the video signal is The moving image is displayed on the monitor 9. When the selector 3 is set to the terminal 3b side, the image data in the memory 15 is read, and
The image is displayed as a still image on the monitor 9 via the / A converter 16 and the analog signal processing circuit 17. In the image data fetched in the memory 15, a video signal from the input terminal 2 is separated into a red signal, a green signal, and a blue signal by the analog signal processing circuit 4, and A
It is digitized after being sampled for each pixel by the / D converter 18. Therefore, when outputting the image data in the memory 15 to the monitor 9, the D / A converter 1
6. The original video signal is converted via the analog signal processing circuit 17. The memory 15 is composed of three frame memories for red, green, and blue.
Under the control of 0, writing and reading of image data of each color are performed. The operation of loading the video signal into the memory 15 is performed by the freeze button 11 on the operation panel 7. When the freeze button 11 is operated, a write signal is sent to the memory controller 20 by the system controller 21, and the memory controller 20 outputs a video signal for one screen via the analog signal processing circuit 4 and the A / D converter 18. The image data is converted into image data and written into the memory 15. In printing, when the print button 12 is operated, a read signal is sent from the system controller 21 to the memory controller 20, and the memory controller 20 sends image data in the memory 15 to the print controller 23. The print controller 23 converts the red, green, and blue image data into three color image data of yellow, cyan, and magenta. Of the three color image data, only the color to be printed, eg, yellow image data, is extracted and sent to the head driver 24. The thermal head 26 includes a large number of heating elements 2.
6a are arranged in a line, and the head driver 24 selectively drives each heating element 26a according to image data, thereby thermally recording a yellow image line by line on a well-known color thermosensitive recording paper 27. . The color thermosensitive recording paper 27 is configured so that image data of three colors is sequentially thermal-recorded by using light fixing together to obtain a full-color image. The print controller 23 controls a motor 29 via a motor driver 28,
Drives the transport roller 30 to intermittently transport the color thermosensitive recording paper 27 line by line. The memory controller 20 has a print prohibition flag memory 32, and sets a print prohibition flag that has become "H" at the time of initialization immediately after power-on. When the freeze button 11 is operated while the print prohibition flag is set, the memory controller 20 clears the memory 15. When the print button 12 is operated, no printing is performed. The synchronizing separation circuit 5 separates a composite synchronizing signal (C.SYNC) from the input video signal, and further separates a vertical synchronizing signal (V.SYNC) and a horizontal synchronizing signal (H.SYNC) from the composite synchronizing signal. And separate. The horizontal synchronization signal is supplied to the analog signal processing circuits 4 and 17 and the A / D converter 1.
8 and the D / A converter 16 and are used as conversion processing timing. Further, an internal horizontal synchronization signal generator is provided in the synchronization separation circuit 5, and when the horizontal synchronization signal cannot be separated from the composite synchronization signal,
Outputs horizontal sync signal. The synchronization separation circuit 5 sends the composite synchronization signal, the vertical synchronization signal, and the horizontal synchronization signal to the synchronization determination circuit 34. As shown in FIG. 4, in a normal video signal,
The equalizing pulse before the vertical synchronizing period in the vertical blanking period and the cutting pulse in the vertical synchronizing period are regularly generated. However, in the case of a distorted video signal, the equalization pulse and the cutting pulse may be irregularly disturbed or may not be included. The synchronization determination circuit 34 of the present embodiment determines whether the video signal is normal by counting the number of synchronization signals that are disturbed by the defective video signal. As shown in FIG. 3, the synchronization determination circuit 34 includes an ENABLE signal generator 34a.
The ENABLE signal generator 34a includes D-FFs 36, 37, and 38 (D-type flip-flops) connected in three stages.
The horizontal synchronization signal is input as a clock signal to each of the CLK terminals, and the signal input to the D terminal is latched at the rise of the clock signal. A vertical synchronizing signal is input to the D terminal of the D-FF 36, and the Q terminal is connected to the D terminal of the D-FF 37 in the next stage. Further, the Q terminal of the D-FF 37 is connected to the D terminal of the D-FF 38 in the third stage. Furthermore, DF
The Q terminal of F36 and the INV-Q terminal of D-FF38 are connected to an AND circuit 39, respectively. AND circuit 3
9 is the Q terminal of the D-FF 36 and the INV-
The logical product of the signals input from the Q terminal is taken, and ENABL
An E signal is output to the ENABLE terminal of the pulse counter 40. This ENABLE signal is generated during the vertical synchronization period, and has a pulse width corresponding to 2H (two horizontal scanning periods). The pulse counter 40 counts the pulses of the composite synchronization signal input to the CLK terminal at the rising edge only when the signal input from the AND circuit 39 to the ENABLE terminal is at the H level. When the count value becomes “4”, an H-level signal is output from the Q terminal to the D terminal of the D-FF 41. A monostable multivibrator (hereinafter referred to as MM) 42 to which the vertical synchronizing signal is input generates a pulse having a width of 30 μs at the rise of the vertical synchronizing signal, and sends the pulse to the CLR terminal of the pulse counter 40. The pulse counter 40 has its counter value reset to “0” by the pulse from the MM 42. A signal output from the Q terminal of the pulse counter 40 is input to the D terminal of the D-FF 41. The signal input to the D terminal is latched at the rising edge of the vertical synchronization signal, and is output to the memory controller 20 from the Q terminal. The output of the H level signal from the Q terminal of the pulse counter 40 is due to the normal counting of the composite synchronization signal, which indicates that the video signal is normal without any disturbance. At this time, the signal output from the Q terminal of the D-FF 41 becomes H level, and the memory controller 20 determines that the synchronization error signal has not been generated. vice versa,
When the output of the Q terminal of the pulse counter 40 is at “L” level, it indicates that the composite synchronization signal is a disturbed video signal that cannot be counted. At this time, Q of D-FF41
The signal output from the terminal becomes the “L” level, and the memory controller 20 determines that a synchronization error signal has occurred. In the memory controller 20, the D-FF4
When the Q terminal of No. 1 is “L”, that is, when it is determined that the synchronization error signal is output, a print prohibition flag is written in the memory 32. And freeze button 1
1 is operated, "NO" is displayed on the display unit 13 of the operation panel 7.
"DATA" is displayed, and "0" or "FF" is written in the memory 15 to clear the contents. When the Q terminal of the D-FF 41 is “H”, that is, when it is determined that the synchronization error signal has not occurred, the print prohibition flag is reset by writing “0” to the print prohibition flag memory 32. When the print prohibition flag is not set, the operation of the freeze button 11 and the print button 12 can be executed. Next, in the above embodiment, the operation when a normal video signal without disturbance is input is shown in FIG.
This will be described with reference to FIG. When the power button 10 of the operation panel 7 is operated, the video printer operates. When the power is turned on, the system controller initializes the program ROM, various flags, and the like. For example, “1” is written in the print prohibition flag memory 32 of the memory controller 20, and the print prohibition flag is set. The video signal is input to the selector 3 by setting the video tape recorder connected to the input terminal 2 to the reproducing state. Since the selector 3 is set to the contact 3a side at the time of initialization, the video signal is sent directly to the monitor 9 via the selector 3 and displayed as a moving image. The video signal from the input terminal 2 is also input to the sync separation circuit 5. In the sync separation circuit 5, the composite sync signal, the horizontal sync signal and the vertical sync signal are separated from the video signal of the even field, and these sync signals are sent to the sync determination circuit 34. The horizontal sync signal is
The analog signal processing circuits 4 and 17 are input to the A / D converter 18 and the D / A converter 16 to perform control. In the vertical blanking period after the video signal of the even field, the synchronization determination circuit 34
Generates a 30 μs pulse at the rise of the vertical synchronization signal. This pulse is input to the CLR terminal of the pulse counter 40, resetting the pulse counter 40 to the count value "0", and setting the Q terminal of the pulse counter 40 to the L level. At the same time, the vertical synchronizing signal is also input to the D terminal of the D-FF 36, and the D terminal of the D-FF 36 becomes H level. At the next fall of the horizontal synchronizing signal, the Q terminal of the D-FF 36 goes to the H level, and the D terminal of the D-FF 38 remains at the L level, so that the INV-Q terminal maintains the H level. Is at H level. The pulse counter 40 can count since the ENABLE signal input to the ENABLE terminal becomes H level. Thereafter, the pulse counter 40 increments the count value Q at the rise of the cutting pulse included in the composite synchronization signal during the vertical synchronization period, and the count value becomes “4” at the rise of the fourth cutting pulse.
The Q terminal is set to the H level at the moment when it becomes. The count value of the pulse counter 40 is "0"
Between D-FF36, 37, and 3 until “4”
8 CLK terminal is input with two horizontal synchronizing signal pulses, and at the falling edge of the second pulse, DF
The Q terminal of F37 changes to H level. However, DF
The Q terminal of F36 and the INV-Q terminal of D-FF38 are H
Remains at the level. After the count value becomes “4”, the D-FF 38 outputs D-FF at the falling edge of the horizontal synchronization signal.
When the H-level signal output from the Q terminal of the FF 37 is latched, the signal at the INV-Q terminal becomes L level,
The NABLE signal becomes L level and the pulse counter 40
Stops counting. The D-FF 41 latches the H-level signal output from the Q terminal of the pulse counter 40 at the fall of the vertical synchronizing signal, so that the output of the Q terminal becomes H level. The signal output from the D-FF 41 is sent to the memory controller 20.
When it is 0, when it is at the H level, it is determined that the synchronization error signal has not been generated. Even if the vertical synchronizing signal ends, the pulse of the horizontal synchronizing signal continues to be applied to the CLK of the D-FFs 36, 37 and 38.
Although the signal is input to the terminal, the output of the AND circuit 39 does not change to the H level because the vertical synchronization signal is at the L level. Therefore, the pulse counter 40 does not count the equalizing pulse of the composite synchronization signal that is input thereafter. Following the vertical blanking period of the even field, various synchronization signals are separated from the video signal of the odd field and input to the synchronization determination circuit. However, the output signal of the D-FF 41 remains at the H level. In the vertical blanking period after the video signal of the odd field, a pulse of 30 μs is generated from the MM 42 at the rise of the vertical synchronizing signal, the count value of the pulse counter 40 is reset to “0”, and the Q The terminal goes to L level. Similarly to the vertical blanking period of the even field, the Q terminal of the D-FF 36 and the INV-Q
With this terminal, the ENABLE signal from the AND circuit 39 becomes H level, and the pulse counter 40 can count. The pulse counter 40 counts the cutting pulses included in the vertical synchronizing period of the composite synchronizing signal, sets the Q terminal of the pulse counter 40 to the H level at the moment when the count value becomes “4”, and sets the subsequent rise of the horizontal synchronizing signal. Stop counting on falling. The D-FF 41 latches the output from the Q terminal of the pulse counter 40 at the fall of the vertical synchronization signal, and the output from the Q terminal of the D-FF 41 is H
Since the level is maintained as it is, the memory controller 20
Then, it is determined that the synchronization error signal has not been generated. The above operation is repeated while the video signal is being input to the input terminal 2. The user looks for a moving image on the monitor 9 to search for a scene to be printed. When the scene is determined, the freeze button 11 on the operation panel 7 is operated. When the freeze button 11 is operated, the system controller 21 sends a write signal to the memory controller 20. The memory controller 20 that has received the write signal determines that the video signal being input is normal because the signal from the D-FF 41 is at the H level, and passes through the analog signal processing circuit 4 and the A / D converter 18. The converted image data for one color and one screen is written in the memory 15. Since the Q terminal of the D-FF 41 is "H" and no synchronization error signal is output, "0" is written in the print prohibition flag memory 32, and the print prohibition flag is reset. When the screen switching button 8 is operated after the video signal is fetched into the memory 15, the system controller 21 switches the selector 3 to the terminal 3 b and sends a read signal to the memory controller 20.
The memory controller 20 reads out the image data written in the memory 15 and sends it out to the monitor 9 via the D / A converter 16 and the analog signal processing circuit 17. Thus, the image data written in the memory 15 is displayed on the monitor 9 as a still image. After confirming the still image displayed on the monitor 9 as described above, the print button 12 is operated. When the print button 12 is operated, the system controller 21 sends a read signal to the memory controller 20 and a print start signal to the print controller 23.
Upon receiving the read signal, the memory controller 20 converts the red, green, and blue image data written in the memory 15 into one.
The print controller 23 reads the data alternately line by line.
To send to. The print controller 23 performs color and tone correction and color conversion into yellow, cyan, and magenta from the sent image data of each color for one line.
As for the converted image data of each color, only the yellow image data is sent to the head driver 24. Head driver 2
4 drives the thermal head 26 based on the yellow image data and thermally records one line of the yellow image on the yellow thermosensitive coloring layer of the color thermosensitive recording paper 27. At the same time, the print controller 23 drives the motor 29 via the motor driver 28, and the transport roller 30 intermittently transports the color thermosensitive recording paper 27 at a speed according to the thermal recording of the thermal head 26. Similarly, yellow images on the second and subsequent lines are thermally recorded, and ultraviolet rays of a predetermined wavelength are irradiated by a yellow ultraviolet lamp disposed downstream of the thermal head 26. As a result, the yellow thermosensitive coloring layer is light-fixed. After the thermal recording of the yellow image, when the color thermal recording paper makes one rotation and comes to the position of the thermal head 26 again, thermal recording of the magenta image is started. In the thermal recording of the magenta image, the magenta image is read line by line, and the thermal head 26 is read via the head driver 24.
Is driven to thermally record a magenta image line by line on the magenta thermosensitive coloring layer of the color thermosensitive recording paper 27. After the thermal recording of the magenta image, ultraviolet rays of a predetermined wavelength are irradiated by an ultraviolet lamp for magenta to fix the light. Finally, the cyan image is recorded on the color thermal recording paper 2
The thermal recording is performed line by line on the cyan thermosensitive coloring layer No. 7. No light fixing is performed on the cyan thermosensitive coloring layer.
After the thermal recording of the cyan image, the color thermal recording paper 27 is discharged. Next, a case where a video signal whose image is disturbed is input will be described. As shown in FIG. 5, the disturbed image does not include an equalizing pulse before the vertical synchronization signal in the vertical blanking period or a cutting pulse in the vertical synchronization period because the synchronization signal is irregularly disordered. As described above, when the freeze button 11 is operated, a video signal is written into the memory 15 as image data. On the other hand, in the synchronization determination circuit 34, a pulse of 3 μs is generated from the MM 42 at the rise of the vertical synchronization signal, and the count value of the pulse counter 40 is reset to “0”. While the vertical synchronizing signal is being generated, the ENABLE signal generating section 34a uses the horizontal synchronizing signal to generate a signal having a pulse width of 2H.
A NABLE signal is generated, and the pulse counter 40 can count. However, since there is no cutting pulse during this time, the count does not proceed and the Q terminal remains at the L level. In this state, when a vertical synchronizing signal is input, the D-FF 41 causes the pulse counter 4 to fall at its falling edge.
The L level signal output from the 0 Q terminal is latched. Therefore, the D-FF 41 outputs an L-level signal from the Q terminal, and the memory controller 20 that has received this signal determines that a synchronization error signal has occurred. When this synchronization error signal is output, "1" is written to the print prohibition flag memory 32 of the memory controller 20, and the print prohibition flag is set. Further, the memory controller 20 writes “0” into the memory 15 to clear the image data. Immediately after this, “NO DAT” is displayed on the display section 13 of the operation panel 7.
"A" is displayed to warn that there is no image to be printed. Even if the print button 12 is operated, printing is not performed because the print prohibition flag is set. Immediately after the power of the video printer is turned on, the memory 15 is cleared by initialization.
Since the print prohibition flag is set, printing is not performed even if the print button 12 is pressed. Although the above embodiment has been described with respect to a thermal recording type video printer, the present invention is not limited to this. For example, a thermal transfer recording type or ink jet type video printer may be used. Further, the present invention can be used not only for line printers but also for serial printers, page printers, and the like. In this embodiment, the case of the NTSC signal is described. SECA
The same processing can be performed for other TV signals such as the M system. As described above, in the video printer of the present invention, a normal image and a disturbed image are discriminated from the synchronization signal, and a print inhibit signal is generated for the disturbed image. Since the memory is cleared, useless printing can be prevented. Further, even a video printer without an output terminal to a monitor can perform printing only when normal data is present in the memory, so that useless printing such as test printing can be prevented.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a flowchart showing an operation of a video printer embodying the present invention. FIG. 2 is a schematic diagram of a video printer embodying the present invention. FIG. 3 is a circuit diagram of a synchronization determination circuit. FIG. 4 is a timing chart of a synchronization separation circuit and a synchronization determination circuit when a normal video signal is input. FIG. 5 is a timing chart of a synchronization separation circuit and a synchronization determination circuit when a disturbed video signal is input. [Description of Signs] 5 Synchronization separation circuit 15 Memory 20 Memory controller 21 System controller 23 Print controller 32 Print inhibition flag memory 34 Synchronization determination circuit

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-61-264871 (JP, A) JP-A-7-67071 (JP, A) JP-A-4-65263 (JP, A) JP-A-63-67 278853 (JP, A) JP-A-3-250976 (JP, A) JP-A-57-180282 (JP, A) JP-A 63-125471 (JP, U) (58) Fields investigated (Int. ⁷ , DB name) H04N 5/76-5/956

Claims (1)

(57) [Claim 1] In a video printer for capturing a video signal into a memory and creating a hard copy, a synchronization separation means for separating a synchronization signal from the video signal,
Notch included in the composite synchronization signal of the synchronization signal
A synchronization determination unit that determines whether the synchronization signal is normal by counting pulses; and a memory controller that clears a memory and generates a print inhibition signal when the synchronization signal is not normal. And a video printer.