JP3427814B2 - Receiver circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a receiving circuit, and more particularly to a receiving circuit for receiving an input data signal transmitted at the same time and a strobe signal for taking in the input data signal.

[0002]

2. Description of the Related Art There is a source clock transmission system for simultaneously transmitting a data signal and a strobe signal as timing information for capturing the data signal. In such a transmission system, there is a receiver circuit for capturing the data signal on the receiving side. A general example is shown in FIG. As shown in FIG. 7, the strobe signal STB is received by the receiving circuit SR, the received output is level-converted by the level converting circuit M9, and then the data latch M for data acquisition is made by using the clock distributing circuit M10.
81 to M8n are distributed and n parallel input data D1
~ Dn is latched.

Input data D1 to Dn are received circuits DR1 to DR1.
The signals received by DRn are received by the level conversion circuit M.
Level conversion is performed at 61 to M6n, and thereafter, delay processing is performed by delay circuits M71 to M7n for compensating the delay generated in the lock distribution circuit M10. Normally, the receiving receiver is a MOS transistor T1 as shown in FIG.
A well known static differential receiver circuit configuration consisting of ~ T5 is used.

[0004]

In the receiver circuit for reception shown in FIG. 8, when the input amplitude becomes small, the output amplitude becomes small, and the amplitude cannot be obtained sufficiently for the internal logic. Therefore, the receiver circuit shown in FIG. As described above, the level conversion circuits M61 to
M6n is required. The output level and amplitude of this differential receiver circuit fluctuate due to noise, and the delay of the level conversion circuit fluctuates, causing jitter. This jitter has a drawback that the setup / hold margins in the data fetch latches M81 to M8n are reduced.

It is an object of the present invention to provide a receiver circuit which does not reduce the setup / hold margin in the data acquisition latch even in small amplitude transmission.

[0006]

A data receiving circuit according to the present invention is a receiving circuit for receiving an input data signal transmitted at the same time and a strobe signal for taking in the input data signal, and an internal reference clock signal. A variable delay means for variably delaying the variable delay means, a delay amount control means for controlling the delay amount of the variable delay means in accordance with the phase difference between the delayed clock signal and the strobe signal, and an output timing of the variable delay means. look contains a data signal acquisition means for taking in the input data signal, to said input data signal
And the strobe signal has a frequency of 1/2,
The delay amount control means halves the delay clock signal.
Frequency dividing means for frequency division and the strobe according to the frequency division output.
The latch signal that latches the
According to the control information for generating the control information for controlling the delay amount.
Information generating means, and
If the strobe signals are shifted by about 1/2 cycle,
The frequency dividing means has a rising timing of the delayed clock signal.
It is characterized in that the frequency division is performed by the ring .

[0007]

Another receiving circuit according to the present invention transmits at the same time.
The incoming input data signal and this incoming data signal
It is a receiving circuit that receives a strobe signal for
Variable delay means for variably delaying the internal reference clock signal
And the position of this delayed clock signal and the strobe signal.
Delay for controlling the delay amount of the variable delay means according to the phase difference
Quantity control means and output timing of this variable delay means.
Data signal capturing means for capturing the input data signal
And the strobe with respect to the input data signal.
When the signal has a frequency of 1/2, the delay amount control means
The stage is a frequency dividing means for dividing the delayed clock signal by 1/2.
And latches the strobe signal according to this divided output
Latch means for controlling the delay amount according to the latch output.
Control information generating means for generating control information for controlling
However, the input data signal and the strobe signal are almost
In the case of the in-phase, the frequency dividing means outputs the delayed clock signal.
The special feature is that the frequency is divided at the falling timing.
It is a characteristic.

Further, the control information generating means is characterized in that the increase / decrease of the delay amount is controlled according to the level of the latch output, and the control information generating means has the first output level. When the level is a level, a counter that counts up in synchronization with the reference clock, and when the output level is a second level, has a counter that counts down in synchronization with the reference clock, and the counter output is used as the control information. And

The operation of the present invention will be described. In a transmission method that simultaneously transmits and receives a data signal and a strobe signal as a timing for capturing this signal, the phase difference between the variable delay output of the internal reference clock signal having the same frequency as the data signal and the strobe signal is detected. The variable delay amount of the reference clock signal is controlled according to the phase difference, and the data signal is latched at the timing of the delay-controlled clock signal. That is, the phase difference signal with respect to the data fetch timing is generated according to the phase difference between the strobe signal and the internal reference clock signal, and the data fetch timing is adjusted using this. For this reason, a latch type circuit can be used instead of the level conversion circuit as in the conventional case, so that there is no jitter generated when the level conversion of the strobe signal is performed,
It is possible to capture data with a very small amount of jitter that does not depend on the amplitude of the input signal, and it is possible to achieve higher speed by not using level conversion.

[0011]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an example of a receiving circuit according to the present invention. This receiving circuit is a latch type receiving circuit DR1 to D for receiving n parallel data signals.
Rn, a latch type receiving circuit SR for receiving the strobe signal STB, a frequency dividing circuit M1, and a counter circuit M2.
And a variable delay circuit M3.

In the receiving circuit SR for the strobe signal, the strobe signal STB is taken in at the timing of the strobe taking signal C2. The strobe take-in signal C2 is a signal obtained by dividing the data take-in signal C1 by the frequency dividing circuit M1. The data acquisition signal C1 is a signal obtained by adjusting the phase of the reference clock signal C0 (clock having the same frequency as the data signal) in the receiving circuit by the variable delay circuit M3. The count value of the counter circuit M2 is increased / decreased by the output of the reception circuit SR for the strobe signal, and the delay amount of the variable delay circuit M3 is adjusted / controlled according to the count value.

FIG. 2 is a diagram showing a detailed circuit of the strobe signal receiving circuit SR which is a component of FIG. The data signal receiving circuits DR1 to DRn have the same circuit configuration as the strobe signal receiving circuit SR. These data signal receiving circuits DR1 to DRn are connected to the data signal D1.
To Dn are latched and received at the timing of the data fetch signal C1.

This circuit has an input signal STB and a reference signal REF.
And a differential receiver M4 for comparing the differential receiver M4 with the differential output signals S3, S4 of the differential receiver as data input and C2 as a clock input, and an output S5 of the differential latch.
And a slave latch M6 for holding

The operation of this embodiment will be described below. As shown in the timing chart of FIG. 3, a case will be described in which the phases of the input data signals D1 to Dn and the strobe signal STB are shifted by a 1/2 cycle. The variable delay circuit M3 generates the data acquisition signal C1 whose phase is delayed from the reference clock signal C0 by the delay Δt. The data acquisition signal C1 is 2 at the positive edge by the frequency dividing circuit M2.
The frequency is divided, and the strobe capture signal C2 is generated.

Now, as shown in FIG. 3, in the strobe receiving circuit SR, the strobe signal S is generated at the positive edge of C2.
When the output signal S1 incorporating TB is at the L level, the output signal S2 of the counter circuit M2 increases, for example, by "1" in synchronization with the reference clock signal C0, and accordingly the delay Δt of the variable delay circuit M3 increases. Let Variable delay circuit M
When the delay Δt of 3 further increases and the output signal S1 that has captured the strobe signal STB at the positive edge of C2 becomes H level, the output signal S2 of the counter circuit M2 is synchronized with the reference clock signal C0 by “1”, for example. Then, the delay Δt of the variable delay circuit M3 is decreased.

By these series of operations, the positive edge of the data fetch signal C1 is controlled so as to always coincide with the positive edge of the strobe signal STR, and the data signals D1 to Dn can be fetched by C1.

Next, the strobe signal receiving circuit of FIG. 2 will be described with reference to the timing chart of FIG. MOS
Differential receiver M4 including transistors T6 to T10
Amplifies the potential difference between the input signal STB and the reference signal REF to generate differential output signals S3 and S4.

The differential latch M5 including the MOS transistors T11 to T20 is precharged when C2 is at L level, and the output signal S5 is at H level. When the potential of S3 is lower than the potential of S4, when C2 goes high,
S5 becomes L level. When the potential of S3 is higher than the potential of S4, C2 remains at H level. Differential latch M
The output S5 of 5 is held by the slave latch M6 and output to S1.

Another embodiment of the present invention is shown in FIG. 5, and the same parts as in FIG. 1 are designated by the same reference numerals. In this example,
The frequency dividing circuit M1 is configured to perform frequency division at the opposite edge of the data acquisition signal C1. As a result, as shown in the timing chart of FIG. 6, even if the input data signals D1 to Dn and the strobe signal STB are in phase with each other, the data signal can be captured by the data capture signal C1. Is obvious.

[0021]

As described above, when the receiving circuit according to the present invention is used, the timing information is converted into the digital information of the delay increase / decrease without using the level conversion circuit in the strobe receiving circuit. It becomes possible to capture data with a very small amount of jitter that does not depend on the level, amplitude, etc. of input data, as compared with the jitter that occurs when converting the level. Therefore, it is possible to obtain the effect of enabling high-speed transfer in small-amplitude transmission that requires level conversion.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a circuit diagram showing a partial specific example of the circuit of FIG.

FIG. 3 is a waveform diagram showing the operation of the block of FIG.

FIG. 4 is a waveform diagram showing the operation of the circuit of FIG.

FIG. 5 is a block diagram of another embodiment of the present invention.

6 is a waveform chart showing the operation of the circuit of FIG.

FIG. 7 is a block diagram showing a conventional example.

FIG. 8 is a circuit diagram showing a partial specific example of the circuit of FIG.

[Explanation of symbols]

DR1 to DRn data receiving circuit Receiver circuit for SR strobe signal M1 frequency divider M2 counter M3 variable delay circuit M4 differential receiver M5 differential latch M6 slave latch

Claims (5)

(57) [Claims] 1. A receiving circuit for receiving an input data signal transmitted at the same time and a strobe signal for taking in the input data signal, the variable delay means variably delaying an internal reference clock signal,
Delay amount control means for controlling the delay amount of the variable delay means according to the phase difference between the delayed clock signal and the strobe signal, and a data signal for taking in the input data signal according to the output timing of the variable delay means. and uptake means <br/> seen including, the strobe signal to the input data signal is 1 /
When the frequency is 2, the delay amount control means is
Frequency dividing means for dividing the delayed clock signal by 1/2, and
Latch for latching the strobe signal according to the frequency output
And a delay amount according to the latch output.
Control information generating means for generating control information , wherein the strobe signal is substantially equal to the input data signal.
If the frequency is shifted by ½ cycle, the frequency dividing means causes the delay
Divide at the rising edge of clock signal
The receiver circuit is characterized in that 2. An input data signal and a simultaneously transmitted data signal.
The strobe signal to capture the input data signal
A receiving circuit for receiving, a variable delay means for variably delaying an internal reference clock signal,
Phase difference between this delayed clock signal and the strobe signal
Delay amount control for controlling the delay amount of the variable delay means according to
Control means and the output timing of this variable delay means
Data signal receiving means for receiving the input data signal
And the strobe signal is 1 /
When the frequency is 2, the delay amount control means is
Frequency dividing means for dividing the delayed clock signal by 1/2, and
Latch for latching the strobe signal according to the frequency output
And a delay amount according to the latch output.
Control information generating means for generating control information, wherein the input data signal and the strobe signal have substantially the same phase.
In the case of, the frequency dividing means raises the delay clock signal.
The feature is that the frequency is divided at the falling timing.
The receiving circuit to do. 3. The control information generating means outputs the latch data.
To control the increase or decrease of the delay amount according to the level of force
The receiving circuit according to claim 1 , wherein the receiving circuit is formed. 4. An input data signal and a simultaneously transmitted data signal.
The strobe signal to capture the input data signal
A receiving circuit for receiving, a variable delay means for variably delaying an internal reference clock signal,
Phase difference between this delayed clock signal and the strobe signal
Delay amount control for controlling the delay amount of the variable delay means according to
Control means and the output timing of this variable delay means
Data signal receiving means for receiving the input data signal
And the strobe signal is 1 /
When the frequency is 2, the delay amount control means is
Frequency dividing means for dividing the delayed clock signal by 1/2, and
Latch for latching the strobe signal according to the frequency output
And a delay amount according to the latch output.
Control information generating means for generating control information, wherein the control information generating means responds to the level of the latch output.
The increase and decrease of the delay amount are controlled accordingly.
And the receiving circuit. 5. The control information generating means is configured to output the output level.
When the level is at the first level, the clock is synchronized with the reference clock.
Up, and when the output level is the second level,
Counting that counts down in synchronization with the reference clock
The counter output is used as the control information.
The receiving circuit according to claim 3 or 4, characterized in that: