JP3425896B2 - Method for manufacturing semiconductor device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a capacitor that constitutes a memory cell of a DRAM.

[0002]

2. Description of the Related Art In recent years, with the progress of manufacturing technology and equipment,
Attempts have been made to achieve high integration and miniaturization of semiconductor memory devices. Above all, DRAM (Dynamic Random Access Memory) is suitable for miniaturization because it has a simple structure in which one memory cell is composed of one transistor and one charge storage unit (capacitor). Memory devices are being developed and commercialized.

However, as the device becomes finer, the area of the capacitor becomes smaller, and therefore the capacity tends to become smaller. When the capacity stored in the memory cell becomes smaller, the amount of change given to the potential of the bit line when reading the charge stored in the capacitor becomes proportionally smaller, so the data read margin becomes smaller, and in the worst case, the The data will be read.

Therefore, it is necessary to increase the capacitance of the capacitor as much as possible even if the element is miniaturized. As one of the methods, a method of increasing the surface area of the electrode by changing the lower electrode structure of the cell capacitor from a simple two-dimensional structure to a three-dimensional structure is being studied.
Examples of the capacitor having a three-dimensional structure include a cylinder type and a fin type.

Here, as an example thereof, a method of manufacturing a cylinder type capacitor by a conventional method will be described with reference to FIGS. 1 and 4. FIG. 1 shows a general COB (Capacitor-
FIG. 3 is a plan view of a DRAM memory cell array portion having an Over-Bitline structure. As shown in FIG. 1, one memory cell includes one N-channel MOS transistor and one
It is composed of two charge storage parts (capacitors).

A plurality of word lines 4 and bit lines 6 are arranged on the main surface of the p-type silicon substrate 1 so as to be orthogonal to each other. The n-type diffusion layer region 2 is formed at a predetermined interval in the direction orthogonal to the word line 4.

The n-type diffusion layer region 2 is electrically isolated from each other by an element isolation insulating film 3.

The bit line 6 is connected to the n-type diffusion layer region 2 via the bit contact 5. The lower electrode 8 of the capacitor is connected to the n-type diffusion layer region 2 via the capacitive contact 7. Although not shown, the upper electrode of the capacitor is arranged so as to cover the entire memory cell array portion.

FIGS. 4A to 4E are sectional views of a portion corresponding to the line AA in FIG. 1, showing the manufacturing steps by the conventional method in order. FIG. 4A shows a p-type silicon substrate 1.
After forming the element isolation insulating film 3 by a known method, and then forming the n-type diffusion region 2 and the word line 4, the bit contact 5 and the bit line 6 are formed through the first interlayer insulating film (oxide film) 9. And a nitride film 11 serving as a wet etching stop layer in the manufacture of the cylinder type capacitor is further deposited on the second interlayer insulating film (oxide film) 10 by 100 nm, for example.

Next, as shown in FIG. 4B, in order to form the capacitive contact 7, first, a photoresist is applied (not shown), exposed and developed, and using this as a mask, n-type diffusion is performed. Anisotropic dry etching is carried out until the layer region 2 is exposed, after which the photoresist is stripped.

In FIG. 4C, next, an oxide film sidewall 13 is formed on the inner wall of the capacitor contact 7 in order to prevent a short circuit between the capacitor contact 7 and the word line 4 or the bit line 6.

As the forming method, first, an oxide film is deposited to a thickness of 50 nm on the entire surface of the wafer by the LPCVD method which enables conformal film formation.

Then, anisotropic dry etching is performed until the n-type diffusion layer region 2 at the bottom of the capacitor contact 7 is exposed to obtain a structure shown in FIG. 4 (c).

In FIG. 4D, next, phosphorus-doped polysilicon 14 is deposited to a thickness of 500 nm across the capacitor contact 7 and a part of the nitride film 11, the capacitor contact 7 is buried, and the surface is flattened. Etch back to 400 nm.

The remaining 100 nm layer of phosphorus-doped polysilicon 14 becomes the bottom of the lower electrode of the cylinder type capacitor. Further, 800 nm of BPSG 15 which will be a core oxide film for forming a cylinder type capacitor is deposited on the phosphorus-doped polysilicon 14 forming region, a photoresist is deposited (not shown), exposed and developed, and then masked. Then, the BPSG 15 and the phosphorus-doped polysilicon 14 are sequentially anisotropically dry-etched to obtain the structure shown in FIG.

Next, phosphorus-doped polysilicon 50 is added again.
After being deposited on the entire surface of the wafer, the nitride film 11 is etched back until it is exposed to form phosphorus-doped polysilicon sidewalls 16 around the core BPSG 15.

After that, the oxide film is wet-etched by using diluted hydrofluoric acid to completely remove the core BPSG 15. As a result, the lower electrode structure of the cylinder type capacitor shown in FIG. 4E is obtained.

Here, the nitride film 11 under the phosphorus-doped polysilicon 14 and the phosphorus-doped polysilicon sidewall 16 functions as a stop layer for wet etching, and prevents a short circuit with the underlying wiring and a collapse of the cylinder type capacitor. .

[0019]

However, the conventional method of manufacturing a cylinder type capacitor has the following problems. This problem will be described with reference to FIG.

In FIG. 4C, when the oxide film side wall 13 for preventing short circuit is deposited on the capacitor contact 7 opened in the second interlayer film 10, the stress is caused in the nitride film 11 which is the wet etching stop layer. As a result, when the oxide film is deposited, a wafer crack 17 is generated from the opening of the capacitor contact 7, which causes a problem that the yield and reliability of products are reduced.

The present invention has been made to solve such a problem, and by relaxing the stress of the nitride film which will be the wet etching stop layer, wafer cracking due to the stress can be prevented, and the yield and yield can be improved. The purpose is to suppress the deterioration of reliability.

[0022]

In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention is a method of manufacturing a semiconductor device having a stress relaxation treatment, wherein the semiconductor device is a DRAM, and charge storage is performed. and use the lower electrode, main
An oxide film is used as an interlayer film between the n-type diffusion layer region of the memory cell transistor, and a nitride film serving as a wet etching stop layer is laminated on the interlayer film. After the contact that connects the lower electrode for charge storage and the diffusion layer region is opened, it is a process of performing ion implantation into the nitride film that will be the wet etching stop layer. Injecting n- type impurities into the n-type diffusion layer region
It also serves as a process for entering .

In addition, in the process of performing the ion implantation,
The ion species to be implanted is an element that becomes an n-type impurity.
And phosphorus, arsenic, or antimony .

[0024]

[0025]

[0026]

[0027]

[0028]

[0029]

[0030]

BEST MODE FOR CARRYING OUT THE INVENTION The method for manufacturing a semiconductor device according to the present invention includes stress relaxation treatment. The semiconductor device has a nitride film that serves as a wet etching stop layer, and the stress relaxation process is a process of implanting ions into the nitride film that serves as a wet etching stop layer.

The present invention is intended to prevent wafer cracking due to the stress of the nitride film serving as the wet etching stop layer in the manufacturing process of a semiconductor device, particularly a cylinder type capacitor, before the capacitance contact opening or at the capacitance contact opening. By implanting ions into the nitride film later, the stress of the nitride film is relaxed, and the yield and reliability of the product due to wafer cracking are suppressed.

The basic structure of the method for manufacturing a semiconductor device according to the present invention will be described below with reference to FIGS. 1 and 2 .
FIG. 1 shows a general COB (Capacitor-Ove).
It is a top view of the DREM memory cell array part of r-Bitline) structure.

In FIG. 1, one memory cell is composed of one N-channel MOS transistor and one charge storage portion (capacitor).

A plurality of word lines 4 and bit lines 6 are arranged on the main surface of the p-type silicon substrate 1 so as to be orthogonal to each other. The n-type diffusion layer region 2 is formed at a predetermined interval in the direction orthogonal to the word line 4, and the element isolation insulating film 3 is formed.
Are electrically isolated from each other.

The bit line 6 is connected to the n-type diffusion layer region 2 via the bit contact 5. The lower electrode 8 of the capacitor is connected to the n-type diffusion layer region 2 via the capacitive contact 7.
Connected with.

The upper electrode of the capacitor is arranged so as to cover the entire memory cell array portion (not shown in the figure).

FIGS. 2A to 2E are process sectional views taken along the line AA of FIG. 2A, after forming the element isolation insulating film 3 and the word line 4 by a known method, the bit contact 5 and the bit line 6 are formed through the first interlayer insulating film (oxide film) 9, and further, This is obtained by depositing, for example, 100 nm of a nitride film 11, which will be a wet etching stop layer in the manufacture of the cylinder type capacitor, on the second interlayer insulating film (oxide film) 10.

Here, in order to relax the stress of the nitride film 11, a stress relaxation process is performed. The stress relaxation treatment is a treatment in which the ion implantation 12 is performed on the entire surface of the wafer (the nitride film 11 and the planned surface where the capacitive contact 7 is to be opened).

[0039] The ion species to be implanted include nitrogen, argon, fluorine, silicon, may be an inactive element such as germanium, phosphorus, arsenic, n such antimony
It may be a type impurity or an element which becomes a P-type impurity such as mother theory, indium, gallium, and aluminum. Alternatively, these elements may be used in combination.

The implantation energy varies depending on the ion species to be implanted, but it is most preferable that the range of the ions is at the center of the nitride film. When the nitride film thickness is 100 nm and the implanted impurity is phosphorus. , 70 keV.

The implantation dose is 1E12 to 1E16 cm.
^In the range of ^-2, about 3E15 cm ^-2 is preferable. When the elements are used in combination, it is preferable to add them together so that the elements fall within the above range.

Next, as shown in FIG. 2B, in order to open the capacitor contact 7, a photoresist is applied (not shown), exposed and developed, and anisotropic dry etching is diffused using this as a mask. The photoresist is stripped until the layer area is exposed.

Next, in FIG. 2C, oxide film sidewalls 13 are formed in advance in order to prevent a short circuit between the capacitor contact 7 and the word line 6 or the bit line 6. As a method of forming the oxide film side wall 13, first, an oxide film is deposited to a thickness of 50 nm on the entire surface of the wafer by the LPCVD method which enables conformal film formation.

Then, anisotropic dry etching is performed until the n-type diffusion layer region 2 at the bottom of the capacitor contact 7 is exposed to obtain the structure shown in FIG. 2 (c). LP
Wafer cracking does not occur because the stress of the nitride film is relaxed before the CVD oxide film is deposited.

In FIG. 2D, next, phosphorus-doped polysilicon 14 is deposited to a thickness of 500 nm, the capacitor contact 7 is buried, and 400 nm is etched back for flattening the same.

The remaining 100 nm of phosphorus-doped polysilicon 14 becomes the bottom part of the lower electrode of the cylinder type capacitor. Further, after depositing 800 nm of BPSG15 which will be a core oxide film in forming a cylinder type capacitor,
After depositing a photoresist (not shown), exposing and developing, BPSG15, phosphorus-doped polysilicon 1 with this as a mask
4 is sequentially anisotropically dry-etched to obtain the structure shown in FIG.

Next, phosphorus-doped polysilicon 16 is deposited again on the entire surface of the 50 nm wafer, and is etched back until the nitride film 11 is exposed to form phosphorus-doped polysilicon sidewalls 16 around the core BPSG 15. .

After that, the oxide film is wet-etched using diluted hydrofluoric acid to completely remove the core BPSG 15. As a result, the lower electrode structure of the cylinder type capacitor shown in FIG. 2E is obtained.

Here, the nitride film 11 under the phosphorus-doped polysilicon 14 and the phosphorus-doped polysilicon sidewall 16 functions as a stop layer for wet etching, and prevents a short circuit with the underlying wiring and a collapse of the cylinder type capacitor. .

According to the above structure , the stress relaxation treatment is performed before the LCVD oxide film deposition and the stress of the nitride film is relaxed by the ion implantation, so that the wafer cracking due to the stress of the nitride film does not occur during the oxide film deposition. Ayumu Thomas Rino improvement and
It can be expected to secure reliability.

Next, an embodiment of the present invention will be described with reference to FIGS. 3A to 3E are also shown in FIG.
2 is a process cross-sectional view taken along the line AA of FIG. Unless otherwise specified , the same components as in Fig. 2
Will be described using the same reference numerals as those used in FIG.

In FIG. 3A, after the element isolation insulating film 3 and the word line 4 are formed by a known method, the bit contact 5 and the bit line 6 are formed through the first interlayer insulating film (oxide film) 9.
Is formed, and further on the second interlayer insulating film (oxide film) 10,
It is obtained by depositing, for example, 100 nm of the nitride film 11 that will be the wet etching stop layer in the manufacture of the cylinder type capacitor.

Next, as shown in FIG. 3B, in order to form the capacitor contact 7, a photoresist is applied (not shown), exposed and developed, and anisotropic dry etching is performed using this as a mask. This is performed until the mold diffusion layer region 2 is exposed, and the photoresist is peeled off.

Here, in order to relax the stress of the nitride film 11, the whole surface of the wafer (the nitride film 11 and the capacitor contact 7 is
Ion implantation 12 is performed as a stress relaxation treatment in the opening (1).

In this embodiment, the ion species to be implanted may be an inert element such as nitrogen or argon, or an element such as phosphorus, arsenic or antimony which becomes an n-type impurity. Alternatively, these elements may be used in combination.

Although the implantation energy changes depending on the type of ions to be implanted, it is most preferable from the viewpoint of stress relaxation that the range of the ions is located at the center of the nitride film.
When the nitride film thickness is 100 nm and the impurity to be implanted is phosphorus, it becomes 70 keV.

Since the ion implantation performed here also serves as the implantation for forming the diffusion layer under the capacitor contact, the implantation may be performed according to the required diffusion layer depth.

The implantation dose is 1E12 to 1E16 cm.
^The implantation is performed in the range of ^-2 , preferably about 1E13 cm-2. When the elements are used in combination, it is preferable to add them together so that the elements fall within the above range.

Next, in order to prevent a short circuit between the capacitive contact 7 and the word line 4 or the bit line 6, an oxide film side wall 13 is formed. As the forming method, first, an oxide film is deposited to a thickness of 50 nm on the entire surface of the wafer by the LPCVD method which enables conformal film formation.

Then, anisotropic dry etching is performed until the diffusion layer region at the bottom of the capacitance contact is exposed to obtain a structure shown in FIG. Also in the second embodiment, the nitride film 11 is formed before the LPCVD oxide film 13 is deposited.
Since the stress is relaxed, wafer cracking does not occur.

Then, as shown in FIGS. 3D and 3E, phosphorus-doped polysilicon 14 is deposited to a thickness of 500 nm,
400 nm for embedding the capacitor contact 7 and planarizing
Etching back is performed, and BPSG15 to be a core oxide film is deposited to 800 nm to form a cylinder type capacitor.

After that, a photoresist is deposited (not shown), exposed and developed, and then BPSG 15 and phosphorus-doped polysilicon are sequentially anisotropically dry-etched using this as a mask to deposit phosphorus-doped polysilicon 16 on the entire surface of the 50 nm wafer. Then, this is etched back until the nitride film 11 is exposed to form a phosphorus-doped polysilicon sidewall 16 around the core BPSG 15.

After that, the oxide film is wet-etched using diluted hydrofluoric acid to completely remove the core BPSG 15 to obtain the lower electrode structure of the cylinder type capacitor. The procedure of the process shown in FIGS. 3D and 3E is the same as that of the previous embodiment.

In this embodiment, as the stress relaxation treatment of the nitride film, both ion implantation and ion implantation for forming a diffusion layer in the capacitor contact opening can be performed, so that wafer cracking can be performed without increasing the number of steps. It is possible to prevent the accompanying reduction in yield and reliability.

[0065]

According to the present invention, in a semiconductor device, particularly in the manufacture of a cylinder type capacitor, as a stress relaxation treatment, ions are implanted into a nitride film which is a wet etching stop layer to form a nitride film which is a wet etching stop layer. Since the stress is relieved, it is possible to prevent the wafer from cracking due to the stress, and thus it is possible to suppress the reduction in yield and reliability.

Further, by using an n-type impurity such as phosphorus, arsenic, or antimony as an element for ion implantation, it can also serve as ion implantation for forming a diffusion layer under the capacitor contact, and the nitride film can be formed without increasing the number of steps. The stress of can be relaxed.

[Brief description of drawings]

FIG. 1 is a general COB (Capacitor-Ove).
FIG. 6 is a plan view of a DRAM memory cell array portion having an r-bitline) structure.

2A to 2E are cross-sectional views of a portion corresponding to line AA in FIG. 1, showing the first embodiment according to the present invention in process order.

3A to 3C are cross-sectional views of a portion corresponding to the line AA in FIG. 1, showing a part of the second embodiment according to the present invention in the order of steps.

4 (a) to 4 (e) are cross-sectional views of a portion corresponding to the line AA in FIG. 1, and are views sequentially showing manufacturing steps by a conventional method.

[Explanation of symbols]

1 p-type silicon substrate 2 n-type diffusion layer region 3 Insulation film for element isolation 4 word lines 5 bit contact 6 bit line 7 capacity contacts 8 Lower electrode 9 First interlayer insulating film (oxide film) 10 Second interlayer insulating film (oxide film) 11 Nitride film 12 Ion implantation 13 Oxide film sidewall 14, 16 Phosphorus-doped polysilicon 15 core BPSG 16 phosphorus-doped silicon sidewall

Claims (2)

(57) [Claims] 1. A method of manufacturing a semiconductor device having a stress relaxation treatment, wherein the semiconductor device is a DRAM, and a lower electrode for charge storage,
An oxide film is used as an interlayer film between the memory cell transistor and the n-type diffusion layer region, and a nitride film serving as a wet etching stop layer is laminated on the interlayer film. After opening the contact connecting the lower electrode for charge storage and the diffusion layer region, it is a process of implanting ions into the nitride film which will be the wet etching stop layer. A method of manufacturing a semiconductor device, which also serves as a process of implanting an n-type impurity into the n-type diffusion layer region. 2. The semiconductor device according to claim 1, wherein in the process of performing the ion implantation, the ion species to be implanted is one of phosphorus, arsenic, and antimony as an element that becomes an n-type impurity. Manufacturing method.