JP3424200B2 - Bit line forming method for memory cell / capacitor array - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor memory device, and more particularly to a method for forming a bit line of a memory cell / capacitor array of DRAM.

[0002]

BACKGROUND OF THE INVENTION Very large integrated circuit technology (VLSI) has significantly increased the circuit density of chips. Fine elements constructed on and in a semiconductor substrate form circuits, and very finely separate the circuits, and the integration density thereof has also become remarkably large. Recently, for example, the circuit density has been improved by the progress of photolithography technology such as phase shift mask and the progress of self-alignment process, and further the scale down of semiconductor devices. With these developments, in ultra-large integrated circuits (ULSI), it has become possible to integrate more than one million transistors on a single chip with a minimum device scale of 1 μm or less. The circuit device manufactured by such an advanced manufacturing process faces a problem of limitation in electrical characteristics due to its scale down.

A memory cell array on a dynamic random access memory chip can be used as a circuit element facing such a limit of electrical characteristics. Generally, one metal / oxide / semiconductor field-effect transistor constitutes a single memory cell of a DRAM, which is widely used in the electronic industry for storing data. The single memory cell of DRAM is
1-bit data is stored in a capacitor in the form of electric charge. The reduction of the memory cell capacity due to the reduction of the memory cell area has been a major obstacle to further improving the integration density of DRAM. Therefore, the integration density of the semiconductor memory device can be increased only after solving the problem of the decrease in the memory cell capacity. The problem of reduced memory cell capacity not only lowers the data read capability, but also increases the soft error rate of the memory cell and causes the situation that power consumption over occurs during the low voltage operation period due to the action of the resistance element. It was.

Normally, the memory cell area is about 1.5 μm ²
In a 64 MB DRAM which adopts the well-known two-dimensional stacked capacitor cell structure, even if a material having a high dielectric constant such as tantalum pentoxide (Ta ₂ O ₅ ) is used, a sufficient memory cell capacitance value can be obtained. I couldn't get it. Therefore, it has been proposed to increase the capacitance value of the memory cell by the stacked capacitance having a three-dimensional structure. Such stacked capacitors include, for example, double stacked capacitors, blade-shaped capacitors, pillar-shaped capacitors, distributed stacked capacitors, and box-shaped capacitors.

Prior art DRAM capacitor array structures have employed either embedded or non-embedded bit lines. When the embedded bit line structure is used, the bit line configuration is such that the bit line of the memory cell field effect transistor (FET) and the contact hole are vertically close to each other, and the memory cell capacitor is horizontal and the word line and the bit It was formed above the line.
When the non-embedded bit line structure is used, the deep vertical contact hole penetrates the thick insulating film and the memory cell FE.
Formed by reaching T, the capacitor was located above the word line and below the bit line. Such a non-embedded bit line structure is also referred to as a "bit line below capacitor" or "capacitor above bit line" structure, which is also the subject of this invention.

[0006]

The following US patents include:
Related manufacturing processes as well as bit line structures are disclosed. That is, Lage US Pat. No. 5,389,56
6, Choi et al., US Pat. No. 5,422,295, De
nnison U.S. Pat. No. 5,401,681. However, utilizing fewer optics and etching steps can improve such prior art manufacturing processes. Many of the prior art manufacturing processes have had to employ steps and / or planar structures that make the manufacturing process complicated and costly. Since other manufacturing methods also had to control the progress of etching to a predetermined etching depth, it was extremely difficult to perform such control in semiconductor manufacturing. Then, when the bit line contact hole is opened, a relatively large process error must be taken into consideration to prevent a short circuit between the bit line contact and the word line or the capacitor electrode. Here, there is a problem that the device cannot be downsized unless the memory cell is downsized.

Therefore, it is an object of the present invention to develop a method of forming a capacitor and a bit line which minimizes such manufacturing cost and maximizes the yield of semiconductor devices. In particular, it is a problem to be solved by the present invention to reduce the photoresist and photomask steps to the minimum and to maximize the manufacturing error tolerance to obtain the highest yield.

It is an object of the present invention to provide a method of forming a bit line contact hole which can reduce the optical and etching steps.

Another object of the present invention is to reduce the complexity of the manufacturing process and increase the tolerance of process error to avoid shorting the bit line to the word line and the electrode plate. To provide a method of forming a "line".

Yet another object of the present invention is to use only three layers of polysilicon film as well as high density bit lines,
A dynamic random access memory (DRA) that is easy to manufacture, has a low manufacturing cost, and has improved yield.
It is to provide a manufacturing method of M).

[0011]

In order to solve the above problems and achieve the above object, the present invention provides a method for forming a bit line of a memory device having a high density.
As shown in FIG. 1 to FIG.
The drain region 8 is formed between the two separated transfer gates 14 and 18, and the first insulating films 20 and 22 on the drain region 8 are formed.
A capacitor having the first conductive film 30 above the drain region 8 and the intermetal dielectric film on the capacitor structure are formed. Then, as shown in FIG. 4, a first opening 38 is formed in the intermetal dielectric film 32 so as to reach the first conductive film 30 above the drain region 8. Next, the first conductive film 30 which is the third polysilicon film is anisotropically etched to remove the first conductive film 30 above the drain region 8 (FIG. 5).
Further, a dielectric sidewall separation film 40 is formed on the sidewall of the first opening 38 (FIG. 6). The dielectric sidewall isolation film 40 is the first conductive film 30.
And the bit line contact 50 are insulated and separated (FIG. 7).
In this manner, since the dielectric side wall isolation film 40 allows the use of a small bit line, the memory cell to be formed can be made small. In addition, the bit line material 56 is formed by filling the second opening (bit line contact hole) correspondingly formed through the dielectric sidewall isolation film 40 with metal.
Can be connected (Fig. 8).

More specifically, the present invention provides a high density D
A method of forming a bit line of a RAM is provided. To manufacture this DRAM, only three layers of polysilicon film need be used. First, as shown in FIG. 1, the drain region 8 is formed between the two separated transfer gates 14 and 18 on the semiconductor substrate 10. Then, the first insulating films 20 and 22 are formed on the inner sidewalls of the transfer gates 14 and 18 in the drain region 8 and the upper surfaces of the gate electrodes. The cell electrode 24
It is formed on the source region 4 (FIG. 2). Next, a capacitor dielectric film 26 is formed on the entire surface of the substrate including the cell electrode 24 (FIG. 3).

Capacitor dielectric film 26 and first insulating film 2
At least one first conductive film 30 (upper electrode plate) is formed on 0 and 22 (FIG. 3). It is desirable to form the first conductive film 3 0 on the entire surface of the substrate. Forming a first opening 38 in the intermetal dielectric film 32 above the drain region 8;
To expose the first conductive film 30 on the drain region 8 upward (Fig. 4). The first opening 38 is formed on the sidewall 3 of the intermetal dielectric film 32.
It is partitioned by 2A. Exposed first conductive film 30
Is anisotropically etched in the first opening 38 to expose the first insulating film 22 on the drain region 8 (FIG. 5). The side wall 30A of the first conductive film 30 is also formed in the first opening 38 by the anisotropic etching process (FIG. 5). As one of the important steps, the dielectric sidewall isolation film 40 is formed on the sidewalls 30A and 32A of the first conductive film 30 and the intermetal dielectric film 32. The dielectric sidewall isolation film 40 is also formed on the first insulating film 22. Is also formed, and the second opening 38A is formed through anisotropic etching.
Are formed (FIG. 6). Then, the bit line contact 50 is formed in the second opening 38A and electrically connected to the drain region 8. Finally, the protective film 54 and the bit line material 56, which is a metal film, are formed on the surface of the substrate to electrically connect the elements in the circuit (FIG. 8).

The present invention has many advantages as compared with the prior art, and only three layers of polysilicon film (the first polysilicon film 14A and the cell electrode 2 which is the second polysilicon film) are used.
4. Since the memory cell and the bit line contact hole of the DRAM can be formed only by using the first conductive film 30 which is the third polysilicon film, the number of resist and etching steps can be reduced as compared with the conventional technique. Can be reduced. Further, the protective space, which was indispensable for preventing a short circuit between the first conductive film 30 and the bit line contact 50, is reduced by four steps of the bit line contact hole (see steps f to i of claim 1). (Figs. 4 to 7). Compared with the conventional DRAM manufacturing process,
The memory cell area can be reduced by 10% to 20%. Furthermore, except the part where the bit line contact 50 on the drain region 8 is electrically connected to the drain region 8, the entire chip is covered with the first conductive film 30 which is the third polysilicon film (FIG. 3). By such a carpet type coating of the first conductive film 30 (upper electrode plate), D
The soft error rate of RAM can be significantly reduced.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below with reference to the drawings. First, referring to the basic principle of the present invention, the present invention discloses a method of forming a memory cell (for example, a DRAM), and has a fine scale "bit line on capacitor" structure. Therefore, the tolerance of the manufacturing process error can be increased and the yield can be improved with a small number of optical steps. It should be noted that the manufacturing process for forming the field oxide and the field effect transistor structure when forming the memory cell of the DRAM is described here only briefly within the range necessary for understanding the present invention. . As those skilled in the art will appreciate, other manufacturing processes not included in the description of this embodiment can be utilized, or other types of semiconductor devices can be included in the DRAM chip. For example, the method of the present invention can also be applied to the manufacture of P-wells in N-type substrates and CMOS circuits. Also, as a matter of course, what is shown in the drawings is a large number of DRAMs formed simultaneously on a substrate.
Only one of the memory cells. Furthermore, these bit lines can be applied to chips of other types than DRAM chips. Furthermore, these bit lines can be applied to other types of chips such as SRAM, EPROM, and E ² PROM.

The semiconductor substrate 10 shown in FIG. 1 includes a semiconductor wafer, active and passive elements formed inside the wafer, and each film body formed on the wafer. The term "substrate surface" includes each exposed film body on a semiconductor wafer, such as a silicon surface and an insulating film, and metal wiring.

In FIG. 1, the manufacturing process according to the present invention is performed by forming a bit line (not shown) on a semiconductor substrate 10 having field oxide films 12 and 12 and FET elements formed therebetween. is there. A field oxide film 12 is formed on the semiconductor substrate 10 to separate the active area and the insulating area. Preferred semiconductor substrate 1
0 is preferably made of P-type single crystal silicon having a crystal orientation (100). Generally, neither is shown, but relatively thick field oxide (FOX).
Are formed to surround the active areas and electrically insulate these areas. The field oxide is composed of thick silicon oxide (pad oxide) as well as a thicker silicon nitride film that is a resist to oxidation and is formed over the active area. Then, when the silicon substrate is oxidized in an oxidizing atmosphere, the field oxide film 12 shown in FIG. 1 is formed. Its preferred thickness is in the range of about 4000-6000Å.

Usually, after removing the silicon nitride resist film and the pad oxide by a wet etching process,
A semiconductor FET device is formed in the active region. DR
Of the AMs, the most frequently used is the MOSFET, and this device first thermally oxidizes the active region to form a thin gate oxide film 13. With a 3V power supply, the preferred thickness is in the range of about 75-120Å.

After depositing an appropriately doped polysilicon film (that is, the first polysilicon film 14A) and the insulating film 15 on the semiconductor substrate 10, the first polysilicon film 14A and the insulating film 15 are formed by a known lithography technique. Form into the required pattern. By this step, the transfer gates 14 and 18 of the MOSFET can be formed in the active region. As shown in FIG. 1, two transfer gates 14 and 18 are formed on the surface of the semiconductor substrate 10, and the positions are between the field oxide films 12 and 12. First active region (for example, source regions 4 and 4) between the transfer gates 14 and 18 and the field oxide film 12.
Are used for electrical connection with the memory cell capacitor. The region between the transfer gates 14 and 18, that is, the second active region (for example, the drain region 8) is used for electrical connection with the bit line. The other transfer gates are formed at other positions on the semiconductor substrate (none are shown). The transfer gates 14 and 18 are MOS
It can also be used to electrically connect the gate electrode of the FET to the word line of the appropriate peripheral circuitry on the DRAM chip. Next, the lightly doped source 4A and drain 8A of the N-channel MOSFET are formed,
An N-type ion species such as arsenic or phosphorus is implanted between the transfer gates 14 and 18 and the field oxide film 12 to form it. For example, a typical implant can be phosphorus P31, its dose can be in the range of about 1E13 to 1E14 atoms / cm2, and its implant energy can be in the range of about 30 to 80 KeV.

After forming the lightly doped source 4A and drain 8A, sidewall isolation films 16 and 17 can be formed on the sidewalls of the transfer gates 14 and 18. The side wall isolation film 17 facing the drain region 8 (bit line) is called an inner side wall isolation film 17. These side wall separation films 16 and 17 are
It is preferable that a low temperature silicon oxide film (not shown) is deposited and then the surface of this low temperature silicon oxide film is anisotropically back-etched. For example, this low-temperature silicon oxide film is made of tetraethyoxysilane (TEOS = tetraethoxys
(ilane) is used to perform chemical vapor deposition at a temperature in the range of about 650 to 900 ° C., and is then etched back by a low pressure reactive ion etching apparatus to form.

The source region 4 and the drain region 8 can be formed by at least two methods. First, the source region 4 and the drain region 8 of the MOSFET
Can implant an N-type ion species such as arsenic (As75) between the sidewall isolation films 16 and 17 to complete the source region 4 and the drain region 8. The implantation is usually performed through a thin silicon oxide film having a thickness of about 200 to 300Å in order to suppress the implantation channeling phenomenon as much as possible and avoid contamination from metals and other impurities. A typical dose is about 1E15-2E1
The implantation energy is set to about 2 at 6 atoms / cm2.
The range is 0 to 70 KeV. The drain region 8 which is the N + region is preferably formed by implanting arsenic or phosphorus, and its typical dose amount is about 1E15 to 1E16.
Atom / cm2 range, preferably about 5E15 atoms /
cm2, and the implantation energy amount is about 20 to 70 KeV
The range is. All other regions are covered during the ion implantation period for the source / drain. The second method is
The source region 4, which is the N + region, is preferably one that diffuses impurities through the cell electrode 24, which is a second polysilicon film to be formed later, as shown in FIG. 2 to complete the doping.

In the present embodiment, the parts described later are particularly related to the above-mentioned object of the present invention.
It is suitable for a method of manufacturing a three-layer polysilicon film DRAM for forming fine scale bit lines.

Similarly, in FIG. 1, the first insulating film 20,
22 at least the drain region 8 and the transfer gate 1
4, 18 inner sidewall separation film 17 and gate electrode 13,
It is formed on the upper surface of 14A, 15. The first insulating film 20,
22 can be formed of silicon oxide, for example deposited silicon oxide. The first insulating films 20 and 22 are
The thickness can be in the range of about 1000-2000Å. It is desirable that the first insulating films 20 and 22 have openings formed on the source region 4 by known lithography and etching techniques.

In FIG. 2, a cell electrode 24, which is a second polysilicon film, is formed on the source region 4, the outer wall 16 of the transfer gates 14 and 18, and the upper surfaces of the gate electrodes 13, 14A and 15. The cell electrode 24 constitutes an electrical connection to the source region 4. At this time, the cell electrode 24 can be formed on the surface of the substrate by patterning the conductive polysilicon film to be synchronously doped. The patterned polysilicon film covers the source region 4, the outer wall isolation film 16, and the upper surfaces of the transfer gate electrodes 14 and 18 to form the cell electrode 24. The thickness of the cell electrode 24 is set to about 2000 to 6000.
The range is Å. The cell electrode 24 is about 5E20 to 5E2.
The impurity concentration can be in the range of 1 atom / cm 3, preferably about 1E21 atom / cm 3. Further, the cell electrode 24 can be increased in surface area by being reinforced by using some techniques. For example, hemispherical grain polysilicon (HSG = hemisipherical grain polysi
licon) membrane is described by Dennison in US Pat. No. 5,401,681.
Is formed on the cell electrode described in No. Furthermore, N
As shown in FIG. 2, the source region 4 which is the + region is formed by diffusing and doping impurities through the cell electrode 24 which is the second polysilicon film.

In FIG. 3, a capacitor dielectric film 26 is deposited on the cell electrode 24. The material of the capacitor dielectric film 26 may be any material that has a high dielectric constant, good continuity, and no pinhole. The qualifying capacitor dielectric film 26 can be formed of silicon nitride, oxide / nitride / oxide (ONO) film, tantalum pentoxide (Ta2O5), or silicon oxide. Speaking of a 3V power supply, the capacitor dielectric film 26 that satisfies the condition is about 45
It is desirable that the equivalent oxide thickness be in the range of -60Å.

Similarly, in FIG. 3, a first conductive layer 30 which is an upper electrode plate is formed to cover the capacitor dielectric film 26. The formation of the first conductive layer 30 on the substrate surface can be utilized to achieve this coating. First conductive layer 30
Can be formed of silicon silicide or doped polysilicon material. The first conductive layer 30 is made of polysilicon by LPCVD (low pressure chemical vapor deposi).
using a low pressure chemical vapor deposition reactor.
It is desirable to form at a temperature of 0 to 650 ° C. The polysilicon film is N-type doped and can be ion-implanted, for example, by implanting arsenic ions with an implantation energy amount in a range of about 20 to 80 KeV and a dose amount of about 1E15 to 1E16 atoms / cm ^2. . As another method, synchronous doping can be performed when depositing the polysilicon film. The thickness of the first conductive layer 30 is about 1000 to
It is desirable to set it in the range of 2000Å. First conductive layer 3
The impurity concentration of 0 can be in the range of 1E21 to 1E22 atoms / cm ³ , preferably about 1E22 / cm ³ .

In the present invention, the first conductive layer 30, which is the third polysilicon film, is provided to connect the bit line contact 50 (see FIGS. 7 and 8) above the drain region 8 to the drain region 8. It is desirable to cover the entire chip except the bit line contact region.
Such a carpet-type coating of the first conductive layer 30 can significantly reduce the soft error rate.

In FIG. 4, an intermetal dielectric film 32 is formed on the first conductive layer 30. The intermetal dielectric film 32 is formed by borophosphosilicate glass or undoped TEOS method (silicon oxide), and has a thickness of about 50,000-100.
It is desirable that the thickness is in the range of 00Å.

Next, a first opening 38 is formed in the intermetal dielectric film 32 above the drain region 8 to expose the first conductive layer 30 above the drain region 8. The first opening 38 is defined by the sidewall 32A of the intermetal dielectric film 32. As shown in FIG. 4, the first opening 38 is formed in the intermetal dielectric film 32, but also includes a resist film 34 having an opening pattern 37, and the intermetal dielectric film is provided through the opening 37 pattern. 32 is anisotropically etched to remove the resist film 34. The size of the first opening 38 of the intermetal dielectric film 32 is set within the range allowed by the design rule, and the depth thereof is about 5 mm.
The range is from 000 to 10000Å.

In FIG. 5, the first conductive layer 30 exposed in the first opening 38 is removed by one anisotropic etching process. The first insulating film 22 on the drain region 8 is exposed by the anisotropic etching process. The sidewall 30A is formed in the first opening 38 by the anisotropic etching process.
The anisotropic etching process can be a dry etching process of polysilicon and has excellent selectivity with respect to polysilicon on the silicon oxide film. The anisotropic etching process is performed by using a chloride (Cl) containing a reactant such as CF ₂ -Cl.
It is desirable to perform the dry etching process of ₂ .

In FIG. 6, the dielectric side wall isolation film 40 is the side walls 30A, 3 of the first conductive film 30 and the intermetal dielectric film 32.
2A is formed. The dielectric sidewall isolation film 40 partially partitions at least the second opening 38A (first insulating film 22).
Except for the side wall 22A portion of). That is, the dielectric sidewall isolation film 40 is formed by depositing an oxide or a nitride on the intermetal dielectric film 32 using the first conductive film 30 and the intermetal dielectric film 32. Next, the first insulating film 2 in the first opening 38
The drain region 8 is exposed by anisotropically etching 2 and the second opening 38A (that is, the bit line contact hole) is completed. In this etching process, the sidewalls 30 of the first conductive film 30 and the intermetal dielectric film 32 are formed.
A dielectric side wall separation film 40 on A and 32A is partitioned. The dielectric sidewall isolation film 40 is preferably formed of a nitride, and has a range of about 400 to 600 Å and a thickness of about 500.
Desirably Å.

In FIG. 7, bit line contact 50
Are formed in the second opening 38A (see FIG. 6) connecting to the drain region 8. Bit line contact 50 is preferably formed from tungsten or aluminum. The bit line contact 50 has the second opening 38A.
Is formed by depositing a conductive film (not shown) on the inside of the substrate and on the intermetal dielectric film 32, and then patterning the conductive film on the intermetal dielectric film 32.

In FIG. 8, a protective film 54 is deposited, and a through hole 54A for the bit line contact 50 is opened by patterning. This protective film 54
Is preferably formed of borophosphosilicate glass (BPSG). A bit line material 56, which is a metal film, is deposited, and a necessary bit line (for example, a patterned metal wiring) is formed by patterning.

Therefore, in the present invention, three layers of polysilicon film (that is, the first polysilicon film 14A, the cell electrode 24 which is the second polysilicon film, and the first conductive film 30 which is the third polysilicon film) are formed. A DRAM memory cell can be manufactured only by using it. The number of resist and etching steps can be reduced as compared with the conventional technique of manufacturing a DRAM with a four-layer polysilicon film. Compared with the conventional technique of manufacturing a DRAM with four layers of polysilicon film, the present invention can omit two lithography steps, two RIE etching steps, and a bit line polysilicon module. Further, the bit line contact hole (second opening 38A. FIG. 6)
(See step f to i of claim 1)
As can be seen from the above, it is possible to greatly reduce the protection space that was conventionally indispensable for avoiding a short circuit between the word line (or the capacitor upper electrode plate) and the bit line.

In the method of the present invention, the drain region 8 is covered with the first conductive layer 30 (upper electrode plate) which is a polysilicon film, and the bit line contact 50 is used as the drain region 8.
The entire chip is covered except for the bit line contact region for electrical connection to. Such a carpet type coating can greatly reduce the soft error rate.

Although what is shown in the drawings is a stacked type capacitor, it will be understood by those skilled in the art that the bit line forming method according to the present invention can be applied to any type of capacitor. For example, it can be applied to a stacked capacitor and a trench capacitor.

While the present invention has been disclosed above with reference to preferred embodiments, it will be understood by those skilled in the art that many changes in form and detail may be made within the spirit and scope of the invention. It can be done.

[0038]

With the above-described structure, the method of forming the bit line of the memory cell / capacitor array according to the present invention requires only the use of three layers of polysilicon film in the DRAM.
Memory cell can be manufactured, the number of steps of lithography and etching can be reduced, and the tolerance of manufacturing error is increased by increasing the tolerance of the manufacturing error by the method of forming the bit line contact hole using the dielectric side wall isolation film. Since the protection space required to prevent short circuit between the memory cell and the bit line can be reduced, the area of the memory cell can be reduced to 10-2.
It can be reduced by 0%. Further, since the entire chip can be covered with the polysilicon film, the DRAM
The soft error rate of can be significantly reduced. Therefore, the present invention can improve the integration density and performance of the integrated circuit, reduce the number of steps, simplify the manufacturing process, reduce the cost, and improve the yield. High utility value.

[Brief description of drawings]

FIG. 1 is a process cross-sectional view showing formation of a gate electrode according to the present invention.

FIG. 2 is a process sectional view showing formation of a cell electrode according to the present invention.

FIG. 3 is a process sectional view showing formation of a first conductive film according to the present invention.

FIG. 4 is a process sectional view showing formation of a first opening according to the present invention.

FIG. 5 is a process cross-sectional view showing formation of a sidewall of the first conductive film according to the present invention.

FIG. 6 is a process cross-sectional view showing formation of a second opening according to the present invention.

FIG. 7 is a process sectional view showing formation of a bit line contact according to the present invention.

FIG. 8 is a process sectional view showing formation of a bit line according to the present invention.

[Explanation of symbols] 4 Source area 8 drain region 10 Semiconductor substrate 12 field oxide film 13 Gate oxide film 14 Transfer gate 14A First polysilicon film 16 Side wall separation membrane (outer wall separation membrane) 17 Side wall separation film (inner side wall separation film) 18 Transfer gate 20 First insulating film 22 First insulating film 24 Cell electrode (second polysilicon film) 26 Capacitor dielectric film 30 First conductive film (third polysilicon film) 30A side wall 32 Inter-metal dielectric film 32A side wall 34 Resist film 37 opening pattern 40 Dielectric sidewall separation film 50 bit line contact 54 Protective film 54A through hole 56 Bit line material (metal film)

Continued front page       (56) Reference JP-A-4-134858 (JP, A)                 JP-A-4-256358 (JP, A)                 JP-A-9-36329 (JP, A)                 Japanese Unexamined Patent Publication No. 8-236473 (JP, A)                 JP-A-8-335633 (JP, A)                 JP-A-5-198684 (JP, A)                 JP-A-8-264731 (JP, A)

Claims (11)

(57) [Claims] 1. A drain region is provided between two separated transfer gates on a semiconductor substrate, and these separated transfer gates are provided with a source region on both sides of the drain region and an inner wall surface facing the drain region. And an outer wall surface facing the source region, and an upper surface of the transfer gate, wherein the semiconductor substrate defines an active region including the source region and the drain region by a field oxide film region. ) Forming a first insulating film extending to the drain region, the inner wall of the transfer gate and an upper surface of the transfer gate; and b) the source region, an outer wall of the transfer gate and an upper part of the transfer gate. Forming a cell electrode extending to the surface,
Forming an electrical connection of the cell electrode to the source region; c) forming a capacitor dielectric film on the surface of the cell electrode; and d) first conductivity covering at least the capacitor dielectric film and the first insulating film. Forming a film; e) forming an intermetal dielectric film covering the first conductive film; and f) forming a first opening above the drain region of the intermetal dielectric film, the drain region Exposing the first conductive film above, and defining the first opening by at least a sidewall of the inter-metal dielectric film; and g) exposing the first conductive film inside the first opening. The film is removed by anisotropic etching to expose the first insulating film above the drain region and then the first insulating film.
Inside the opening, and forming the first conductive layer and a dielectric sidewall isolation layer <br/> sidewalls and on the on the first insulating layer of the intermetal dielectric layer, h) subsequent to said step of g) Anisotropic etching
To expose the drain region through the memory for forming a second opening, i) forming a bit line contact connected to the drain region in the interior of the second opening, and characterized by including a Method for forming bit line of cell / capacitor array. 2. The dielectric sidewall isolation film is formed by forming a dielectric film on the sidewalls of the intermetal dielectric film and the first conductive film and on the first insulating film inside the first opening. , the dielectric sidewalls of the first through the opening by performing an anisotropic etching, the formation of the second opening by exposing the drain region, located on the sidewalls of the intermetal dielectric layer and the first conductive film The method of claim 1, wherein an isolation layer partially defines the second opening . 3. A method of manufacturing a DRAM having a three-layer polysilicon film for forming a bit line on a capacitor, wherein a drain is formed between two transfer gates made of separate polysilicon on a semiconductor substrate. A region is provided, and these separated transfer gates have source regions on both sides of the drain region and have an inner wall surface facing the drain region and an outer wall surface facing the source region, and the upper surface of the transfer gate is Wherein the semiconductor substrate defines an active region including the source region and the drain region by a field oxide film region, a) on the drain region, an inner wall of the transfer gate and an upper surface of the transfer gate. Forming a extending first insulating film of silicon oxide; and b) the source region and the transfer gate. Of polysilicon extending to the outer wall of the gate and the upper surface of the transfer gate.
Forming a cell electrode that includes the steps of forming an electrical connection to the source region of the cell electrode, c) forming a capacitor dielectric film on the cell electrode surface, d) a first insulating including the capacitor dielectric layer Forming a first conductive film made of polysilicon covering the film; e) forming an intermetal dielectric film made of non-doped silicon oxide covering the first conductive film; and f) the intermetal dielectric film. Forming a first opening above the drain region, exposing the first conductive film above the drain region, and defining the first opening by at least a sidewall of the intermetal dielectric film. And g) anisotropically etching the first conductive film exposed inside the first opening to form a sidewall of the first conductive film inside the first opening. Comprising the steps of, h) forming a first opening wherein the intermetal dielectric layer and said the side wall of the first conductive film first insulating film and the dielectric sidewall isolation layer inside the, i) wherein h) Following the step, anisotropic etching
Memory characterized by comprising exposing said drain region via, forming a second opening, and forming a bit line contact connected to the drain region in the interior of j) said second opening Method for forming bit line of cell / capacitor array. 4. The step b) of forming the cell electrode.
Forming a polysilicon film above the source region and the drain region and etching the polysilicon film to form a polysilicon film on the source region, the outer wall and a part of the upper surface of the transfer gate. 4. The method for forming a bit line of a memory cell / capacitor array according to claim 3, wherein 5. The first conductive film is made of doped polysilicon and has an impurity concentration of about 1E15 to 1E16.
The thickness is 1000 to ^{200 with} the range of atoms / cm ^2.
4. The method of forming a bit line of a memory cell / capacitor array according to claim 3 , wherein the first conductive film is formed on the entire surface of the substrate while having a range of 0Å. 6. The step f) of forming the first opening in the intermetal dielectric film forms a resist film provided with a first opening pattern, and the intermetal dielectric film is formed through the first opening pattern. 2. The method of forming a bit line of a memory cell capacitor array according to claim 1, wherein the resist film is removed while anisotropically etching. 7. The method for forming a bit line of a memory cell capacitor array according to claim 1, wherein the anisotropic etching in step g) uses reactive ion etching including chloride gas. . 8. The first insulating film has a thickness of about 100.
4. The method of forming a bit line of a memory cell / capacitor array according to claim 1, wherein the bit line is formed of silicon oxide in the range of 0 to 2000Å. 9. The memory cell according to claim 1, wherein the intermetal dielectric film is made of borophosphosilicate glass (BPSG) and has a thickness in the range of about 5000 to 10000Å. A method of forming a bit line of a capacitor array. 10. The method according to claim 1, further comprising forming a protective film and a patterned metal film on the intermetal dielectric film and the bit line contact. 3 memory cell
Method of forming bit line of capacitor array. 11. The dielectric sidewall isolation film is made of one of silicon oxide and silicon nitride, and
4. A method of forming a bit line of a memory cell / capacitor array according to claim 1, wherein the thickness is in the range of about 400 to 600Å.