JP3423960B2 - Light output correction circuit for light emitting diode array - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a light output correction circuit of a light emitting diode array, which is used for a recording head of an optical printer or the like, and corrects a difference in light output of each light emitting diode, and more particularly to a logic circuit. The present invention relates to a light output correction circuit for a light emitting diode array, which has a small number of parts and can cope with changes in the number and configuration of light emitting diodes.

[0002]

2. Description of the Related Art FIG. 3 shows a conventional light output correction circuit for a light emitting diode array.

The light output correction circuit of this light emitting diode array includes an oscillator 1 for generating a clock, an address data generation counter 2 for counting the clock to generate address data, and a nonvolatile memory for storing correction data for each light emitting diode. The memory 6 includes a control signal generation circuit 7 that generates various control signals, and a line selector 5 that switches whether to input lighting data or correction data to the light emitting diode array 4.

The light emitting diode array 4 is provided with a driver 42 for driving each of the light emitting diodes 41, and each driver 42 is constituted by connecting a plurality of transistors in parallel.
Is provided and a latch circuit 43 for selectively driving the transistor according to the correction data is provided.

The control signal generation circuit 7 includes a line selector 5
Line switching signal generation circuit 71, a latch circuit selection signal generation circuit 72 connected to a latch circuit in the light emitting diode array, and a latch strobe signal generation circuit 7.
It is composed of three.

The clock output from the oscillator 1 is input to the address data generation counter 2. The address data generation counter 2 counts this clock and generates address data that gradually increases or decreases. This address data is
It is input to the nonvolatile memory 6 and the control signal generation circuit 7.
The correction data stored at the address is output from the non-volatile memory 6. From the control signal generation circuit 7, a line switching signal for switching whether to input lighting data or correction data to the light emitting diode array, a latch circuit selection signal for selecting which latch circuit to latch the correction data, and a latch. A latch strobe signal that controls the storage of correction data in the circuit is output.

The line selector 5 receives lighting data from a host device (not shown) and correction data from a non-volatile memory, and the line selector 5 outputs either the lighting data or the correction data to latch the data. 43 is input.

By inputting the lighting data to the latch circuit 43, it is determined whether or not the light emitting diode is lighted. The combination of which transistor is driven is determined by inputting the correction data to the latch circuit.

Since the transistor of each driver is selectively driven by the correction data for each light emitting diode, the difference in the light output for each light emitting diode is corrected and the unevenness is eliminated.

Conventionally, the line switching signal generation circuit, the latch circuit selection signal generation circuit, and the latch strobe signal generation circuit are all composed of a combination of logic circuits.
The signal generated by each is based on the address data.

[0011]

Since the output timing of the control signals such as the line switching signal, the latch circuit selection signal and the latch strobe signal is determined by the logic circuit, the parts forming the logic circuit are necessary. . Therefore, it is difficult to reduce cost, size, and current consumption. In addition, when the number and configuration of the light emitting diodes are changed and the output timing of the control signal is changed, the configuration of the logic circuit must be changed.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to solve the above problems and provide a light output correction circuit for a light emitting diode array, which has a small number of parts constituting a logic circuit and can cope with a change in the number and structure of the light emitting diodes. is there.

[0013]

In order to achieve the above object, the present invention provides a driver in which a plurality of transistors are connected in parallel to each of a plurality of light emitting diodes, and the driver is provided with lighting data of the light emitting diodes. A light-emitting diode array light that corrects the difference in light output for each light-emitting diode by providing a latch circuit that individually drives these multiple transistors according to the correction data and supplies the respective correction data to each latch circuit In the output correction circuit, the correction data corresponding to each latch circuit and the latch circuit to which the correction data is supplied are set.
A memory for storing control data for controlling a latch operation including a designated bit is provided, and an address circuit for sequentially reading data from the memory and supplying the data to the latch circuit is provided.

The control data is supplied to the latch circuit as a point.
A bit that switches between sending the lamp data and the correction data.
May be included.

The control data controls the address circuit.
Control bits may be included.

The present invention also provides a plurality of light emitting diodes.
A driver with multiple transistors connected in parallel
The driver is equipped with this driver to turn on the light emitting diode.
Gives data and corrects these multiple transistors
Provide a latch circuit that is driven individually according to the data, and
Each correction data can be supplied to each latch circuit.
To correct the difference in light output for each light emitting diode
In the light output correction circuit of the light emitting diode array,
Control the correction data and the latch operation corresponding to the switch circuit.
A memory for storing multiple control data is provided to
Data and control data are the same for the same light emitting diode
Stored at the same address as the data corresponding to
The same light emitting diode timing is applied to multiple consecutive addresses.
The data corresponding to the
Read data in address order and supply to the latch circuit
An address circuit is provided.

[0017]

BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of the present invention will be described in detail below with reference to the accompanying drawings.

FIG. 1 shows a light output correction circuit for a light emitting diode array according to the present invention. Elements common to those in FIG. 3 are designated by the same reference numerals.

The light output correction circuit of the light emitting diode array includes an oscillator 1 for generating a clock, an address data generation counter (address circuit) 2 for counting the clock to generate address data, and correction data for each light emitting diode. And a non-volatile memory 3 for storing control data,
The light emitting diode array 4 is composed of a line selector 5 for switching between lighting data and correction data.

The light emitting diode array 4 is provided with a driver 42 for driving each light emitting diode 41, and each driver 42 is constituted by connecting a plurality of transistors (not shown) in parallel. Further, the light emitting diode array 4 is provided with a latch circuit 43 for turning on / off the driver 42 according to the lighting data and selectively driving the transistors according to the correction data.

The non-volatile memory 3 has an area 31 for storing correction data and an area 32 for storing control data. The correction data and the control data are stored at the same address so that the data corresponding to the same timing of the same light emitting diode can be taken out at the same time. Here, 8 bits are used for correction data, 1 bit is used for line switching, and 2 bits are used for latch circuit selection.
Bits, 4 bits are used for the latch strobe, and 1 bit is used for controlling the address data generation counter. By storing the data corresponding to the signal timing order of the same light emitting diode in a plurality of consecutive addresses, the data output can be changed each time the address increases or decreases by one. As a result, it is possible to form a control signal that statically switches or a control signal having a rising or falling edge.

Of the data output lines of the non-volatile memory 3, the correction data 101 is connected to one data input section of the line selector 5, and each bit of the control data is connected to each circuit. That is, the line switching bit (line switching signal) 102 is connected to the switching signal input portion of the line selector 5, and the latch circuit selection 2 bits (latch circuit selection signal) 103 are decoded into 4 bits by a decoder (not shown). Connected to the select input section of the latch circuit, 4 bits of the latch strobe (latch strobe signal) 104 are separately connected to the four groups of the latch circuit, and bits of address data generation counter control (address data generation counter control signal) 105 Is connected to the counter stop input.

To the address input of the nonvolatile memory 3, the output (address data) 10 of the address data generation counter is input.
6 is connected.

The operation of this light output correction circuit will be described with reference to the timing chart of FIG.

When the circuit is activated, the line switching selects correction data, and the address data generation counter control selects operation of the address data generation counter 2.

The clock 107 output from the oscillator 1 is input to the address data generation counter 2. The address data generation counter 2 counts this clock 107 to generate address data 106 that gradually increases or decreases. The address data 106 is input to the nonvolatile memory 3. The correction data 101 stored at the address is output from the non-volatile memory 3.

At the same time, control data is output. That is, a line switching signal 102 for inputting correction data to the light emitting diode array 4, a latch circuit selection signal 103 for selecting which latch circuit to latch the correction data, and a latch strobe for controlling the storage of the correction data in the latch circuit. The signal 104 and the address data generation counter control signal 105 for operating the address data generation counter are output.

The correction data 101 from the non-volatile memory 3 is input to the line selector 5, and the correction data is output from the line selector 3 and input to the latch circuit 43. The latch circuit selection signal 103 is decoded by a decoder (not shown) into four signals, which are input to four groups of latch circuits. Therefore, any one group is selected. The latch circuit selection signal 103 is
Continued for multiple clocks. Latch strobe signal 10
4 is output one pulse at a time during the continuous period.
Therefore, the parallel 8-bit correction data that is sequentially output each time the address is updated is sequentially latched by each latch circuit in one group.

4-bit correction data is latched in one latch circuit. This is because the four transistors that make up one driver 42 have a current capacity of 1 time, 2 times, 4 times.
This is because the current capacity is doubled and eight times larger, and 16 levels of current capacity can be realized by combination.

In this way, the light emitting diode array 4
The respective correction data are latched in the latch circuits corresponding to all the light emitting diodes. In addition, the correction data for each light emitting diode is to light each light emitting diode in advance with a uniform current, measure the light output intensity of each light emitting diode, and based on this measurement result, all the light emitting diodes are lit without uneven light output. It is calculated to do.

When the latching of all the correction data is completed, the non-volatile memory 3 outputs an address data generation counter control signal for stopping the address data generation counter 2. Further, the line switching signal 102 for inputting the lighting data to the light emitting diode array 4 is output, and the line selector 5 outputs the lighting data 108 from the host device (not shown) to the light emitting diode array 4.

[0032]

The present invention exhibits the following excellent effects.

(1) When the number and configuration of the light emitting diodes are changed, it is necessary to change the configuration of the logic circuit in the past, but in the present invention, it is easy to change the data stored in the memory. Yes, the circuit does not need to be modified.

(2) A logic circuit for generating a control signal is not required, and cost reduction, size reduction, and current consumption reduction can be achieved.

(3) Conventionally, the address data generation counter continues to operate even after the correction data input to the light emitting diode array is completed, but in the present invention, the address data generation counter is stopped after the correction data input is completed. The subsequent current consumption can be reduced.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a light output correction circuit showing an embodiment of the present invention.

2 is an operation timing chart of the optical output correction circuit of FIG.

FIG. 3 is a circuit diagram of a conventional light output correction circuit.

[Explanation of symbols]

1 oscillator 2 Address data generation counter 3 Non-volatile memory 4 Light emitting diode array 5 line selector 41 light emitting diode 42 driver 43 Latch circuit

─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Toshio Hino 4-1-1 Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture Fujitsu Limited (72) Inventor Motohiro Tokaibayashi 4-chome, Ueodaanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture No. 1-1 No. 1 within Fujitsu Limited (56) Reference JP-A-1-258965 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) B41J 2/44 B41J 2/45 B41J 2 / 455 H01L 33/00 H04N 1/036

Claims (4)

(57) [Claims] 1. A latch for providing a driver in which a plurality of transistors are connected in parallel to each of a plurality of light emitting diodes, and supplying the driver with lighting data of the light emitting diodes and individually driving the plurality of transistors according to correction data. In the light output correction circuit of the light emitting diode array that corrects the difference in light output of each light emitting diode by providing a circuit and supplying each correction data to each latch circuit, the correction data corresponding to each latch circuit Latch circuit to which correction data is supplied
A memory for storing control data for controlling a latch operation including a bit designating a bit, and an address circuit for sequentially reading data from the memory and supplying the data to the latch circuit. And a light output correction circuit for the light emitting diode array. 2. The control data is supplied to a latch circuit.
You can switch between sending lighting data and correction data.
2. The light output correction circuit for a light emitting diode array according to claim 1 , further comprising: 3. The control data is stored in the address circuit.
3. The method according to claim 1 , further comprising a control bit.
A light output correction circuit for the light emitting diode array described. 4. A plurality of LEDs for each of the plurality of light emitting diodes.
Provide a driver that connects the transistors in parallel.
Give the lighting data of the light emitting diode to the driver of
Together with these multiple transistors according to the correction data
A latch circuit that drives individually is provided, and each latch circuit
Light emission by supplying each correction data to the road
Light-emitting diode that corrects the difference in light output for each diode
Supports each latch circuit in the array optical output correction circuit
Control data to control the correction data and the latch operation.
A memory for storing the data and
Data corresponding to the same timing of the same light emitting diode.
Data stored in the same address as the data
Addresses correspond to the same light emitting diode timing order.
Data is stored and the data in this memory is addressed.
Address circuits that are read out in sequence and supplied to the latch circuit
A light output correction circuit for a light emitting diode array characterized by being provided .