JP3419131B2 - Absolute scale device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an absolute scale device used, for example, in metal working machine tools, industrial machines, precision length measuring and angle measuring devices, and the like.

[0002]

2. Description of the Related Art Conventionally, the problems to be solved by the invention
The so-called "battery backup method" and "code plate method" are used as absolute scale devices used in metalworking machine tools, industrial machines, precision length measuring and angle measuring devices, etc.
And are put to practical use.

The former "battery backup system" is
Incrementally detected position information is counted by a counting controller that is backed up by a battery, and the absolute position when power is cut off is held.

This is basically an incremental type scale, and although it is easy to cope with high resolution, a battery for backup is required and periodic maintenance work is required to maintain reliability. there were. Further, in order to secure a correct absolute position for movement of a machine or the like when the power is cut off, it is necessary to supply power not only to the counting control unit but also to the detection unit. Increasing the size was inevitable.

Further, there is a problem in maintainability and reliability that the absolute position cannot be restored once the absolute value information is lost due to mixing of noise or the like.

On the other hand, as the latter "code plate system",
There are methods such as detecting the total scale length using a code plate of multiple tracks, and a system in which the resolution is improved by combining the main track and the code plate.Therefore, even when the power is cut off or noise is mixed, Although it is excellent in terms of reliability such as being able to reliably return the absolute position, it has an essential drawback that the absolute value measurement range and the realizable resolution are limited by the number of tracks.

For this reason, this code plate system inevitably involves an increase in cost due to the complexity of the structure, and at the expense of resolution, the increase in the number of tracks must be suppressed and the cost must be optimized. At present, it is rarely put to practical use in fields requiring high resolution,
The application is limited to the industrial machine field, which has a relatively low resolution.

In view of the above points, the present invention has an object to obtain a relatively small-sized and high-resolution absolute scale device.

[0009]

In the absolute scale device of the present invention, a main track recorded so as to output an incremental signal having a wavelength λ, and a relative displacement amount between the main track and a main track detection head are used as a movement amount. A main track signal detecting means for extracting as a phase-modulated signal corresponding to the main track signal detecting means for detecting the position within the reproduction wavelength λ as an absolute value, and a section equal to the reproduction wavelength λ of the main track or an integral multiple thereof is divided as an information recording unit This information recording unit has the same wavelength as the reproduction wavelength λ of the main track, and the phase amount 2π is N (N is 3 or more) based on the reproduction signal of the main track according to the address information to be recorded. M) (M is a positive integer) number of address tracks recorded so that signals having a phase difference divided into
An address signal detecting means for demodulating address information from a detection signal from an address track detecting head which works with this main track detecting head, corresponding to each address track, and a reproduction wavelength λ obtained from the main track signal detecting means. And the absolute value of the address information obtained from the address signal detecting means are combined with each other by compensating the weights and combining them.

[0010]

According to the present invention, M address tracks are divided into information recording units in a section equal to the reproduction wavelength λ of the main track or an integral multiple thereof, and the reproduction wavelength of the main track is divided into the information recording units. A signal having the same wavelength as λ and having a phase difference obtained by dividing the phase amount 2π into N (N is an integer of 3 or more) in accordance with the address signal to be recorded is used as a reference. Since it is recorded so as to be output, it is possible to obtain an absolute scale device in which the number M of address tracks is relatively high in resolution.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment in which the absolute scale device of the present invention is applied to a magnetic scale device will be described below with reference to the drawings. In the magnetic scale device, for example, a magnetoresistive element is used as a detection head. Depending on the configuration, half of the recording wavelength may be reproduced as one cycle, but here, description will be made with reference to the wavelength of the reproduction signal regardless of the recording wavelength. In FIG. 1, 1 indicates a magnetic scale, and the length of the magnetic scale 1 is, for example, 81
9.2 mm, and in this example, this magnetic scale 1
As shown in FIG. 2, a main track 2 and four address tracks 3, 4, 5 and 6 are provided along the longitudinal direction of the magnetic scale 1.

As shown in FIG. 3A, a magnetic scale is recorded on the main track 2 so as to output a sine wave signal (incremental scale) having a reproduction wavelength λ of 0.2 mm, for example. In addition, in this example, the main track 2 is added to the first address track 3 as shown in FIGS. 2, 3B and 4A.
Is divided as an information recording unit, and the information recording unit has the same wavelength λ as the reproducing wavelength λ of the main track 2 and a phase amount 2π based on the reproducing signal of the main track 2. Is sequentially magnetically recorded so as to output a signal having a phase difference φ (d) of, for example, 45 ° divided into 8 (= 2 ³ ) ways.

That is, as shown in FIGS. 3B and 4A, in the first λ section d1,1 of the first address track 3, a sine wave signal having the same phase difference of 0 ° as the reproduction signal of the main track 2 is obtained. The magnetic scale is recorded as follows, and this second λ section d
Magnetic scales 1 and 2 are recorded so that a sine wave signal with a phase difference of 45 ° with the reproduction signal of the main track 2 is obtained.
A magnetic scale is recorded in the fourth λ section d1,3 so that a sine wave signal having a phase difference of 90 ° with the reproduction signal of the main track 2 is obtained. A magnetic scale is recorded so that a sine wave signal having a phase difference of 135 ° with the reproduction signal is recorded, and the fifth λ section d1,5 is a sine wave signal having a phase difference of 180 ° with the reproduction signal of the main track 2. A magnetic scale is recorded so that the phase difference between the reproduced signal of the main track 2 and the reproduced signal of the main track 2 is 2 in the sixth λ section d1,6.
A magnetic scale is recorded so that a sine wave signal of 25 ° can be obtained, and the λ section d1,7 of the seventh address is magnetic so that a sine wave signal having a phase difference of 270 ° with the reproduction signal of the main track 2 is obtained. A graduation is recorded, and a magnetic graduation is recorded in the eighth λ section d1,8 so that a sine wave signal having a phase difference of 315 ° from the reproduction signal of the main track 2 is obtained. In the above, the recording is sequentially repeated so as to output the eight kinds of sine wave signals.

In this example, as shown in FIGS. 2 and 4B, information recording is carried out on the second address track 4 in a section (8λ) that is 8 (= 2 ³ ) times the reproduction wavelength λ of the main track 2. The information recording unit (8λ) has the reproduction wavelength λ of the main track 2 and the phase amount 2π is divided into 8 (= 2 ³ ) ways based on the reproduction signal of the main track 2. Magnetic recording is sequentially performed so as to output signals having a phase difference of 45 °, for example.

That is, as shown in FIG. 4B, the first 8λ section d2,1 to d2,8 of the second address track 4 has a reproduction wavelength λ having the same phase difference of 0 ° as the reproduction signal of the main track 2. A magnetic scale is recorded so that a sine wave signal can be obtained. In this second 8λ section d2,9 to d2,16, a sine wave signal having a phase difference of 45 ° with the reproduction signal of the main track 2 is obtained. Record the magnetic scale and record the third 8λ section d2,17-d
The magnetic recording marks 2 and 24 are recorded so that a sine wave signal with a phase difference of 90 ° from the reproduction signal of the main track 2 can be obtained.
A magnetic scale is recorded in the eighth 8λ section d2,25 to d2,32 so as to obtain a sine wave signal having a phase difference of 135 ° with the reproduction signal of the main track 2, and the fifth 8λ section d2,33 to d
2,40 has a magnetic scale recorded so that a sine wave signal having a phase difference of 180 ° with the reproduction signal of the main track 2 is obtained, and the sixth 8λ section d2,41 to d2,48 of the main track 2 is recorded. A magnetic scale was recorded so that a sine wave signal having a phase difference of 225 ° from the reproduction signal was obtained, and the seventh 8λ section d2,49 ~
The magnetic scale is recorded on d2,56 so as to obtain a sine wave signal having a phase difference of 270 ° with the reproduction signal of the main track 2, and the eighth 8λ section d2,57 to d2,64 of the 8th 8λ section A magnetic scale is recorded so that a sine wave signal having a phase difference of 315 ° with the reproduction signal is obtained, and the second address track 4 is sequentially repeated every 8λ sections so as to output the eight kinds of sine wave signals. I will record it.

Further, in this example, a section (64λ) of 64 (= 2 ⁶ ) of the reproduction wavelength λ of the main track 2 is divided as an information recording unit in the third address track 5, and this information recording unit (64λ ) Has the reproduction wavelength λ of the main track 2 and the phase amount 2 based on the reproduction signal of the main track 2.
Phase difference obtained by dividing π into 8 (= 2 ³ ) ways, for example, 4
Sequential magnetic recording is performed so as to output a signal having 5 °.

That is, in the first 64λ section d3,1 to d3,64 of the third address track 5, a sine wave signal having a reproduction wavelength λ having the same phase difference as that of the reproduction signal of the main track 2 is obtained. The magnetic scale is recorded so that the second 64λ
In the section d3,65 to d3,128, a magnetic scale is recorded so that a sine wave signal having a phase difference of 45 ° with the reproduction signal of the main track 2 is recorded, and the third 64λ section d3,129 to d3,192.
Is recorded on the magnetic scale so as to obtain a sine wave signal having a phase difference of 90 ° with the reproduction signal of the main track 2, and the fourth 64λ section d3,193 to d3,256 is the reproduction signal of the main track 2 The magnetic scale was recorded so that a sine wave signal with a phase difference of 135 ° could be obtained, and the fifth 64λ section d3,25 was recorded.
7 to d3,320 has a phase difference of 18 with the reproduction signal of the main track 2.
A magnetic scale is recorded so that a 0 ° sine wave signal can be obtained. In the sixth 64λ section d3,321 to d3,384, a sine wave signal having a phase difference of 225 ° with the reproduction signal of the main track 2 is obtained. The magnetic scale is recorded so that the 7th 64λ section d3,384 to d3,448 is recorded so that a sine wave signal having a phase difference of 270 ° with the reproduction signal of the main track 2 is obtained. , The 8th 64λ section d3,449
~ D3,512 has a phase difference of 315 with the reproduction signal of the main track 2.
Record the magnetic scale to obtain a sinusoidal signal of °,
On the third address track 5, recording is sequentially repeated every 64λ sections so that the eight kinds of sine wave signals are output.

In the present example, the fourth address track 6 has a recording wavelength λ of the main track 2 of 512 (= 2 ⁹ ).
(512λ) is divided as an information recording unit, and the reproduction wavelength λ of the main track 2 is divided into this information recording unit (512λ).
Further, magnetic recording is sequentially performed so as to output a signal having a phase difference of, for example, 45 ° each obtained by dividing the phase amount 2π into, for example, 8 (= 2 ³ ) ways based on the reproduction signal of the main track 2.

That is, in the first 512λ section d4,1 to d4,512 of the fourth address track 6, a sine wave signal having a reproduction wavelength λ with the same phase difference as the reproduction signal of the main track 2 is obtained. Record the magnetic scale so that the second 5
In the 12λ section d4,513 to d4,1024, magnetic scales are recorded so that a sine wave signal having a phase difference of 45 ° with the reproduction signal of the main track 2 is recorded, and the third 512λ section d4,1025 is recorded.
~ D4,1536 has a phase difference of 90 ° with the reproduction signal of main track 2
The magnetic scale is recorded so as to obtain the sine wave signal of, and the fourth 512 λ section d4,1537 to d4,2048 is a sine wave signal having a phase difference of 135 ° with the reproduction signal of the main track 2. Record the magnetic scale on the
In the 2λ section d4, 2049 to d4, 2560, the magnetic scale is recorded so that a sine wave signal having a phase difference of 180 ° with the reproduction signal of the main track 2 is recorded, and the sixth 512λ section d4, 2561.
~ D4,3072 has a phase difference of 225 from the reproduction signal of the main track 2.
Record the magnetic scale to obtain a sinusoidal signal of °,
In the seventh 512 λ section d4,3073 to d4,3584, a magnetic scale is recorded so that a sine wave signal having a phase difference of 270 ° with the reproduction signal of the main track 2 is recorded.
In the 12λ section d4, 3585 to d4, 4096, magnetic scales are recorded so that a sine wave signal having a phase difference of 315 ° with the reproduction signal of the main track 2 can be obtained. Sequential recording is performed every 512 λ intervals so that a sine wave signal is output.

With respect to the magnetic scale 1, as shown in FIG. 1, a main track detecting head 31 for detecting the main track 2 is provided.
And the first, second, third and fourth address tracks which interlock with the main track detection head 31 to detect the first, second, third and fourth address tracks 3, 4, 5 and 6, respectively. The detection heads 32, 33, 34, and 35 are provided, for example, arranged in-line at substantially right angles to the detection direction.

The main track signal detected by the main track detection head 31 is supplied to the phase detection circuit 41. The phase detection circuit 41 is constructed, for example, as shown in FIG. In FIG. 5, the main track detection head 31 is provided with two magnetoresistive effect magnetic heads arranged so as to obtain an output signal having an electrical phase difference of 90 ° with respect to the reproduction wavelength λ of the main track 2. It is composed of heads 31a and 31b.

In FIG. 5, 41h indicates a rectangular wave signal input terminal for excitation to which a rectangular wave signal EX of frequency f is supplied, and the rectangular wave signal EX supplied to this rectangular wave signal input terminal 41h is low-passed. The magnetic signals are supplied to the magnetic heads 31a and 31b as the excitation signal e _x via the filter 41f and the excitation amplifier 41g, respectively. Note that the rectangular waveform signal EX as the excitation signal may be directly supplied to the magnetic heads 31a and 31b via the excitation amplifier 41g.

The excitation signal e _X is e _X = sinωt (1) obtained by converting the rectangular wave signal EX into a sine wave by the low pass filter 41f.

The signal detected by the magnetic head 31a is supplied to the adding amplifier 41d via the preamplifier 41a, and the signal detected by the magnetic head 31b is added via the preamplifier 41b and the 90 ° phase shifter 41c. It is supplied to the amplifier 41d.

In this case, the magnetic heads 31a and 31b are arranged so as to obtain an output signal electrically having a phase difference of 90 ° with respect to the reproduction wavelength λ of the main track 2, so that the preamplifier 41a is provided. And 41b respectively output signals e ₁ and e ₂ can be expressed as: e ₁ = sin ωt × cos (2πx / λ) (2) e ₂ = sin ωt × sin (2πx / λ) (3) where ω = 2πf and x are positions within the wavelength λ (absolute position) ).

By the way, the output signal e _{2 of the} preamplifier 41b
The 90 ° phase shifter 41c causes the carrier phase to be 90 °.
After being changed, it is added by the addition amplifier 41d. Therefore, the output signal e _P of the adding amplifier 41d becomes a phase modulation signal as shown in the following equation.

E _p = sin (ωt + 2πx / λ) (4)

In this example, the phase modulation signal e _p is converted into a rectangular wave via the waveform shaping circuit 41e and output as the phase modulation signal S converted into the rectangular wave. In this case, the phase-modulated signal S converted into the rectangular wave can be expressed as follows if only its phase is focused. S = sin (ωt + 2πx / λ) (5)

That is, the phase modulation signal S is a rectangular wave signal whose phase changes depending on the positions of the main track 2 and the main track detection head 31 (31a, 31b) within the wavelength λ, and its phase amount (2πx / Λ) is the amount of movement is 2π for each λ
(= 360 °).

The phase modulation signal S obtained at the output side of the phase detection circuit 41 is supplied to the λ internal position detection circuit 42. The in-λ position detection circuit 42 discriminates the phase amount (2πx / λ) of the phase-modulated signal S and compares the phase amount with the reference phase amount 2π (= 360 °) corresponding to the wavelength λ. The position within λ is detected.

Here, the phase modulation signal e _p shown in equation (4)
The phase amount (2πx / λ) can be detected in an analog manner with reference to the carrier frequency of the phase modulation signal e _p , that is, the excitation signal e _x shown in the equation (1). Assuming that the amount of change is sufficiently small, this reference signal is replaced with the excitation signal e _X and used as a rectangular wave signal EX for excitation, and this phase amount is digitally compared by comparing with the phase modulation signal S shown in equation (5). (2πx /
λ) can be detected.

FIG. 6 shows an example of the configuration of the position detection circuit 42 within λ.
Shown in. 6, the phase modulation signal S supplied to the S signal input terminal 41i is supplied to the synchronous differentiating circuit 42a and the clock signal CK having a frequency of 200f supplied to the clock signal input terminal 42f is supplied to the synchronous differentiating circuit 42a. Pulse Ds, which is supplied to the output terminal of the synchronous differentiating circuit 42a and is synchronized with the rising edge (or falling edge) of the phase modulation signal S, which constitutes the phase comparison circuit.
-K is supplied to the K terminal of the flip-flop circuit 42c.

Further, the rectangular wave signal EX having a frequency f obtained at the rectangular wave signal input terminal 41h is supplied to the synchronous differentiating circuit 42b, and the clock signal CK obtained at the clock signal input terminal 42f is supplied to the synchronous differentiating circuit 42b. Then, the phase comparison circuit is configured by using the pulse Dr obtained at the output terminal of the synchronous differentiating circuit 42b in synchronization with the rising (or falling) of the rectangular wave signal EX as a reference signal.
It is supplied to the J terminal of the -K flip-flop circuit 42c, and the clock terminal C of this J-K flip-flop circuit 42c is supplied.
Frequency 200f from clock signal input terminal 42f for K
Of the clock signal CK.

In this case, J which constitutes this phase comparison circuit
At the output terminal of the -K flip-flop circuit 42c, the phase amount (2πx / λ) of the phase modulation signal S, that is, the position x within the wavelength λ.
A pulse width modulation signal W _p whose pulse width changes corresponding to is obtained.

By the way, the carrier frequency of the phase modulation signal S is f, and its phase amount changes by 2π (= 360 °) corresponding to the movement of the wavelength λ (0.2 mm). Further, the time corresponding to the phase 2π (= 360 °) corresponds to one cycle time of the carrier frequency of the phase modulation signal S, that is, 1 / f.

The pulse width modulation signal W _p obtained at the output end of the phase comparison circuit 42c is supplied to one input terminal of the AND gate circuit 42d and the AND gate circuit 4 is supplied.
A clock signal CK having a frequency of 200f is supplied to the other input terminal of 2d.

In this case, the output side of the AND gate circuit 42d has a resolution of 1 μm corresponding to the position x within the wavelength λ.
A unit pulse train signal P _W is obtained, and this pulse train signal P _W is obtained.
_The data D (R) obtained by measuring the absolute position within the wavelength λ with a resolution of 1 μm for each cycle of the phase modulation signal S by counting _W by the 200-ary counter 42e is output from the output terminal 4
2g can be obtained. Data D of the absolute position x with a resolution of 1 μm within the wavelength λ obtained at the output terminal 42g
(R) is supplied to the absolute address generation circuit 51 described later.

Further, in this example, as shown in FIG. 1, the first, second, third and fourth address track detection heads 3 are provided.
2, 33, 34 and 35 detect the first, second, third and fourth address signals respectively, and phase detection circuits 43, 45, respectively.
47 and 49 respectively. Phase detector circuit 4
3, 45, 47 and 49 are respectively constructed as shown in FIG. 5 similarly to the phase detection circuit 41. The first, second, third and fourth address track detection heads 32, 33, 34 and 3
Reference numeral 5 is also a magnetic head of the magnetoresistive effect type which is arranged so as to obtain an output signal having an electrical phase difference of 90 ° with respect to the recording wavelength λ of the main track 2 similarly to the main track detecting head 31. Constitute.

Similarly to the above, the phase modulation signal S ₁ obtained at the output side of the phase detection circuit 43 is supplied as address information to the PSK demodulation circuit 44 for obtaining the 3 bits b _{0 to} b ₂ from the bottom. . In this case, when the phase modulation signal S of the main track is S = sin (ωt + 2πx / λ), this phase modulation signal S ₁ is represented by S ₁ = sin (ωt + 2πx / λ + φ (d ₁ )) (6) be able to.

The phase amount φ (d ₁ ) in the equation (6) is the address information, and the phase amount φ corresponding to this address information φ
The PSK demodulation circuit 44 for detecting (d ₁ ) is configured as shown in FIG. 7, for example. To explain FIG. 7,
In FIG. 7, the phase differentiating signal S having the carrier frequency f supplied to the S signal input terminal 41i is supplied to the synchronous differentiating circuit 44.
The clock signal CK ₂ of frequency 8f supplied to the clock signal input terminal 44i is supplied to this synchronous differentiating circuit.

Synchronized with the rising (or falling) of the phase modulation signal S obtained at the output side of the synchronous differentiating circuit 44a, eight times the carrier frequency of the phase modulation signal S,
That is, the one-cycle time width pulse Ds of the clock signal CK _{2 having} the frequency of 8f is supplied to the J terminal of the JK flip-flop circuit 44c which constitutes the phase comparison circuit.

Further, the phase modulation signal S ₁ supplied to the address signal input terminal 44h is supplied to the synchronous differentiating circuit 44b and the frequency 8f supplied to the clock signal input terminal 44i.
The clock signal CK ₂ is supplied to the synchronous differentiating circuit 44b. Obtained at the output side of the synchronous differentiator 44b, synchronized with the rising edge of the phase-modulated signals S ₁ (or falling) of 8 times the frequency 8f of the carrier frequency of the phase-modulated signals S ₁ of the clock signal CK ₂ One cycle time width pulse D
r ₁ The frequency supplied to the clock input terminal ck of the J-K flip-flop circuit 44c to the clock signal input terminal 44i is supplied to the K terminal of the J-K flip-flop circuit 44c which constitutes the phase comparator circuit 8f of The clock signal CK ₂ is supplied.

It is obtained at the output side of this phase comparison circuit 44c.
Phase modulation signal S and phase modulation signal S ₁Phase difference with φ
A pulse width modulation signal W having a pulse width corresponding to (d)
_SIs obtained. This is obtained on the output side of the phase comparison circuit 44c.
Pulse width modulated signal W_SOf the AND gate circuit 44d
This AND gate circuit is supplied to one input terminal
The clock signal input terminal 44i is connected to the other input terminal of 44d.
Clock signal CK of frequency 8f supplied to₂Supply
Like

By the way, this processing is an operation for detecting the difference in phase difference between the phase modulation signal S and the phase modulation signal S _1, and the pulse width of the pulse width modulation signal W _S output from the phase comparison circuit 44c is the first. No. 1 track detection head 32
The value is a constant value φ (d) as long as the position does not change over one λ section, that is, the position of the first address track detection head 32 is located in the same λ section.

That is, for example, in FIG. 3, as long as the position Xa of the first address track detection head 32 is located in the λ section d1,4, the pulse width of the pulse width modulation signal W _S has a phase difference of 135 °. The pulse width modulation signal W _S changes from 0 ° to 315 ° at 45 ° intervals when the position Xa changes from λ period d1,4 to λ period d1,1 to d1,7. It has a pulse width corresponding to eight ways. on the other hand,
The synchronization time of the pulse width corresponding to the phase difference of 360 ° corresponds to one cycle time T (= 1 / f) of the carrier frequency f.

Therefore, when this pulse width modulation signal W _S is supplied to the AND gate circuit 44d together with the clock signal CK ₂ , a pulse train signal P _S having a frequency of 8f and a number varying from 0 to 7 can be obtained. .

The pulse train signal P _S obtained at the output side of the AND gate circuit 44d is generated every time the rising edge (or the falling edge) of the phase modulation signal S generated prior to the pulse train signal P _S is input. by counting in octal counter 44f that is configured to be reset by the signal CL, for each period of the phase modulation signal, the phase difference phi 2 binary code 3 bits corresponding to the (d) Q _a ~Q _c
Can be demodulated.

[0048] supplying a binary code Q _a to Q _c of 3 bits of the octal counter 44f to the code converting circuit 44g for converting a binary code as shown in Table 1, the code conversion circuit 44
As shown in Table 1 on the output side of g, it is possible to obtain the address information of the code system in which the numerical representations of two consecutive numbers differ only in one code position, that is, the address information b _{0 to} b ₂ of the lower 3 bits. .

[0049]

[Table 1]

[0050] may be used as a binary code Q _a to Q _c, but when using such coding system shown in Table 1, the detection is easy to error detection in the demodulation system, reliable The system can be easily constructed.

In this example of FIG. 7, an octal counter 44f for counting with a binary code and a code converting circuit 44g are combined to demodulate address information, but if an octal counter for counting with a code shown in Table 1 is used. This code conversion circuit 44g becomes unnecessary.

The address information b _{0 to} b ₂ of the lower 3 bits obtained at the output side of the code conversion circuit 44g is supplied to the absolute address generation circuit 51.

Further, in the same manner as described above, the phase modulation signals S ₂ , S ₃ and S ₄ obtained at the respective output sides of the equal phase detection circuits 45, 47 and 49 are respectively used as address information from the bottom 4
6 bit b ₃ ~b _5, 7~9 bit b ₆ ~b ₈ and 1
0-12 supplies each bit b ₉ ~b ₁₁ PSK demodulating circuit 46, 48 and 50 for obtaining a signal.

In this case, the phase modulation signals S ₂ , S ₃ and S
₄ can be expressed as follows. S ₂ = sin (ωt + 2πx / λ + φ (d ₂ )) S ₃ = sin (ωt + 2πx / λ + φ (d ₃ )) S ₄ = sin (ωt + 2πx / λ + φ (d ₄ )) The phase amount φ (d ₂ ) in the above equation , Φ (d ₃ ), φ
Each of (d ₄ ) is address information, and as the PSK demodulation circuits 46, 48 and 50 for detecting the address information, the same ones as the PSK demodulation circuit 44 shown in FIG. 7 can be used.

Further, in this case, the output of the PSK demodulation circuit 46
The address information obtained on the side of the 12-bit address information is
4 to 6 bits from the bottom b₃~ B_Five3 bits, PS
The address information obtained at the output side of the K demodulation circuit 48 is 12 bits.
7-9 bits from the bottom of the address information₆~ B₈of
It is 3 bits and is obtained at the output side of the PSK demodulation circuit 50.
The address information is 10 from the bottom of the 12-bit address information.
~ 12 bits b₉~ B ₁₁Is 3 bits.

Of the PSK demodulation circuits 46, 48 and 50
Address information b obtained on each output side ₃~ B_Five, B₆~ B
₈And b₉~ B₁₁To the absolute address generation circuit 51, respectively.
It

FIG. 8 shows a configuration example of this absolute address generation circuit 51.
Shown in. In the example of this FIG.
Data D of absolute position x with resolution of 1 μm within wavelength λ
(R) is supplied to the latch circuit 51a and PSK demodulation
12 bits from the output side of the circuits 44, 46, 48 and 50
Street address information b₀~ B₂, B₃~ B_Five, B₆~ B₈as well as
b ₉~ B₁₁Is supplied to the latch circuit 51b.

The output signal of the latch circuit 51a is supplied to the adder 51e, and the output signal of the latch circuit 51b is supplied to the adder 51e via the weight multiplication circuit 51c. On the other hand, the timing signal generating circuit 51d is supplied with the phase modulation signal S from the main track 2 and the clock signal CK of frequency 200f, and the latch pulse L _P is generated at the timing of the rising (or falling) position of the phase modulation signal S.
Is generated, and the data input to the latch circuits 51a and 51b is latched at the timing of the latch pulse L _P.

The 12-bit address information from the latch circuit 51b is supplied to the weight multiplication circuit 51c, which corresponds to a reproduction wavelength λ of the main track 2, for example, 0.2 mm, and λ (for example, 0.2).
(mm) and multiplied by the adder 51e with the absolute position information within the wavelength λ from the latch circuit 51a.
The absolute position information ADP having a resolution of 1 μm is obtained on the output side of e.

In this example, the absolute position information ADP obtained at the output side of the adder 51e is converted into the serial / parallel conversion circuit 5
1f and a data conversion clock pulse DCK from the timing signal generation circuit 51d are supplied, and the serial data ADS of the absolute position information ADP and the data conversion clock signal SCK suitable for the interface are supplied from the serial / parallel conversion circuit 51f. Make it output.

In the absolute address generation circuit 51 of this example, the absolute data ADP output in units of resolution is converted into serial data ADS, but the parallel data can be used as it is, and the absolute address generation circuit 51 is also available.
Mainly has an arithmetic function, and can also be realized by using a microcomputer or the like.

Since this example is constructed as described above, for example, four address tracks 3, 4, 5 and 6 are used as the main track 2.
The same λ section, 8λ section, 64λ section, and 512λ section as the reproduction wavelength λ (0.2 mm) of the main track 2 are divided into information units.
A signal having the same wavelength λ and having a phase difference of 45 ° obtained by dividing the phase amount 2π into 8 (= 2 ³ ) ways based on the reproduction signal of the main track 2 according to the address information to be recorded. Since recording is performed so as to be obtained, it is possible to obtain a highly reliable absolute position with a high resolution of 1 μm in a section of 819.2 mm among the four address tracks 3, 4, 5 and 6.

According to this example, since the number of address tracks can be small, the scale 1 can be downsized, and the structure of this absolute scale device can be simplified and the cost can be reduced. The main truck 2 and the address trucks 3, 4,
Since both 5 and 6 are based on the same principle of phase detection method, the detection heads 31, 32, 33, 34 and 35 can be easily integrated, and the absolute scale device can be downsized and the cost can be reduced.

Further, according to this example, the address tracks 3, 4,
Since the wavelengths of the signals recorded on the tracks 5 and 6 are selected to be the same as the reproduction wavelength λ of the main track 2, the address tracks 3,
There is less interference with the main track 2 than 4, 5, and 6.
Therefore, there is an advantage that the pitch between tracks can be narrowed without sacrificing the stability, and the scale 1 can be downsized and the main track 2 can be highly accurate.

In the above embodiments, the present invention is applied to the magnetic scale 1 having a reproduction wavelength λ of 0.2 mm to realize an absolute scale device having a resolution of 1 μm. Detection circuit 41
Further, by setting the clock signal CK and the 200-ary counter 42e in the λ-internal position detection circuit 42 to appropriate values as necessary, any resolution can be realized. For example, the clock signal CK is 100f and the counter 42e is 1
If it is a 00-base counter, the resolution is 1/100, 2 μm
Is obtained.

In the above embodiment, the number M of the address tracks is set to 4, but the number M of tracks is arbitrary depending on the effective length and resolution required for the absolute scale device, the reproduction wavelength of the main track 2 and the like. Can be decided.

In the above embodiment, the address tracks 3, 4,
As the address information to be recorded in 5 and 6, recording was performed so that a signal having a phase difference of 45 ° obtained by dividing the phase amount 2π into 8 (= 2 ³ ) ways (N ways) based on the reproduction signal of the main track 2 was obtained. but, this n n-way good the number as necessary 3 above, on the relationship between 2 ⁿ which performs digital processing (n is 2 or more) is preferably.

In the above description, since N = 8, the clock signal CK ₂ is 8f and the counter 44f is an octal counter. For example, when N = 16, CK2 is 16f and the counter 44f is hexadecimal. Also, the phase difference φ (d
_In order to detect stably even if _n ) (here, n = 1, 2, 3, ...) Has a variation, the frequency of the clock signal CK ₂ is (N × M) f (M is a positive integer), The counter 44f may be an (N × M) base counter, and the code conversion circuit 44g may be a predetermined conversion code. For example, when N = 8 and M = 4, M (4) pulses P _S are normally generated for 2π / N = 2π / 8 = 45 ° of φ (d ₁ ).
When φ (d ₁ ) has an error, 3 or 5 pulses P _S may be generated. Therefore, 44f (N ×
The output of the M) -adic counter (32-adic counter) is counted by the code conversion circuit 44g and the count number M ± 1 (3 to 5) is set to No. 1 in Table 1. When code conversion is performed so that b ₂ : b ₁ : b ₀ = 0: 0: 1 of 2, φ (d ₁ ) = 45 ° ± 45
An error of the phase difference can be allowed in the range of ° / M = ± 11.25 °. Further, for φ (d ₂ ) = 90 °, the count numbers 7 to 9 of the (N × M) base counter (32 base counter) are shown in Table 1. 3 b ₂ : b ₁ : b ₀ = 0: 1:
If the code is converted to be 1, φ (d ₂ ) = 90 °
It is possible to allow a phase difference error within a range of ± 11.25 °. Similarly, up to φ (d ₇ ) can be allowed.

In the above embodiment, the magnetic scale 1
Although an example of an absolute scale device using a magnetoresistive effect type magnetic head has been described above, a magnetic flux response type magnetic head may be used as described above, but in this case, the excitation signal frequency is f / 2 and the phase is It is necessary to provide a bandpass filter after the addition output of the modulation signals. Further, the present invention can be applied in the same manner as described above to an electromagnetic induction type scale device such as an inductosyn, a resolver or the like, which extracts the relative movement amount between the scale part and the detection part in the form of a phase modulation signal.

Also, in an optical scale device that outputs a two-phase signal having a 90 ° phase difference according to the relative movement of the scale part and the detection part, this two-phase signal is converted into a two phase signal having a 90 ° phase difference. The present invention can be applied if the displacement amount is extracted as a phase modulation signal by means such as modulation with the phase carrier frequency.

The present invention is not limited to the above-mentioned embodiments, and it goes without saying that various other configurations can be adopted without departing from the gist of the present invention.

[0072]

According to the present invention, it is possible to obtain an absolute scale device capable of obtaining an absolute position with high resolution and high reliability with relatively few address tracks.

According to the present invention, since the number of address tracks is at least good, the scale can be downsized, and the structure of this absolute scale device can be simplified and the cost can be reduced.

Further, according to the present invention, since the main track and the address track are based on the same principle of phase detection method, the detection heads can be easily integrated, and the absolute scale device can be downsized and the cost can be reduced.

Further, according to the present invention, since the reproduction wavelength of the signal recorded on the address track is selected to be the same as the reproduction wavelength λ of the main track, there is less interference from the address track to the main track. Therefore, there is an advantage that the pitch between the tracks can be narrowed without sacrificing the stability, and the scale can be made smaller and the accuracy of the main track can be made compatible.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing an embodiment of an absolute scale device of the present invention.

FIG. 2 is a diagram for explaining the present invention.

FIG. 3 is a diagram for explaining the present invention.

FIG. 4 is a diagram for explaining the present invention.

FIG. 5 is a configuration diagram showing an example of a phase detection circuit.

FIG. 6 is a configuration diagram showing an example of a λ internal position detection circuit.

FIG. 7 is a configuration diagram showing an example of a PSK demodulation circuit.

FIG. 8 is a configuration diagram showing an example of an absolute address generation circuit.

[Explanation of symbols]

1 Magnetic scale 2 main trucks No. 3, 4, 5, 6 trucks 31 Main track detection head Track detection head at address 32, 33, 34, 35 41, 43, 45, 47, 49 Phase detection circuit 42 λ position detection circuit 44,46,48,50 PSK demodulation circuit 51 Absolute address generation circuit

Front page continuation (58) Fields surveyed (Int.Cl. ⁷ , DB name) G01B 7/00 G01D 5/245

Claims (4)

(57) [Claims] 1. A main track recorded so as to output an incremental signal having a wavelength λ, and a relative displacement amount between the main track and a main track detection head is extracted as a phase modulation signal according to a moving amount to obtain a reproduction wavelength. A main track signal detecting means for detecting a position in λ as an absolute value, and a section which is the same as the reproduction wavelength λ of the main track or a section which is an integral multiple thereof is divided as an information recording unit. It has the same wavelength as the reproduction wavelength λ of the track, and the phase amount 2π is N (N is an integer of 3 or more) based on the reproduction signal of the main track according to the address information to be recorded.
The M (M is a positive integer) number of address tracks recorded so that the signals having the phase difference divided as described above are output, and the main track detection head corresponding to the M number of address tracks. An address signal detecting means for demodulating address information from a detection signal from an address track detecting head, an absolute value within a reproduction wavelength λ obtained from the main track signal detecting means, and address information obtained from the address signal detecting means. An absolute scale device characterized by comprising an absolute address generating means for correcting and combining weights. 2. The absolute scale device according to claim 1, wherein the main track signal detecting means determines a relative displacement amount between the main track and the main track detecting head as a carrier frequency f.
Of the carrier frequency f by using the signal of the carrier frequency f as a reference signal for phase comparison,
Obtaining a pulse width modulation signal whose pulse width changes corresponding to the position of the main track detection head within the reproduction wavelength λ,
The pulse width modulated signal is interpolated with a clock pulse having a frequency K times that of the reference signal, converted into a pulse train signal corresponding to a position within the reproduction wavelength λ, the pulse train signal is counted, and the main track is recorded. The absolute scale device is characterized in that the position resolution within the reproduction wavelength λ can be detected as the absolute value of R = λ / K. 3. The absolute scale device according to claim 1, wherein the signal recorded on the address track changes the phase of a carrier frequency f corresponding to the amount of relative displacement between the address track and the address track detection head. A pulse width change corresponding to N kinds of phase differences recorded on the address track by taking out as a modulation signal and comparing the phase modulation signal with a phase modulation signal of a carrier frequency f obtained from the main track. A pulse width modulation signal is obtained, demodulated as N kinds of information recorded on the address track, and address information is generated from the N kinds of information, an azosolute scale device. 4. The absolute scale device according to claim 1, wherein the N is 2 to the n-th power (n is an integer of 2 or more).