JP3417842B2 - Method and apparatus for designing a field effect transistor model - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method and apparatus for designing a field effect transistor model, and more particularly to a high frequency circuit design apparatus including a field effect transistor model for circuit simulation.

[0002]

2. Description of the Related Art A high-frequency circuit design apparatus (simulator) incorporates various models of active elements and passive elements, and it is a necessary condition that each model can reproduce realistic characteristics. At present, various models have been proposed for the drain current included in the large-signal model for GaAs MESFETs that are often used as high-frequency active elements. For example, Curtis quadratic model, Curtis cubic model, Materka (M
Aterka) model, Stats model, etc. The number of parameters related to transconductance, which is very important in design, that is, the number of parameters related to gate voltage, is two in the second model of Curtis and three in the third model of Curtis.
Two Materka models, Stats
) There are 3 models. Not surprisingly, the fitting accuracy of these models for the measured values is higher for the Curtis third-order model and the Statz model than the other two models. On the other hand, the number of parameters related to drain conductance as important as transconductance, that is, the number of parameters related to drain voltage is one in the unsaturated region and one in the saturated region in any model. Therefore, these conventional models have a problem that the fitting accuracy of the drain conductance is inferior to the fitting accuracy of the transconductance.

As for the capacitance model, a model that can be introduced into a circuit model assumes a uniform impurity concentration distribution, and if it is applied to a non-uniform concentration distribution such as that formed by ion implantation, it greatly increases. There was a problem that the accuracy deteriorated.

[0004]

A drain current model capable of accurately expressing not only transconductance but also drain conductance characteristics and a capacitance model capable of coping with a channel layer having a nonuniform impurity concentration are provided. It is an object of the present invention to provide a design device that can be provided and can perform simulation with higher accuracy.

[0005]

According to the present invention, there is provided a method of designing a field effect transistor model used for designing a high frequency integrated circuit, comprising a measuring step of measuring a drain current, a gate voltage and a drain voltage of the field effect transistor model. , The drain current based on the drain current value and the gate voltage value and the drain voltage value measured in the measuring step , the first coefficient term, the second coefficient
A first-order product term of a coefficient and the gate voltage, and a third coefficient
The second-order product term of the gate voltage, the fourth coefficient, and the gate
Of the third order of the gate voltage, and the first order to be multiplied by the different order terms of the gate voltage to fit a third order equation represented by the product of the trigonometric function of the drain voltage .
To Drain where the fourth to fourth coefficients are different coefficients
Each term, as represented by multiple linear expressions for voltage
A coefficient calculation step of calculating the coefficients in parallel at the same time,
Each coefficient obtained by the coefficient calculation step
According to the third order equation and the first order equation
Model calculation step for calculating a flow model, and the model
And a replacement step of replacing with 0 when the value of the drain current calculated in the calculation step becomes negative.

Further, the cubic equation for _obtaining the drain current is such that when the drain current is I _ds , the gate voltage is V _gs , and the drain voltage is V _ds , the first equation
Is expressed by the following expression (A) including the coefficients A ₀ , A ₁ , A ₂ , and A ₃ which are the fourth coefficients, and the plurality of linear expressions that are further operated in parallel are the following expressions (B1) to (B1) B4) I _ds = (A ₀ + A ₁ V _gs + A ₂ V _gs ² + A ₃ V
_gs ³ ) tanh (γV _ds ) ... (A) A ₀ = A ₀₀ + A ₀₁ V _ds (B1) A ₁ = A ₁₀ + A ₁₁ V _ds (B2) A ₂ = A ₂₀ + A ₂₁ V _ds (B3) ) it is characterized in that represented by _{a 3 = a 30 + a 31} V ds ... (B4).

Further, in a method of designing a field effect transistor model used for designing a high frequency integrated circuit, a predetermined relation between a drain current, a drain voltage, a gate voltage of the field effect transistor model and an element input / output by a two-terminal measuring method is shown. a measuring <br/> step of measuring the S parameters, respectively, the measured measured gate-drain voltage in step, the gate-source capacitance which is calculated from the voltage and S parameters between the gate and the source, a first coefficient section,
The primary product term of the second coefficient and the gate-source voltage, third
Second term of the coefficient of the coefficient and the voltage between the gate and the source , the fourth relation
The sum of the number and the first-order product term of the gate-drain voltage
To fit the quadratic equation, the coefficients of the first to fourth
A coefficient calculation step of calculating a parallel simultaneously, the engagement
Has the first to fourth coefficients obtained in the numerical calculation step
Capacitance calculation that calculates the gate-source capacitance by a quadratic equation
Location where the calculation step, the value of the gate <br/> Tososu capacitance calculated by the capacity calculation step replaces at 0 when a negative
And a replacement step.

Further, the gate-source capacitance is calculated 2
The following equation is based on the _assumption that the gate-source capacitance is C _gs and the intrinsic gate-source voltage V _g0 and the intrinsic gate-drain voltage V _g
As the expression of _gd, the following expression C _gs = C _s1 + C _s2 V _g0 + C _s3 V _g0 ² including the coefficients C _s1 , C _s2 , C _s3 , and C _s4 as the first to fourth coefficients. + C
It is characterized by being _s4 V _gd .

Further, in a method of designing a field effect transistor model used for designing a high frequency integrated circuit, a predetermined relation between a drain current, a drain voltage, a gate voltage of the field effect transistor model and an element input / output by a two-terminal measuring method is shown. a measuring <br/> step of measuring the S parameters, respectively, the measured gate-drain voltage in the measuring step, the gate-drain capacitance calculated from the voltage and S parameters between the gate and the source, the first coefficient
Term, the second coefficient and the first-order product of the gate-drain voltage
Term, the second coefficient and the quadratic product of the gate-drain voltage
Term, the term of the first-order product of the fourth coefficient and the gate-source voltage ,
In order to fit a quadratic equation that is the sum of
A coefficient calculation step for calculating each of them in parallel at the same time and a coefficient having a coefficient calculated in the coefficient calculation step.
Model operation to calculate the quadratic equation of the capacitance model between gate and drain
The method further comprises a calculation step and a replacement step of replacing with 0 when the value of the gate-drain capacitance calculated in the model calculation step becomes negative.

[0010] 2 linear equation for evaluating the gate-drain capacitance, the gate-drain capacitance and C _gd, as an expression of the gate-source voltage V _g0 gate-drain voltage V _gd and the intrinsic intrinsic, to the first free The following formula C _gd = C _d1 + C _d2 V _gd + C _d3 V _gd ² + C including the respective coefficients C _d1 , C _d2 , C _d3 , and C _d4 as the fourth coefficient.
It is characterized in that it is _d4 V _g0 .

The field-effect transistor is a GaAs formed on a semi-insulating substrate of gallium arsenide compound.
It is characterized by being a field effect transistor.

The field effect transistor is a GaAs formed on a semi-insulating substrate of gallium arsenide compound.
It is characterized by being a MESFET.

Further, high frequency integrated circuit drain current of the field effect transistor model used in the design, the field effect transistor design models for determining the coefficients for each value of electrical data to set the optimum value of the gate voltage and the drain voltage In the device, a drain current measuring means for measuring a drain current of the field effect transistor model, a gate voltage measuring means for measuring a gate voltage of the field effect transistor model, and a drain voltage for measuring a drain voltage of the field effect transistor model. measuring means, the drain current measuring means, the drain current is <br/> measure respectively the gate voltage measuring means and a drain voltage measuring means, based on the gate voltage and the drain voltage, the drain current, the first Coefficient of
Term, second-order coefficient and first-order product term of the gate voltage, third
The second-order product term of the coefficient and the gate voltage, and the fourth coefficient
Multiplying terms of different gate voltages to fit a cubic equation represented by the product of the third-order product term of the gate voltage and the trigonometric function of the drain voltage.
In different coefficients of the first to fourth coefficients including
Represented by multiple linear equations for a given drain voltage
So that the first to fourth coefficients are simultaneously and in parallel.
Calculated by coefficient calculating means and the coefficient calculating means
The cubic equation and the 1
A model calculator that calculates the drain current model using the following formula
And a replacement unit for replacing the drain current calculated by the model calculation unit with 0 when the drain current value becomes negative.

Further, in a field effect transistor model design apparatus for obtaining a coefficient for each electric data value in order to set a field effect transistor model used for designing a high frequency integrated circuit, the drain current of the field effect transistor model is calculated. Drain current measuring means for measuring, drain voltage measuring means for measuring drain voltage of the field effect transistor model, gate voltage measuring means for measuring gate voltage of the field effect transistor model, and S parameter of the field effect transistor model and S parameter measuring means for measuring the drain current measuring means, the drain voltage measuring means, the gate-drain voltage was measured respectively by the gate voltage measuring unit and the S parameter measurement unit, or the gate-source voltage and S parameters The calculated gate-source capacitance,
The first coefficient term, the second coefficient and the gate-source voltage of 1
Next product term, third coefficient and second-order product of gate-source voltage , fourth-order coefficient and first-order product of gate-drain voltage
Sections to fit the quadratic equation is the sum of said first
To a coefficient calculating means for obtaining a fourth coefficient in parallel simultaneously, the first to fourth engagement of which is obtained by the coefficient calculation means
Calculate gate-source capacitance by quadratic equation with number
It is characterized in further comprising a capacity calculation unit, and a replacement <br/> means for replacing at 0 when the value of the gate-source capacitance which is calculated by the volume calculating means is negative.

Further, in a field effect transistor model design apparatus for obtaining a coefficient for each electric data value in order to set a field effect transistor model used for designing a high frequency integrated circuit, a drain current of the field effect transistor model is calculated. Drain current measuring means for measuring, drain voltage measuring means for measuring drain voltage of the field effect transistor model, gate voltage measuring means for measuring gate voltage of the field effect transistor model, and S parameter of the field effect transistor model Is calculated from the S-parameter measuring means for measuring, and the gate-drain voltage, the gate-source voltage and the S-parameter measured by the drain current measuring means, the drain voltage measuring means, the gate voltage measuring means and the S-parameter measuring means. And the gate-drain capacitance, the first
The coefficient of the term, first-order product terms of the second coefficient and the gate-drain voltage, a secondary product of the second coefficient and the gate-drain voltage
Sections 1 order term of the product of the fourth coefficient and the gate-source voltage
The first to to fit the quadratic equation as a sum of
Coefficient calculating means for simultaneously calculating each of the four coefficients in parallel, and a controller having the coefficient calculated by the coefficient calculating means.
Model operation to calculate the quadratic equation of the capacitance model between gate and drain
Location where the calculation means, the values of the gate-drain capacitance calculated by the model arithmetic operation step is replaced by 0 when a negative
And a replacement means.

As described above, according to the present invention, in the large-signal model of the field effect transistor which is an active element, the parameter value can be quickly obtained from the measured value by the least square method, and the fitting current has a high fitting accuracy. To enable high-precision circuit simulation.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Prior to the description of the embodiments of the present invention, the basic concept of the present invention will be described first. The present invention evaluates the parasitic source resistance R _s and the parasitic drain resistance R _d from the S parameter measurement value of the field effect transistor, and the drain current I for a plurality of gate voltages V _g and drain voltage V _d .
_d is measured and calculated by the intrinsic gate voltage V _g0 V _g −R _s × I _d , and the intrinsic drain voltage V _d0 is V _d − (R _s + R
_d ) × I _d , and 8 or more pairs of (V _g0 , V _d0 , I _d ) are obtained for the drain current in the saturation region, and 8 ×
The n rows and m columns of elements of the matrix A of 8 as a _mn, a ₁₁ is the number of data, the sum of a ₁₂ is V _d0, a ₁₃ is the sum of V _g0, a ₁₄ is V
_g0 V _d0 sum, a ₁₅ V _g0 ² sum, a ₁₆ V _g0 ² V _d0
, A ₁₇ is the sum of V _g0 ³ , a ₁₈ is the sum of V _g0 ³ V _d0 , a ₂₁ is the sum of V _d0 , a ₂₂ is the sum of V _d0 ² , and a ₂₃ is V.
_g0 V _d0 sum, a ₂₄ V _g0 V _d0 ² sum, a ₂₅ V _g0 ²
The sum of V _d0 , a ₂₆ is the sum of V _g0 ² V _d0 ² , and a ₂₇ is V _g0 ³
A sum of V _d0 , a ₂₈ is a sum of V _g0 ³ V _d0 ² , a ₃₁ is a sum of V _g0 , a ₃₂ is a sum of V _g0 V _d0 , a ₃₃ is a sum of V _g0 ² , a
₃₄ is the sum of V _g0 ² V _d0 , a ₃₅ is the sum of V _g0 ³ , and a ₃₆ is V
_g0 ³ V _d0 sum, a ₃₇ V _g0 ⁴ sum, a ₃₈ V _g0 ⁴ V
_d0 summation, a ₄₁ summation of V _g0 V _d0 , a ₄₂ summation of V _g0 V _d0 ² , a ₄₃ summation of V _g0 ² V _d0 , a ₄₄ summation of V _g0 ² V _d0 ² , a ₄₅ Is the sum of V _g0 ³ V _d0 , a ₄₆ is the sum of V _g0 ³ V _d0 ² , a ₄₇ is the sum of V _g0 ⁴ V _d0 , a ₄₈ is the sum of V _g0 ⁴ V _d0 ² , and a ₅₁ is V _g0 ² , A ₅₂ is the sum of V _g0 ² V _d0 ,
a ₅₃ is the sum of V _g0 ³ , a ₅₄ is the sum of V _g0 ³ V _d0 , a ₅₅ is the sum of V _g0 ⁴ , a ₅₆ is the sum of V _g0 ⁴ V _d0 , and a ₅₇ is V _g0 ⁵
, A ₅₈ is the sum of V _g0 ⁵ V _d0 , a ₆₁ is the sum of V _g0 ² V _d0 , a ₆₂ is the sum of V _g0 ² V _d0 ² , a ₆₃ is the sum of V _g0 ³ V _d0 , a ₆₄ Is the sum of V _g0 ³ V _d0 ² , a ₆₅ is the sum of V _g0 ⁴ V _d0 , a ₆₆ is the sum of V _g0 ⁴ V _d0 ² , a ₆₇ is the sum of V _g0 ⁵ V _d0 , and a ₆₈ is V _g0 ⁵ A sum of V _d0 ² , a ₇₁ is a sum of V _g0 ³ , a ₇₂ is a sum of V _g0 ³ V _d0 , a ₇₃ is a sum of V _g0 ⁴ , a
₇₄ is the sum of V _g0 ⁴ V _d0 , a ₇₅ is the sum of V _g0 ⁵ , and a ₇₆ is V
_g0 ⁵ V _d0 sum, a ₇₇ V _g0 ⁵ sum, a ₇₈ V _g0 ⁶ V
The sum of _d0 , a ₈₁ is the sum of V _g0 ³ V _d0 , and a ₈₂ is V _g0 ³ V _d0
² sum, a ₈₃ is V _g0 ⁴ V _d0 sum, and a ₈₄ is V _g0 ⁴ V _d0
² sum, a ₈₅ is V _g0 ⁵ V _d0 sum, and a ₈₆ is V _g0 ⁵ V _d0
² sum, a ₈₇ is V _g0 ⁶ V _d0 sum, and a ₈₈ is V _g0 ⁶ V _d0
^When the inverse matrix A ^{−1 of the} matrix that is the sum of ² is obtained, and b _n is the element in the nth row of the 8 × 1 matrix B, b ₁ is the sum of I _d and b ₂ is the value of I _d V _d0 Sum, b ₃ is the sum of I _d V _g0 , b
₄ is the sum of I _d V _g0 V _d0 , b ₅ is the sum of I _d V _g0 ² , b
₆ is the sum of I _d V _g0 ² V _d0 , b ₇ is the sum of I _d V _g0 ³ ,
A matrix B is obtained in which b ₈ is the sum of I _d V _g0 ³ V _d0 , and then the product of the matrices of A ⁻¹ and B is obtained, and the n-th row element of the obtained 8 × 1 matrix D is d. The drain current in the equivalent circuit model as _n is (d ₁ + d ₂ V _d0 ) + (d ₃ + d ₄ V _d0 ) V _g0 +
(D _s + d ₆ V _d0 ) V _g0 ² + (d ₇ + d _s V _d0 ) V _g0 ³
The field effect transistor model that can be expressed by is designed.

After evaluating the parasitic source resistance R _s and the parasitic drain resistance R _d by measuring the S parameter of the field effect transistor, the drain voltage V _d -drain current I _d is measured for a plurality of gate voltages V _g . and the gate voltage V _g0 intrinsic calculated by V _g -R _s × I _d, the drain voltage of the intrinsic a V _d0 V _d - calculated in _{(R s + R d) ×} I d,
For the drain current in the saturation region, (V _g0 , V _d0 ,
I _d ), eight or more sets are created, and parameters d ₁ , d ₂ ,
Using d ₃ , d ₄ , d ₅ , d ₆ , d ₇ , and d ₈ , f = I <sub>d
- {(d 1 + d 2</sub> V d0) + (d 3 + d 4 V d0) V g0 +
_{(D 5 + d 6 V d0} ) V g0 2 + (d 7 + d 8 V d0)
V _g0 ³ }, the sum of the values obtained by partially differentiating the square of f with d ₁ , the sum of the values obtained by partially differentiating the square of f with d ₂ , and the sum of the values obtained by partially differentiating the square of f with d _3. , The sum of the values obtained by partially differentiating the square of f by d ₄ , the sum of the values obtained by partially differentiating the square of f by d ₅ , the sum of the values obtained by partially differentiating the square of f by d ₆ , and the square of f the sum of the partial differential value in d _7, the square of f so that the sum of values value obtained by partially differentiating in d ₈ are all 0, the parameters _{d 1, d 2, d 3} , d 4, d 5, d ₆ , d ₇ , d
₈ is obtained, and the drain current inside the equivalent circuit is (d ₁ + d ₂ V _d0 ) + (d ₃ + d ₄ V _d0 ) V _g0 + (d ₅
It is also possible to design a field effect transistor model that can be expressed as + d ₆ V _d0 ) V _g0 ² + (d ₇ + d ₈ V _d0 ) V _g0 ³ .

Further, in the field effect transistor model used for the high frequency IC design, the drain current I _ds is _expressed as (d ₁ + d ₂ V _d0 ) + (d ₃ + d) as an equation of the intrinsic gate voltage V _g0 and the intrinsic drain voltage V _{d0. 4} V _d0 ) V _g0 + (d <sub>5
+ D 6 V d0) V g0</sub> 2 + ( expressed as _{d 7 + d 8 V d0)} V g0 3, determined by the least square method from the further drain voltage Drain current characteristics measured these coefficients, if calculated by these formulas A field effect transistor model may be designed by incorporating a drain current model that is replaced with 0 when the calculated value becomes negative.

After evaluating the parasitic source resistance R _s and the parasitic drain resistance R _d by measuring the S parameter of the field effect transistor, the drain current I _d is measured for a plurality of gate voltages V _g and drain voltages V _d . and the gate voltage V _g0 intrinsic calculated by V _g -R _s × I _d, the drain voltage of the intrinsic a V _d0 V _d - calculated in _{(R s + R d) ×} I d,
The voltage between the gate and the drain is obtained by setting V _gd as V _g0 −V _d0 ,
The gate-source capacitance C _gs and the gate-drain capacitance C _gd are calculated from the S parameter measurement for a plurality of V _g0 and V _ds , and (V _g0 , V _gd , V _gs ) and (V _g0 , V _gd , C _gd ) seeking set of four or more, respectively, the elements of n rows and m columns of the matrix a of 4 × 4 as a _mn, a ₁₁ is the number of data, the sum of a ₁₂ is V _g0, sum a ₁₃ is V _g0 ² , A ₁₄ is the sum of V _gd , and a ₂₁ is V
sum of _g0, sum a ₂₂ is V _g0 ^2, the sum a ₂₃ is V _g0 ^3,
a ₂₄ is the sum of V _g0 V _gd , a ₃₁ is the sum of V _g0 ² , and a ₃₂ is V
sum of _g0 ³ , a ₃₃ is the sum of V _g0 ⁴ , a ₃₄ is the sum of V _g0 ² V _gd , a ₄₁ is the sum of V _d0 , a ₄₂ is the sum of V _g0 V _d0 , a ₄₃
Is the sum of V _g0 ² V _d0 , and a ₄₄ is the sum of V _d0 ² , the inverse matrix A ⁻¹ is obtained, and the n-th row element of the 4 × 1 matrix B is b.
_{When n} , b ₁ is the sum of C _gs , b ₂ is the sum of C _gs V _g0 , b ₃ is the sum of C _gs V _g0 ² , b ₄ is the sum of C _gs V _d0 ,
Then, the matrix B is obtained, and then the product of the matrices of A ⁻¹ and B is obtained. The n-th element of the obtained 4 × 1 matrix C _s is C _sn ,
The gate-source capacitance in the equivalent circuit model is represented by c _s1 + c _s2 V _g0 + c _s3 V _g0 ² + c _s4 V _d0 , and then the n-th row and m-th element of the 4 × 4 matrix G is set to g _mn and g ₁₁ Is the number of data, g ₁₂ is the sum of V _gd , and g ₁₃ is V _gd
² sum, g ₁₄ sum of V _g0 , g ₂₁ sum of V _gd , g ₂₂
Is the sum of V _gd ² , g ₂₃ is the sum of V _gd ³ , and g ₂₄ is V _gd V _g0
, G ₃₁ is the sum of V _gd ² , g ₃₂ is the sum of V _gd ³ , and
₃₃ is the sum of V _gd ⁴ , g ₃₄ is the sum of V _gd ² V _d0 , and g ₄₁ is V
The inverse matrix G ^-1 of a matrix in which the sum of _g0, the sum of G ₄₂ is the sum of V _g0 V _gd , the g ₄₃ is the sum of V _gd ² V _g0 , and the g ₄₄ is the sum of V _g0 ² , When the n-th row element of the matrix H is h _n ,
h ₁ is the sum of C _gd , h ₂ is the sum of C _gd V _gd , and h ₃ is the C _gd
A matrix H in which the sum of V _gd ² and h ₄ is the sum of C _gd V _g0 is obtained, and then the product of the matrices of G ⁻¹ and H is obtained, and n rows of the obtained 4 × 1 matrix C _d are obtained. The field-effect transistor model may be designed such that the capacitance between the gate and the drain in the equivalent circuit model is represented by C _d1 + c _d2 V _gd0 c _d3 V _gd ² + c _d4 V _g0, where c _dn is the element.

Further, the S-parameter measurements of the field effect transistor, a parasitic source resistance R _s, after evaluating the parasitic drain resistance R _d, measured drain current I _d with respect to a plurality of gate voltage V _g and the drain voltage V _d , The intrinsic gate voltage V _g0 is calculated by V _g −R _s + I _d , the intrinsic drain voltage is calculated by V _d0 −V _d − (R _s + R _d ) × I _d , and the gate-drain voltage is V _{gd. Is calculated} as V _g0 −V _d0 , the gate-source capacitance C _gs and the gate-drain capacitance C _gd are calculated from the S parameter measurement for a plurality of V _g0 and V _ds , and the parameters c _s1 , c _s2 , c _s3 , and c _s4 are calculated. F _gs = c _gs − (c _s1 + c _s2 V _g0 + c _s3 V _g0 ² + c
The square of _s4 V _gd) to become f _gs and the sum of the values obtained by partially differentiating c _s1, f _gs
The sum of the partial differential value in the square c _s2, the square of f _gs c of
_The parameter c is set so that the sum of the values partially differentiated by _s3 and the sum of the values of the square of f _gs partially differentiated by c _s4 are all zero.
_s1 , c _s2 , c _s3 , c _s4 are obtained, and then the capacitance between the gate and the source inside the equivalent circuit is expressed by the drain current by c _s1 + c _s2 V _g0 + c _s3 V _g0 ² + c _s4 V _gd , and the parameters Using c _d1 , c _d2 , c _d3 , and c _d4 , f _gd = c _gd − (c _d1 + c _d2 V _gd + c _d3 V _gd ² + c
_d4 V _g0 ) and the sum of the values of the square of f _gd partially differentiated by c _d1 and f _gd
And the square of f _gd is the sum of the values obtained by partially differentiating the square of c _d2
Parameter c _d1 , so that the sum of the values partially differentiated by _d3 and the sum of the values partially differentiated by the square of f _gd by c _d4 are all 0,
seeking _{c d2, c d3, c d4} , so as to design a field effect transistor models that represent the gate-drain capacitance of the internal equivalent circuit _{c d1 + c d2 V gd +} c d3 V gd 3 + c d4 V g0 Good.

In the field effect transistor model used for high frequency IC design, the gate-source capacitance C _gs and the gate drain capacitance c _gd are _{expressed by} the equations of the intrinsic gate-source voltage V _g0 and the intrinsic gate-drain voltage V _gd . As
Each is represented as c _gs = c _s1 + c _s2 V _g0 + c _s3 V _g0 ² + c _s4 V _gd c _sd = c _d1 + c _d2 V _gd + c _d3 V _gd ² + c _d4 V _g0 , and these coefficients c _s1 and c _s2 , C _s3 , c _s4 ,
C _d1 , c _d2 , c _d3 , and c _d4 are obtained from the measured plurality of gate-source capacitances C _gs and gate-drain capacitance by the least square method, and if the capacitance values calculated by these formulas are negative, In such a case, a field effect transistor model that incorporates a capacitive current model to be replaced with 0 may be designed.

Embodiments for carrying out the basic concept of the present invention described above will be described in detail with reference to FIGS. 1 to 13. FIG. 1 is a flowchart showing a method for designing a field effect transistor model according to the first embodiment of the present invention. In FIG. 1, the FET model is a step
In the ST1 measurement step, the FET drain current, gate voltage, and drain voltage are measured. Next, in the calculation step of step ST2, the measured drain current is applied to a cubic expression including a 0th to 3rd product obtained by multiplying the measured gate voltage by a predetermined coefficient, and the optimum coefficient is set to a plurality of 1's. Calculated in parallel from the following equation.

Next, it is determined in step ST whether the drain current becomes negative from a predetermined coefficient calculated in parallel and in parallel on the basis of the measured drain current, gate voltage and drain voltage.
If it is determined in the determination step 3 and the drain current becomes negative, the drain current is replaced by 0 in the replacement step of step ST4. When it is determined in step ST4 that the drain current is not negative, the field effect transistor model is determined in the determination step of step ST5. In this way, the field effect transistor model used in the high frequency integrated circuit can be designed.

A cubic equation for obtaining the drain current is shown in FIG.
And the drain current is I _ds ,
When the gate voltage is V _gs and the drain voltage is V _ds , it is represented by the following formula (A) including the respective coefficients A ₀ , A ₁ , A ₂ , and A ₃ , and further, the plurality of parallel calculation are performed. The linear expression is represented by the following expressions (B1) to (B4) I _ds = (A ₀ + A ₁ V _gs + A ₂ V _gs ² + A ₃ V _gs ³ ) tanh (γV _ds ) ... (A) A ₀ = A ₀₀ + A ₀₁ V _ds (B1) A ₁ = A ₁₀ + A ₁₁ V _ds (B2) A ₂ = A ₂₀ + A ₂₁ V _ds (B3) A ₃ = A ₃₀ + A ₃₁ V _ds (B4) .

Although the field effect transistor model designing method according to the first embodiment described above is designed so that the FET model is designed from the drain current model, the present invention is not limited to this and designs from the capacitance model. You may do it. FIG. 3 and FIG. 4 are flowcharts showing the method of designing the field effect transistor model according to the second and third embodiments, in which the FET model is designed from the gate source capacitance and the gate drain capacitance, respectively.

In FIG. 3, in step ST11, the drain current, gate voltage, drain voltage and S parameter of the FET are measured. The S parameter is
It is a coefficient indicating a predetermined relationship between the input and output of the element measured by the two-terminal measuring method. In step ST12, the capacitance between the gate and the source is calculated from the measured S parameter, and the predetermined coefficient is calculated in parallel and at the same time by applying the quadratic equation including the predetermined coefficient. The quadratic equation including this predetermined coefficient is the second equation in FIG. Next step ST13
In, it is determined whether the gate-source capacitance is negative,
If it is negative, the value is replaced with 0 (step ST14). If it is not negative, the field effect transistor model is determined from the gate-source capacitance in step ST15.

Although the FET model is designed from the capacitance between the gate and the source in FIG. 3, the gate drain capacitance may be used as shown in FIG. 4 even when the capacitance model is used. In FIG. 4, steps ST21, ST22, ST2
3, ST24 and ST25 are step ST1 of FIG. 3, respectively.
1, ST12, ST13, ST14 and ST15, and the gate-source capacitance in FIG.
The difference between the two is only the capacitance between the gate and the drain.

In the proposed design apparatus, the field effect transistor model is an equivalent circuit model as shown in FIGS. 2 and 5, and the drain current model and the capacitance model incorporated therein are expressed by the equations shown in the drawings. It is represented by. When I _ds , C _gs , and C _gd calculated by this formula have negative values, they are replaced with 0. Here, γ is a parameter indicating the characteristic of the nonlinear region, and
e) Same as that used in the model. Using this model, the parameters d ₁ , d ₂ , d ₃ , d ₄ , d ₅ , d ₆ , from the measured values of the drain current of a self-aligned GaAs MESFET with a gate length of 0.8 μm,
The results of simulating by extracting the values of d ₇ , d ₈ and γ are shown in FIG. The thick line is the calculated value and the thin line is the measured value. The gate voltage is in the range of −0.4 V to 0.5 V at 0.1 V intervals, and the drain voltage is in the range of 0 to 6 V, and the simulation results are in good agreement with the measured values.

On the other hand, FIG. 7 shows the result of simulation using a conventional Curtice cubic model. In this model, the equivalent circuit is the same as that in FIG. 2, and the drain current equation is expressed as I _ds = (A ₀ + A ₁ V ₁ + A ₂ V ₁ ² + A ₃ V ₁ ³ ) ta
Let nh (γV _ds ) V ₁ = V _gs {1 + β (V _ds −V _ds0 )} be the saturation region of the drain current as a function of V ₁ . V ₁ is a function of V _gs , and the drain voltage is the reference V
_{At ds0} , it is equal to the gate voltage V _gs . As V _ds moves away from V _ds0 , the value of V ₁ is modulated by β, and this apparent change in V _gs represents the drain conductance. However, under the condition that V _gs is 0 V, V ₁
Is always 0 regardless of V _ds . Therefore, this equation cannot describe the drain conductance.
Therefore, the drain conductance is fitted by the value of the resistance R _ds connected in parallel with the current source. The drain conductance other than the gate voltage 0 is β-matched, but if the drain conductance is matched in the high gate voltage region, the drain conductance in the low gate voltage region cannot be matched. Therefore, as shown in FIG. 5, in the region where the gate voltage is low and the drain voltage is high, the deviation of the drain conductance from the measured value becomes large.

On the other hand, the present invention is based on the idea that the drain current is expressed by a cubic expression with respect to the gate voltage at any drain voltage, and their coefficients depend on the drain voltage. As a result, both the transconductance and the drain conductance can be accurately reproduced for any drain voltage in the saturation region.

Further, FIGS. 8 and 9 show the calculation results of the capacitance model of the present invention shown in FIG. 2 together with the measured values and the calculated values of the conventional PN junction model. As shown in FIG. 8 for the dependence on the gate-source voltage and as shown in FIG. 9 for the dependence on the gate-drain voltage, the model of the present invention can reproduce the measured values better than the conventional model. I understand.

Next, a field effect transistor model design device according to a fourth embodiment of the present invention will be described with reference to FIG. FIG. 10 shows a device for designing a field effect transistor for obtaining a coefficient for each electric data value in order to set optimum values of a drain current, a gate voltage and a drain voltage of a field effect transistor model used in a high frequency integrated circuit. ing.

In FIG. 10, the design apparatus 10 comprises a drain current measuring means 11 for measuring the drain current of the field effect transistor model and a gate voltage measuring means 12 for measuring the gate voltage of the field effect transistor model.
And drain voltage measuring means 13 for measuring the drain voltage of the field effect transistor model, the drain current measuring means, the gate voltage measuring means, and the drain current, the gate voltage and the drain voltage measured by the drain voltage measuring means. The drain current is calculated by using a first-order product, a second-order product, and 3 of the gate voltage and a predetermined coefficient.
In order to fit a cubic expression represented by the product of the following product and a predetermined coefficient and the trigonometric function of the drain voltage, the predetermined coefficients are simultaneously obtained in parallel by predetermined linear expressions, respectively. A drain current model is calculated by the calculating means 15 for replacing with 0 when the value of the drain current obtained by the following equation becomes negative, and the predetermined coefficient applied to the cubic equation and a plurality of linear equations to be parallelly computed. Circuit simulation executing means 16 for determining.

The device for designing a field effect transistor model according to the fourth embodiment shown in FIG. 10 described above is a device for designing an FET model from a drain current, but the present invention is not limited to this, and a gate source or a gate drain. The FET model may be designed from the capacitance. Figure 1
1 is a block diagram showing the configuration of a field effect transistor model design device according to the fifth embodiment, and is different from FIG. 10 in that an S parameter measuring means 14 is provided. The S parameter is a coefficient indicating a predetermined relationship between the input and the output between the two terminals of the FET. The design apparatus according to the fourth embodiment is applied to the one in which the FET model is designed from only the capacitance model, but the present invention is not limited to this, and both the drain current model and the capacitance model are combined. You may use it.

12 and 11 show the results of simulating the power characteristics using the high frequency circuit simulation shown in FIG. 11 incorporating the drain current model and the capacitance model of the present invention. The source and load impedances were set so that the small signal gain was maximized. The calculated DC current of the output power characteristic was in good agreement with the measured value as shown in FIG. The calculation result of the power load efficiency also showed an extremely good result as shown in FIG.
On the other hand, the calculation results of the conventional Curtice cubic model and the PN junction model show large deviations in the measured values as shown in these figures, and in particular, there is a large deviation of about 20% in the power load efficiency under the condition that the input power is large. occured.

[0037]

As described above, when the drain current and capacitance models according to the present invention and the circuit design device incorporating these models are used, the FET characteristics can be reproduced with high accuracy, and the accuracy of circuit simulation is improved. To do. As a result, it is possible to shorten the period of device development and reduce the number of prototype lots, which greatly contributes to the efficiency of device development.

[Brief description of drawings]

FIG. 1 is a flowchart showing a method for designing a field effect transistor model according to a first embodiment of the present invention.

FIG. 2 is an equivalent circuit diagram showing a field effect transistor model according to the first embodiment of the present invention.

FIG. 3 is a flowchart showing a method for designing a field effect transistor model according to a second embodiment of the present invention.

FIG. 4 is a flowchart showing a method of designing a field effect transistor model according to a third embodiment of the present invention.

FIG. 5 is an equivalent circuit diagram showing field effect transistor models according to second and third embodiments of the present invention.

FIG. 6 is a characteristic diagram showing a drain current model according to the first to third embodiments of the present invention.

FIG. 7 is a characteristic diagram showing an example of a conventional drain current model.

FIG. 8 is a characteristic diagram comparing an example of a capacitance model according to a second embodiment of the present invention with an example of a conventional capacitance model in terms of gate-source voltage dependence.

FIG. 9 is a characteristic diagram comparing an example of a capacitance model according to a second embodiment of the present invention and an example of a conventional capacitance model in terms of gate-drain voltage dependence.

FIG. 10 is a circuit design device incorporating a drain current model and a capacitance model according to a fourth embodiment of the present invention.

FIG. 11 is a circuit design device incorporating a drain current model and a capacitance model according to a fifth embodiment of the present invention.

FIG. 12 is a characteristic diagram showing output characteristics and DC current characteristics of a power amplifier designed using the circuit design device of the present invention.

FIG. 13 is a characteristic diagram showing power load efficiency of a power amplifier designed using the circuit design device of the present invention.

[Explanation of symbols]

ST1 measurement step ST2 calculation step ST3 judgment step ST4 replacement step ST5 decision step 10, 20 FET model design device 11 Drain current measuring means 12 Gate voltage measuring means 13 Drain voltage measuring means 14 S-parameter measuring means

─────────────────────────────────────────────────── --- Continuation of front page (56) References JP-A-60-91651 (JP, A) JP-A-10-65159 (JP, A) JP-A-9-135028 (JP, A) MANKOO LEE et. a. , A Self-Bakgating GaAs MESFET Model for Low-Frequency Anomalies, IEEE Transactions on Electron Devices, USA, October 1990, Vol. 37, No. 10, p. 2148-2157 (58) Fields investigated (Int.Cl. ⁷ , DB name) H01L 29/80 H01L 29/00

Claims (11)

(57) [Claims] 1. A high-frequency integrated circuit design method of a field effect transistor model used in the design, the measurement stearyl <br/>-up for measuring the field effect transistor models drain current and the gate and drain voltages respectively, wherein Based on the drain current value, the gate voltage value, and the drain voltage value measured in the measuring step, the drain current is set to the term of the first coefficient, the second coefficient, and the gate voltage.
The first-order product term of, the third coefficient and the second-order of the gate voltage
A product term, a fourth coefficient and a third order product term of the gate voltage,
The sum of, in order to fit the cubic equation expressed by the product of the trigonometric function of the drain voltage, next the gate voltage different
As the first to fourth coefficients by which the number terms are multiplied are represented by a plurality of linear equations relating to the drain voltage, which are respectively different coefficients, the coefficients of each term are simultaneously and in parallel. Performance
Coefficient calculation step to calculate and each coefficient obtained in the coefficient calculation step
According to the third order equation and the first order equation
A method for designing a field effect transistor model , comprising: a model calculation step for calculating a flow model; and a replacement step for replacing with 0 when the value of the drain current calculated in the model calculation step becomes negative. 2. A cubic equation for determining the drain current is defined as the first to fourth equations when the drain current is I _ds , the gate voltage is V _gs , and the drain voltage is V _ds .
The plurality of linear expressions represented by the following expression (A) including the coefficients A ₀ , A ₁ , A ₂ , and A ₃ and further operated in parallel are the following expressions (B1) to (B4) I _ds = (A ₀ + A ₁ V _gs + A ₂ V _gs ² + A ₃ V
_gs ³ ) tanh (γV _ds ) ... (A) A ₀ = A ₀₀ + A ₀₁ V _ds (B1) A ₁ = A ₁₀ + A ₁₁ V _ds (B2) A ₂ = A ₂₀ + A ₂₁ V _ds (B3) _{) a 3 = a 30 + a} 31 V ds ... ( designing method of a field effect transistor model according to claim 1, characterized by being represented by B4). 3. A method of designing a field effect transistor model used for designing a high frequency integrated circuit, which shows a predetermined relationship between a drain current, a drain voltage, a gate voltage of the field effect transistor model and an element input / output by a two-terminal measurement method. A measurement step of measuring each S parameter, a gate-drain voltage measured in the measurement step ,
The gate-source capacitance calculated from the gate-source voltage and the S parameter is defined as the first coefficient term, the second coefficient, and the first-order product term of the gate-source voltage , and the third coefficient. Game
Secondary product of terms Tososu voltage, in order to fit into the fourth coefficient and the primary product term of the gate-drain voltage, quadratic as a sum of the first to fourth coefficient Same in parallel
A coefficient calculation step that is sometimes calculated, and the first to fourth coefficients obtained in the coefficient calculation step.
Calculate gate-source capacitance by quadratic equation with number
A method of designing a field effect transistor model , comprising: a capacitance calculation step; and a substitution step of replacing with 0 when the value of the gate-source capacitance calculated in the capacitance calculation step becomes negative. 4. A quadratic equation for evaluating the capacity between the gate source and gate-source capacitance and C _gs, as an expression of the gate-drain voltage V _gd voltage V _g0 and the intrinsic gate-source intrinsic, to the first free Coefficient C as the fourth coefficient
_The following formula including _s1 , C _s2 , C _s3 , and C _s4 C _gs = C _s1 + C _s2 V _g0 + C _s3 V _g0 ² + C
The field effect transistor model design method according to claim 3, wherein the field effect transistor model is _s4 V _gd . 5. A method of designing a field effect transistor model used for designing a high frequency integrated circuit, showing a predetermined relationship between a drain current, a drain voltage, a gate voltage of the field effect transistor model and an element input / output by a two-terminal measurement method. A measurement step of measuring each S parameter, a gate-drain voltage measured in the measurement step ,
The gate-drain capacitance calculated from the gate-source voltage and the S parameter is calculated by using the first coefficient term and the second coefficient.
And the first-order product term between the gate-drain voltage and the second coefficient
In order to fit a quadratic equation that is the sum of the quadratic product term of the gate-drain voltage , the fourth coefficient and the first-order product term of the gate- source voltage, Each of the given coefficients in parallel
A coefficient calculation step of calculating simultaneously the gate having coefficients calculated by the coefficient calculating step
A model calculation system that calculates the quadratic equation of the drain-to-drain capacitance model
And a replacement step of replacing with 0 when the value of the gate-drain capacitance calculated in the model calculation step becomes negative, a method of designing a field-effect transistor model. 6. 2 linear equation for evaluating the gate-drain capacitance, the gate-drain capacitance and C _gd, the gate-source voltage of the gate-drain voltage V _gd and the intrinsic intrinsic V _g0
The following equation C _gd = C _d1 + C _d2 V _gd + C _d3 V including the respective coefficients C _d1 , C _d2 , C _d3 , and C _d4 as the first to fourth coefficients. _gd ² + C
_The method of designing a field effect transistor model according to claim 5 , wherein _d4 V _g0 . 7. The field effect transistor is a GsAs field effect transistor formed on a semi-insulating substrate of gallium arsenide compound.
6. The method for designing a field effect transistor model according to any one of 5 above. 8. The GsAs MES formed on a semi-insulating substrate of a gallium arsenide compound in the field effect transistor.
6. The field effect transistor model design method according to claim 1, wherein the field effect transistor model is a FET. 9. The high-frequency integrated circuit drain current of the field effect transistor model used in the design, the field effect transistor design models for determining the coefficients for each value of electrical data to set the optimum value of the gate voltage and the drain voltage In the device, a drain current measuring unit for measuring a drain current of the field effect transistor model, a gate voltage measuring unit for measuring a gate voltage of the field effect transistor model, and a drain voltage for measuring a drain voltage of the field effect transistor model. measuring means, the drain current measuring means, the drain current measured respectively by the gate voltage measuring means and a drain voltage measuring means, based on the gate voltage and the drain voltage, the drain current, the first coefficients of the terms, first Coefficient of 2
And the first-order product term of the gate voltage, the third coefficient and the gate voltage.
Second-order product term of the gate voltage, fourth coefficient, and the gate voltage
The third order product terms, the sum and the gate in order to fit the cubic equation expressed by the product of the trigonometric function of the drain voltage
Said first including those multiplied by different order terms of voltage
To the fourth coefficient are different coefficients.
As represented by a plurality of linear equations for pressure ,
The coefficient calculation means for simultaneously calculating the first to fourth coefficients in parallel and the respective coefficients obtained by the coefficient calculation means are included.
According to the third-order equation and the first-order equation
A field effect transistor model design apparatus comprising: a model calculation unit that calculates a dell; and a replacement unit that replaces with 0 when a value of a drain current calculated by the model calculation unit becomes negative. 10. A field effect transistor model design apparatus for obtaining a coefficient for each electric data value for setting a field effect transistor model used for designing a high frequency integrated circuit, comprising: Drain current measuring means for measuring, drain voltage measuring means for measuring drain voltage of the field effect transistor model, gate voltage measuring means for measuring gate voltage of the field effect transistor model, and S parameter of the field effect transistor model and S parameter measuring means for measuring the drain current measuring means, the drain voltage measuring means, its the gate voltage measuring unit and the S parameter measurement means
The gate-source capacitance calculated from the measured gate-drain voltage, gate-source voltage and S-parameter, respectively, is calculated by the first-order product of the term of the first coefficient and the second coefficient and the gate-source voltage . Term, third coefficient and gate-source voltage
Secondary product terms of pressure, the fourth coefficient and the gate-drain voltage
Engaging the primary product terms, in order to fit the quadratic equation is the sum of, obtaining the first to fourth coefficient parallel simultaneously
The number calculation means and the first to fourth coefficients obtained by the coefficient calculation means
Capacitance for calculating the gate-source capacitance by the quadratic equation
Calculating means and the design device of the field effect transistor model, characterized in that it comprises a replacement unit, the value of gate-source capacitance which is calculated by the volume calculating means replaces at 0 when negative. 11. A field effect transistor model design apparatus for obtaining a coefficient for each electric data value for setting a field effect transistor model used for designing a high frequency integrated circuit, comprising: Drain current measuring means for measuring, drain voltage measuring means for measuring drain voltage of the field effect transistor model, gate voltage measuring means for measuring gate voltage of the field effect transistor model, and S parameter of the field effect transistor model S-parameter measuring means for measuring, and a value calculated from the gate-drain voltage, the gate-source voltage and the S-parameter measured by the drain current measuring means, the drain voltage measuring means, the gate voltage measuring means and the S-parameter measuring means. And the gate-drain capacitance, terms of the first coefficient, the first-order product terms of the second coefficient and the gate-drain voltage, the second coefficient and the gate-drain voltage
Of the quadratic product , the fourth coefficient and the gate-source voltage of 1
Wherein in order to fit the quadratic equation is the sum of the next product of claim No.
Coefficient calculation means for simultaneously calculating each of the first to fourth coefficients in parallel, and a gate drain having the coefficients calculated by the coefficient calculation means.
Model calculation means for calculating a quadratic expression of the inter-in capacitance model, and replacement means for replacing with 0 when the value of the gate-drain capacitance calculated in the model calculation step becomes negative. Field effect transistor model design equipment.