JP3415784B2 - Semiconductor storage device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a multi-bank structure semiconductor memory device.

[0002]

2. Description of the Related Art Synchronous DRAM (Dynamic)
A high-speed DRAM such as a Random Access Memory) has a plurality of banks including a memory array block including memory cells, bit line sense amplifiers, row decoders, etc., and a configuration in which each bank can be accessed asynchronously is adopted. According to this configuration, it becomes possible to read data from a certain bank and prepare for the sensing operation of the next bank to be read.
Higher speed continuous access becomes possible.

In the above-mentioned semiconductor memory device composed of a plurality of banks, it is necessary to activate or precharge a specific bank regardless of the states of other banks. Therefore, a timing control circuit is provided for each bank. By the way, in order to operate a plurality of independent banks at the same time (bank interleave operation), it is necessary to maintain the internal state of the bank except when the bank is selected by the bank selection signal. . Conventionally, a timing control circuit provided for each bank has a function of maintaining the internal state of the bank.

[0004]

By the way, the timing control circuit requires many circuits such as a delay circuit in order to generate the timing for operating the memory array block, and the layout area is large. Therefore, if a timing control circuit is provided for each bank, a considerably large layout area is required for the entire device. This problem is caused by the number of banks in the device being 2
When the number of banks is as small as 4 or 4, the effect is not so large, but in a device with a large number of banks such as 8 banks or 16 banks, the chip size is affected, which is a big problem. Will be.

The present invention has been made in view of the above problems and other problems of the conventional semiconductor memory device, and the first object of the present invention is to reduce the layout size. , To provide a new and improved semiconductor memory device.

A second object of the present invention is to provide a new and improved semiconductor memory device capable of quickly recognizing that the device is in an active state.

[0007]

In order to solve the above problems, according to a first aspect, as described in claim 1, a plurality of banks each including a memory cell array and a bit line sense amplifier are provided, and each bank is provided. In a semiconductor device that controls each bank according to an input bank selection signal, a row decoder provided corresponding to each row address of each bank and having a function of holding a selected state of the row address,
A bank selection signal provided for each bank, a row decoder reset signal for resetting the row decoder, a row decoder enable signal for enabling the row decoder, and a row address signal for selecting the row decoder. , And a row decoder control unit for controlling the row decoder and corresponding to each bank, which controls the bit line sense amplifier by the sense signal and which equalizes the bit line according to the state of the bank selection signal.
Hold the state of the equalize signal
There is provided a semiconductor memory device including a sense amplifier control circuit having a function of holding a state of a sense signal according to a state of a signal.

The row decoder control unit has a function of holding the state of the row address signal, as described in claim 5 , and the row address signal corresponds to the state of the row decoder enable signal. It may be configured to be sent to.

According to this structure, each bank has a function of holding the internal state of each bank, in addition to the timing control circuit for generating the timing for operating the memory array block. Therefore, unlike the conventional device in which the timing control circuit is provided for each bank, only one timing control circuit needs to be provided, which has the effect of reducing the layout size.

[0010] Preferably as described in claim 6, the row address signal is directly sent to the row decoder, row decoder enable signal in response to the bank selection signal, configured to enable the row decoder .

With this configuration, it is not necessary to provide a holding circuit for each row address signal. Therefore, unlike the configuration in which a holding circuit for controlling the row address signal is provided corresponding to each row address signal, it is possible to further reduce the layout size of each bank.

Further, as described in claim 7 , the row address decode signal may be a predecoded signal. With this configuration, it is possible to further reduce the size of the circuit.

In order to solve the above problems, according to a second aspect , as described in claim 2 , a memory cell array and a memory cell array are provided.
Each bank has multiple banks of bit line sense amplifiers.
Each bank is controlled by the bank selection signal input to the link
In the semiconductor memory device that operates: each row address of each bank
Is provided for each address and holds the selected state of the row address.
A row decoder having a function to enable; for each bank
Provided, bank select signal and row decoder reset
Decoder for resetting row decoder and row decoder
Row decoder enable signal that enables
The row address signal for selecting the decoder is input.
Control unit for controlling the row decoder
And; provided corresponding to each bank and
Control the input line sense amplifier to change the state of the bank selection signal.
Depending on the state of the equalize signal, the bit lines are equalized accordingly.
State is maintained and the sense signal is received according to the state of the equalize signal.
Sense amplifier controller having a function of holding the state of the signal
Circuit and; determine whether each bank is activated
Determining means and for, provided with, each bank, if the bank is not activated to output the first signal of one level to the determination means, the other to the determination means if the banks are activated The first signal at the level of
When all the signals are at one level, the second signal at one level is output, and when any of the first signals is at another level, the second signal at another level is output. A semiconductor memory device is provided.

As a concrete configuration example of the judging means,
As described in claim 3 , propagation circuits corresponding to each bank of n (n is an integer of 2 or more) are connected in series, and each propagation circuit includes a NAND element and an inverter that receives an output of the NAND element as an input. And N of the first propagation circuit
A signal of the power supply voltage level and the first signal output from the first bank are input to the AND element, and the NAND element of the i-th (i is an integer from 2 to n) i-th
The first signal output from the th bank and the output signal of the inverter in the i−1 th propagation circuit are input.

According to this structure, it is possible to reduce the number of wirings for sequentially propagating the first signal, for example, the equalizing signal, to one. Therefore, unlike the conventional case, it is not necessary to provide as many decision circuits as the number of banks, and the wiring layout area can be reduced.

[0016] More preferably, the judgment means is claim 4.
As described in 1), when the sense signal is further input and the sense signal is enabled, the second level of another level is increased.
It is configured to output a signal. According to such a configuration, it is possible to quickly recognize that the device is in the active state.

[0017]

BEST MODE FOR CARRYING OUT THE INVENTION Referring to the accompanying drawings,
A preferred embodiment of a semiconductor memory device according to the present invention will be described in detail. In the present specification and the drawings, components having substantially the same functional configuration are designated by the same reference numerals, and duplicate description will be omitted.

(First Embodiment) A semiconductor memory device 100 according to a first embodiment will be described with reference to FIG. The semiconductor memory device 100 is
As shown in FIG. 1, a plurality of banks each including a memory cell array and bit line sense amplifiers are provided. Each bank B0 to Bn, a row decoder provided corresponding to the row address, the row decoder system for controlling the row decoder
A decoder unit 120 including a control unit and a sense amplifier control circuit 130 are provided.

Further, the semiconductor memory device 100 is provided with a timing control circuit 110 which receives a control signal such as a sense signal SAL and a precharge signal PRE and outputs an array control signal AC for controlling the memory cell array to each of the banks B0 to Bn. ing. Timing control circuit 110
Is a circuit that creates the timing for controlling the memory array block of the selected bank.

It is assumed that the sense signal SAL and the precharge signal PRE input to the timing control circuit 110 are valid signals only when they rise to a high level.
For example, when the sense signal SAL is changed from low level to high level while the bank selection signal BS is selecting 0 bank, the timing control circuit 110 starts to operate,
The array control signal AC for each bank is sequentially enabled, and circuits such as the equalize signal EQB, the word line WLi, and the sense amplifier are sequentially activated.

Next, the array control signal AC output from the timing control circuit 110 to each of the banks B0 to Bn will be described. Array control signal AC
Includes control signals such as a row decoder reset signal LRS for resetting the row decoder and a row decoder enable signal LEN for enabling the row decoder. These signals are output to the decoder section 120 in the subsequent stage.
Entered in.

Further, the array control signal AC is
A sense amplifier enable signal SEN for enabling the sense amplifier, an equalizing enable signal EEN for enabling the equalizing signal EQB,
It includes control signals such as an equalize reset signal ERS for resetting the equalize signal EQB. These signals are input to the subsequent sense amplifier control circuit 130.

Next, the decoder section 120 and the sense amplifier control circuit 130, which are characteristic components of this embodiment, will be described. The decoder unit 120 and the sense amplifier control circuit 130 accept the input signal only when the bank is selected by the bank selection signal BS, and when the bank is not selected,
It has the function of being disconnected from the input signal and latching the internal state.

(Decoder Unit 120) Decoder Unit 120
As shown in FIG. 2, a row decoder 123 provided corresponding to each row address and having a function of latching a selected state of the row address and a word line WLi provided corresponding to each row decoder are driven. Word driver 12
5 and a row decoder control unit 124 provided corresponding to each bank and controlling each row decoder. Although only the row decoder and word driver corresponding to one word line WLi are shown in FIG. 2, the row decoder and word driver are provided corresponding to each row address in the bank, and row decoder control is performed. It is connected to the section 124.

(Row Decoder Control Unit 124) The row decoder control unit 124 has a bank selection signal BS and a row decoder reset signal L for resetting the row decoder.
RS, a row decoder enable signal LEN for enabling the row decoder, and a row address signal AXi for selecting the row decoder are input. In addition,
The row address signal AXi is predecoded as described later.

The row decoder control section 124 includes a reset signal latch circuit 121 for latching the row decoder reset signal LRS and a row address latch circuit 122 for latching the row address signal LEN. The reset signal latch circuit 121 and the row address latch circuit 122 are controlled by the bank selection signal BS.

The reset signal latch circuit 121 is composed of clocked inverters CINV1 and CINV2 and inverters I121 and I122. The row decoder reset signal LRS input to the reset signal latch circuit 121 is input to the clocked inverter CINV1. The bank selection signal BS and its inverted signal are input to the clocked inverter CINV1. When the bank selection signal BS is at the low level, the output of the clocked inverter CINV1 has a high impedance. When the bank selection signal BS is at the high level, the clocked inverter CINV1 functions in the same manner as a normal inverter, and its output is in the latter stage. It is input to the inverter I121.

The output of the inverter I121 is output via the inverter I122 to the PMO in the subsequent row decoder 123.
It is input to the S transistor P1 and also input to the clocked inverter CINV2. The bank selection signal BS and its inverted signal are input to the clocked inverter CINV2. When the bank selection signal BS is at high level, the output of the clocked inverter CINV2 becomes high impedance, and when the bank selection signal BS is at low level, the clocked inverter CINV functions like an ordinary inverter, and its output is again an inverter. I121
Entered in.

Next, the predecode signal latch circuit 12
2 will be described. In general, if the decode signal corresponding to each address is input to the row decoder,
The circuit configuration becomes very large. Therefore, a plurality of decode signals are predecoded to create a predecode signal, and the predecode signal is used for the row decoder. As an example of predecoding, FIG. 2 shows a case where predecoding is performed by three row address predecode signals AXi.

Three row address predecode signals AX
Each predecode signal latch circuit 122 provided corresponding to i has substantially the same configuration as the reset signal latch circuit 121. Each predecode signal latch circuit 122 has a row address predecode signal AXi, a bank selection signal BS and a row decoder enable signal LE.
The output signal of the NAND element N124 to which N is input,
The output signal of the AND element N124 and the signal passed through the inverter I124 are input. That is, each predecode signal latch circuit 122 latches the row address predecode signal under the control of the bank selection signal BS, its inverted signal, and the row decoder enable signal LEN, and the NMOS transistors N1 to N1 in the row decoder 123 in the subsequent stage are latched.
Send to N3.

(Row Decoder 123) Row Decoder 12
3 includes the PMOS P1 described above. PMOSP1
Is connected to the power source, and the gate of the PMOS P1 is connected to the inverter I12 in the row decoder controller 124 described above.
2 outputs are connected. A power source is connected to the source of the PMOS P1, and the node A connected to the drain of the PMOS P1 is set to a high level under the control of the row decoder reset signal LRS. When the node A becomes high level, the row decoder 123 is reset.

Further, the row decoder 123 is the above-mentioned NM.
It includes OSN1 to N3. NMO connected in series
The above-described row address predecode signal AXi is connected to the gates of SN1 to N3. NMOSN
The source of 1 is connected to the node A, and the drain of the NMOS N3 is grounded. Row decoder enable signal L
Under the control of EN, the node A connected to the source of the NMOS N1 is set to low level. When the node A becomes low level, the row decoder 123 is enabled.

The row decoder 123 further includes a latch unit 126 which holds the state of the node A and outputs it to the word driver 125 at the subsequent stage. The latch unit 126 includes a PMOS P2 whose source is connected to a power supply and an inverter I1. Node A is connected to inverter I1. The output of the inverter I1 is the word driver 1 of the latter stage.
25, and is connected to the gate of PMOS P2. The drain of the PMOS P2 is again the inverter I.
Connected to 1.

(Sense amplifier control circuit 130)
Next, the sense amplifier control circuit 130
Will be described with reference to. The sense amplifier control circuit 130, as shown in FIG. 3, receives the equalize enable signal EEN, the equalize reset signal ERS, and the bank select signal BS.
1 and the signal E which is the output of the equalize latch circuit 131.
It includes a sense amplifier latch circuit 132 to which Q and the sense amplifier enable signal SEN are input.

The equalize latch circuit 131 is a NAND
It is composed of elements N131 to N134. NAN
The D element N131 receives the equalization enable signal EEN and the bank selection signal BS as input, and receives the NAND element N13.
It outputs to one gate of 3. The NAND element N132 is
The equalization reset signal ERS and the bank selection signal BS are input and output to the gate of the NAND element N134. The NAND element N133 is the NAND element N131.
And the output of the NAND element N134. NAN
The D element N134 is the NAND element N132 and the NAND
The output of the element N133 is input and the signal EQ is output.
The signal EQ is input to the sense amplifier latch circuit 132 and also output as an equalize signal EQB for equalizing the bit line via the inverter I131.

The sense amplifier latch circuit 132 is a NAN.
It is composed of D elements N135 to N136 and an inverter I131. The NAND element N135 receives the sense amplifier enable signal SEN via the inverter I132 and further receives the output of the NAND element N136. The NAND element N136 has signals EQ and NAN.
The output of the D element NANDN 135 is input. NAN
The output of the D element N136 is the NAND element NAND135.
And is output as a sense latch signal SL via the inverter I133. The sense latch signal SL is a signal for controlling the sense amplifier.

The operation of the semiconductor memory device 100 having the above structure will be described with reference to the timing chart shown in FIG.

When the sense signal SAL is changed from the low level to the high level while the bank selection signal BS is selecting the 0 bank, the timing control circuit 110 starts to operate, and the EQ reset signal ERE, the row decoder enable signal LEN, and the like. The array control signal AC including the sense amplifier enable signal SEN and the like is sequentially enabled.

When the array control signal AC is enabled, 0 selected by the bank selection signal BS
Only the decoder unit 120 and the sense amplifier control circuit 130 of the memory array block of the bank receive the array control signal AC. Then, as described above, only the node A of the row decoder 123 of the specific address in the 0 bank becomes the low level by the row address predecode signal AXi which becomes the high level at the same time, and the low address is supplied via the inverter 11 and the word driver 125. ，
The word line WLi becomes high level.

In this state, when the bank selection signal BS becomes low level, the states of the decoder section 120 and the sense amplifier control circuit 130 are latched, and the 0 bank maintains the active state until the next selection. . Array control signal AC is bank selection signal B
After S is reset, it is automatically reset.

Next, when the bank selection signal BS selects two banks and the sense signal SAL is changed from low level to high level, the timing control circuit 110 operates again and the array control signal AC is sequentially enabled. As in the case of 0 bank, only the memory array blocks of 2 banks become active. At that time, since the memory array block of 0 bank is not selected by the bank selection signal BS, the active state is maintained.

Next, when the precharge signal PRE changes from the low level to the high level with the bank selection signal BS selecting the 0 bank, the timing control circuit 110
Starts the precharge operation, and among the array control signals AC, the signals related to the precharge operate,
The row decoder and the sense amplifier control circuit of the memory array block selected by the bank selection signal BS are reset and the precharge operation is performed.

According to the semiconductor memory device 100 configured and operated as described above, the conventional circuit configuration is provided by providing the row decoder and the sense amplifier control circuit in the memory array block with the function of maintaining the state of each bank. The bank interleave operation similar to that can be controlled by only one timing control circuit, and the layout size can be reduced.

(Second Embodiment) A semiconductor memory device 200 according to a second embodiment will be described with reference to FIG. The semiconductor memory device 200 is the decoder unit 1 of the semiconductor memory device 100 according to the first embodiment.
20 is replaced with the decoder unit 220 shown in FIG. The configuration of the other components and the signal connection relationship are substantially the same as those of the semiconductor memory device 100 shown in FIG.

(Decoder Unit 220) Decoder Unit 220
As shown in FIG. 5, a row decoder 223 provided corresponding to each row address and having a function of latching a selected state of the row address, and a word line WLi provided corresponding to each row decoder are driven. Word driver 22
5 and a row decoder control unit 224 provided corresponding to each bank and controlling each row decoder. Although only the row decoder and word driver corresponding to one word line WLi are shown in FIG. 5, the row decoder and word driver are provided corresponding to each row address in the bank, and row decoder control is performed. It is connected to the section 224.

(Row Address Control Unit 224) The row decoder control unit 224 has a bank selection signal BS and a row decoder reset signal L for resetting the row decoder.
RS, a row decoder enable signal LEN for enabling the row decoder, and a row address signal AXi for selecting the row decoder are input.

The row decoder reset signal LRS is input to the NAND element NA220 together with the bank selection signal BS. The NAND element NA220 has a bank selection signal B
When S becomes high level, the bank is selected, and the row decoder reset signal LRS becomes high level, the low level signal XDP is sent to the PMOS P1 in the row decoder 223 in the subsequent stage.

The row decoder enable signal LEN is input to the NAND element NA221 together with the bank selection signal BS. In the NAND element NA221, the bank selection signal BS becomes high level, the bank is selected, and the row decoder enable signal LEN becomes high level, so that the row decoder 223 in the rear stage is supplied via the inverter I220 in the rear stage. The high level signal LBS is sent to the NMOS N4.

The row address signal AXi is predecoded into three row address predecode signals AXi as in the case of the semiconductor memory device 100. The row address predecode signal AXi is
It is directly sent to the gates of the NMOSs N1 to N3 in the row decoder 223 in the subsequent stage.

(Row Decoder 223) The row decoder includes the PMOS P1 described above. The source of the PMOS P1 is connected to the power supply, and the gate of the PMOS P1 is connected to the above-mentioned signal XDP. A power source is connected to the source of the PMOSP1 and the PMOS is controlled by the signal XDP.
The node A connected to the drain of P1 is set to high level. When the node A becomes high level, the row decoder 2
23 is in a reset state.

Further, the row decoder 123 is the above-mentioned NM.
It includes OSN1 to N4. NMO connected in series
The row address predecode signal AXi is connected to the gates of SN1 to N3, and the gate of the NMOS N4 connected in series is connected to the signal LBS. The source of the NMOS N4 is connected to the node A, and the drain of the NMOS N3 is grounded. By controlling the signal LBS, the node A connected to the source of the NMOS N1 is set to low level. When the node A becomes low level, the row decoder 223 is enabled.

The row decoder 223 further includes a holding unit 226 which holds the state of the node A and outputs it to the word driver 225 in the subsequent stage. The holding unit 226 includes a PMOS P2 having a source connected to the power supply, an NMOS N5 having a drain grounded, and an inverter I1. Node A is connected to inverter I1. The output of the inverter I1 is output to the word driver 225 in the subsequent stage and is also connected to the gate of the PMOS P1 and the gate of the NMOS N5. Drain of PMOSP1 and NMOSN
The source of 5 is again connected to the inverter I1.

The operation of the semiconductor memory device 200 having the above structure will be described with reference to the timing chart shown in FIG.

When the sense signal SAL is changed from the low level to the high level while the bank selection signal BS selects the 0 bank, the timing control circuit 210 starts to operate, and the EQ reset signal ERE, the row decoder enable signal LEN, and the like. The array control signal AC including the sense amplifier enable signal SEN and the like is sequentially enabled.

When the array control signal AC is enabled, 0 selected by the bank selection signal BS
Only the decoder unit 220 and the sense amplifier control circuit 230 of the memory array block of the bank receive the array control signal AC. Then, as described above, only the node A of the row decoder 223 of the specific address in the 0 bank becomes the low level by the row address predecode signal AXi which becomes the high level at the same time, and the low address is supplied via the inverter 11 and the word driver 225. ，
The word line WLi becomes high level.

In this state, when the bank selection signal BS becomes low level, the states of the decoder section 220 and the sense amplifier control circuit 230 are latched, and the 0 bank maintains the active state until the next selection. . Array control signal AC is bank selection signal B
After S is reset, it is automatically reset.

Next, when the bank selection signal BS selects two banks and the sense signal SAL is changed from low level to high level, the timing control circuit 210 operates again and the array control signal AC is sequentially enabled. As in the case of 0 bank, only the memory array blocks of 2 banks become active. At that time, since the memory array block of 0 bank is not selected by the bank selection signal BS, the active state is maintained.

Next, when the precharge signal PRE changes from low level to high level while the bank selection signal BS selects 0 bank, the timing control circuit 110
Starts the precharge operation, and among the array control signals AC, the signals related to the precharge operate,
The row decoder and the sense amplifier control circuit of the memory array block selected by the bank selection signal BS are reset and the precharge operation is performed.

According to the semiconductor memory device 200 configured and operating as described above, the same effect as the latched row decoder can be obtained as in the semiconductor memory device 100 in the first embodiment, and at the same time, FIG. Decoder section 12 shown
The row address signal latch circuit 122 of 0 becomes unnecessary,
The layout size of each bank can be reduced.

(Third Embodiment) Many general-purpose DRAMs and the like have a function of controlling a DC circuit or the like depending on whether or not the device is in an active state. In that case, whether it is active or not is determined in the timing control circuit shown in FIG.
Generally, the judgment is made by a signal or the like, but in the case of a circuit configuration in which the sense amplifier control circuit has a latch function in multiple banks as in the case of the first embodiment, the EQB signals of each bank are collected. However, there is no choice but to make a judgment based on logic, and the wiring layout becomes very difficult. Therefore,
In the semiconductor memory device 300 according to this embodiment, an active propagation circuit for recognizing whether the device is in the active state is connected to the sense amplifier control circuit.

A semiconductor memory device 300 according to the third embodiment will be described with reference to FIG. In the semiconductor memory device 300, a circuit is connected to the sense amplifier control circuit 130 forming each bank of the semiconductor memory device 100 according to the first embodiment to recognize whether it is in the active state or not. It has the configuration shown in. For other components and connections, see Figure 1.
Since the semiconductor memory device 100 is substantially the same as the semiconductor memory device 100 shown in FIG. The present embodiment can also be applied to the semiconductor memory device 200 according to the second embodiment.

As shown in FIG. 7, the semiconductor memory device 300 includes a sense amplifier control circuit 130 for each bank.
Is connected to the active determination unit 305. The active determination unit 305 includes active propagation circuits 310-0 to 310-n connected corresponding to the sense amplifier control circuit 130 of each bank. Each active propagation circuit is composed of a NAND element and an inverter.
The inverter I31 in the active propagation circuit 310- (i-1) upstream of the NAND element N311-i in the active propagation circuit 310-i (i is an integer of 1 or more and n or less)
The output A- (i-1) of 2- (i-1) and the equalization signal EQB-i of the i bank are input. NAND
The output of the element N311-i is input to the inverter I312-i. It should be noted that one input of the NAND element N311-0 in the active propagation circuit 310-0 is connected to the power supply and 0.
The bank equalization signal EQB-0 is connected.

The output of the inverter I312-n in the active propagation circuit 311-n is output as the decision signal ACTIVE through the inverter I313. Judgment signal A
CTIVE is a signal for determining whether or not it is in the active state.

The operation of the semiconductor memory device 300 having the above structure will be described with reference to FIG.

First, when the bank selection signal BS connected to the 0 bank is in the high level state and the sense signal SAL changes from the low level to the high level, the sense amplifier control circuit 130 of the 0 bank causes the low level equalization signal EQB-. Outputs 0. Then, the output A-0 of the active propagation circuit 310-0 for 0 bank becomes low level, and in response to the low level, the output A-i of the active propagation circuit 310-i for i bank sequentially becomes low level. To go. And the active propagation circuit 3 for the n bank
When the output A-n of 10-n becomes low level, the determination signal ACTIVE becomes high level by the inverter I313. When the determination signal ACTIVE becomes high level, it can be recognized that the device is in the active state. Similarly, when the bank selection signal BS connected to another bank is in the high level state, the determination signal ACTIVE also becomes the high level.

Further, the precharge is the reverse of the sense, and the sense amplifier control circuit 130 of the 0 bank is
Propagates the high level of the equalize signal EQB-0 sequentially, and finally the determination signal ACTIVE becomes low level.

According to the semiconductor memory device 300 configured and operated as described above, the equalization signal EQB is configured to be sequentially propagated to determine whether the required number of banks has become active. There is an effect that the number of wirings for wiring can be reduced to one and the wiring layout area can be reduced.

(Fourth Embodiment) A semiconductor memory device 400 according to a fourth embodiment will be described with reference to FIG. The semiconductor memory device 400 is obtained by modifying the active determination unit 305 of the semiconductor memory device 300 according to the third embodiment to another active determination unit 405 as shown in FIG. The other components of each bank, the connection relation of each bank, and the like are substantially the same as those of the semiconductor memory device 300, and thus the description thereof is omitted.

The active decision section 305 outputs the output A-n of the active propagation circuit 310-n for n banks as the decision signal ACTIVE through the inverter element I313. In the present embodiment, the active propagation circuit 310 for the n bank of the active determination unit 405.
The configuration is such that the output A−n of −n is input to the active signal generation circuit 413, and the active signal generation circuit 413 is controlled by the sense signal SAL, whereby the determination signal ACTIV
Output E. The other points such as the propagation of the equalize signal EQB are the same as those of the active determination unit 305 in the semiconductor memory device 300.

The active signal generation circuit 413 is shown in FIG.
, The output A-n of the active propagation circuit 310-n corresponding to the n-th bank and the sense signal SAL
Inputs and, and outputs a determination signal ACTIVE. The active signal generation circuit 413 includes inverters I414, I
415 and NAND elements N414 and N415. The signal A-n is input to the NAND element N414 via the inverter I414, and the output of the NAND element N415 is input to the NAND element N414. NAND element N415
The sense signal SAL is input via the inverter I415 and the output of the NAND element N414 is input. The output of the NAND element N415 is input to the NAND element N414 and the determination signal ACTIVE
Is output as.

The active signal generation circuit 413 is controlled by the sense signal SAL when the decision signal ACTIVE becomes high level, and confirms that all the banks are not active when the decision signal ACTIVE becomes low level. , Active propagation circuit 410
The circuit is controlled by the output A-n of -n.

The operation of the semiconductor memory device 400 having the above structure will be described with reference to FIG.

First, when the sense signal SAL changes from the low level to the high level while the bank selection signal BS connected to the 0 bank is in the high level state, the determination signal ACTIV
E becomes high level. After that, as in the case of the third embodiment, when the equalize signal BQB-0 becomes low level and the low level is propagated and the output A-n becomes low level, the decision signal ACTIVE is latched to high level. Even if the sense signal SAL becomes low level, the determination signal ACTIVE keeps high level.

Next, in the case of precharge, the high level of the equalize signal EQB-0 is sequentially propagated, the output An becomes high level, and finally the decision signal ACTI.
VE goes low.

In the case of the active decision section in the semiconductor memory device 300, since the equalize signal EQB is sequentially propagated, there is a problem that it takes time until the decision signal ACTIVE finally becomes high level. The active determination unit 405 in the semiconductor memory device 400 according to the present embodiment uses the fact that when the sense signal SAL changes from low level to high level, one of the banks becomes active, and the determination signal based on the sense signal SAL is used. There is an effect that it is possible to quickly recognize that the device is in the active state by setting ACTIVE to the high level.

The preferred embodiments of the semiconductor memory device according to the present invention have been described above with reference to the accompanying drawings, but the present invention is not limited to these examples. It is obvious to those skilled in the art that various changes or modifications can be conceived within the scope of the technical idea described in the claims, and naturally, these are also within the technical scope of the present invention. It is understood that it belongs.

For example, in the above embodiments, various latch means for latching various signals have been described, but the present invention is not limited to such a configuration. The present invention can be similarly applied even if it is replaced with substantially the same latch means.

[0078]

As described above, according to the present invention,
It has the following excellent effects.

According to the semiconductor memory device of the first or fifth aspect , in addition to the timing control circuit for generating the timing for operating the memory array block, each bank has a function of holding the internal state of each bank. ing. Therefore, unlike the conventional device in which the timing control circuit is provided for each bank, only one timing control circuit needs to be provided, which has the effect of reducing the layout size.

According to the semiconductor memory device of the sixth aspect , it becomes unnecessary to provide a holding circuit corresponding to each row address signal. Therefore, unlike the configuration in which a holding circuit for controlling the row address signal is provided corresponding to each row address signal, it is possible to further reduce the layout size of each bank.

According to the semiconductor memory device of the seventh aspect , the circuit can be further downsized.

According to the semiconductor memory device of the second or third aspect , it is possible to reduce the number of wirings for determining that the bank is in the active state, and it is possible to reduce the wiring layout area.

According to the semiconductor memory device of the fourth aspect , it is possible to recognize at high speed that the device is in the active state.

[Brief description of drawings]

FIG. 1 is an explanatory diagram of a semiconductor memory device according to a first embodiment.

FIG. 2 is an explanatory diagram of a row decoder of the semiconductor memory device of FIG.

FIG. 3 is an explanatory diagram of a sense amplifier control circuit of the semiconductor memory device of FIG.

FIG. 4 is a timing chart of the semiconductor memory device of FIG.

FIG. 5 is an explanatory diagram of a row decoder of the semiconductor memory device according to the second embodiment.

FIG. 6 is a timing chart of the semiconductor memory device of FIG.

FIG. 7 is an explanatory diagram of an active determination unit of the semiconductor memory device according to the third embodiment.

8 is a timing chart of the semiconductor memory device of FIG.

FIG. 9 is an explanatory diagram of an active determination unit of the semiconductor memory device according to the fourth embodiment.

FIG. 10 is an explanatory diagram of an active signal generation circuit.

11 is a timing chart of the semiconductor memory device of FIG.

[Explanation of symbols]

100 semiconductor memory device 110 Timing control circuit 120 decoder section 121 Reset signal latch circuit 122 address signal latch circuit 123 Row decoder 124 Row Decoder Control Unit 125 word driver 126 Latch B0 to Bn banks AC array control signal BS bank selection signal LRS row decoder reset signal LEN Row decoder enable signal AXi row address predecode signal WLi word line

─────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-11-162161 (JP, A) JP-A-6-275071 (JP, A) JP-A-9-73774 (JP, A) JP-A-7- 201172 (JP, A) (58) Fields surveyed (Int.Cl. ⁷ , DB name) G11C 11/401

Claims (7)

(57) [Claims] 1. A semiconductor memory device comprising a plurality of banks each comprising a memory cell array and a bit line sense amplifier, wherein each bank is controlled by a bank selection signal inputted to each bank: Corresponding to each row address of each bank A row decoder having a function of holding the selected state of the row address; a bank selection signal provided corresponding to each of the banks; and a row decoder reset signal for resetting the row decoder. A row decoder enable signal for enabling the row decoder and a row address signal for selecting the row decoder, and a row decoder control section for controlling the row decoder; The bit line sense amplifier is controlled by a sense signal, Equalize to equalize the bit line according to the state of the clock select signal
A semiconductor memory device comprising: a sense amplifier control circuit having a function of holding a state of a signal and holding the state of the sense signal according to a state of the equalize signal ; 2. A memory cell array and a bit line sense array.
There are multiple banks of
A semiconductor for controlling each of the banks by a bank selection signal
In the body memory device: provided corresponding to each row address of each bank,
A row having the function of holding the selected state of the row address.
A decoder; provided corresponding to each of the banks, the bank selection signal
And a row decoder for resetting the row decoder.
Reset signal and enable the row decoder
Row decoder enable signal and the row decoder
The row address signal for selecting and
A row decoder control section for controlling the row decoder; provided corresponding to each of the banks,
The bit line sense amplifier is controlled, and the bank selection signal
Equalize the bit lines according to the state of
Holds the signal state, depending on the state of the equalize signal
A sense amplifier having a function of holding the state of the sense signal.
Pump control circuit; Judgment for judging whether or not each of the banks is activated
Means and; wherein the each bank, if the bank is not activated to output the first signal of one level in said determination means, said determining means if the banks are activated The first signal of another level is output, and the determination means outputs a second signal of one level when all of the first signals are of one level, and the determination means outputs one of the first signals of each of the first signals. Is a different level, the semiconductor memory device outputs the second signal of another level. 3. The determination means is configured such that n (n is an integer of 2 or more) propagation circuits corresponding to each bank are connected in series, and each propagation circuit outputs a NAND element and an output of the NAND element. A power supply voltage level signal and a first signal output from the first bank are input to the NAND element of the first propagation circuit, which is composed of an inverter as an input, and i (i is 2 or more) an integer less than or equal to n) Nth of the propagation circuit
3. The semiconductor device according to claim 2 , wherein the AND element receives the first signal output from the i-th bank and the output signal of the inverter in the (i-1) th propagation circuit. Storage device. Wherein said determining means is further input the sense signal, in response to said sense signal, and outputting a second signal of the other levels, also claim 2
Is a semiconductor memory device described in 3 . 5. The row decoder control section has a function of holding the state of the row address signal, and the row address signal is sent to the row decoder according to the state of the row decoder enable signal. 5. The semiconductor memory device according to claim 1, wherein the semiconductor memory device is a semiconductor memory device. Wherein said row address signal is directly sent to the row decoder, the row decoder enable signal in response to the bank selection signal, characterized in that to enable the row decoder, according to claim 1 , 2,
The semiconductor memory device according to any one of 3, 4 or 5. 7. The row address decode signal is a predecoded signal.
7. The semiconductor memory device according to any one of 1, 2, 3, 4, 5 and 6 .