JP3415593B2 - A / D converter - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an A / D converter, and more particularly to an A / D converter that performs digital weighting using a capacitive element.

[0002]

2. Description of the Related Art Recent LSIs have been improved in the degree of integration due to the progress of semiconductor manufacturing processes, and LSIs have been implemented as a system that unifies the circuit functions mounted on independent chips into one chip. Semiconductor chips tend to have higher performance and larger scale.

For example, A built in a signal processing LSI
In the A / D converter, there is a demand for higher processing speed and more channels for processing a plurality of analog signals as the CPU speed and performance increase.

System LSI for controlling engine of automobile
In the A / D converter built in, the analog signals from various sensors (temperature sensor, pressure sensor, etc.) are converted into digital signals to control the engine. In this A / D converter, since the output impedance of the ceramic parts such as the O ₂ sensor is as high as several MΩ, there is a problem that a conversion error occurs unless the input capacitance is reduced.

FIG. 8 is a circuit diagram of an A / D converter described in Japanese Patent No. 2952931. This A / D converter has a first DA converter 2 and a second DA converter 3, and has a resolution of 3 bits. The first DA conversion unit 2 and the second DA conversion unit 3 respectively include capacitive elements C1 to C4 and C5 to C8 having a relative ratio of capacitance values of 1: 1: 2: 4. The capacitance elements C1 and C5, C2 and C6, C3 and C7, and C4 and C8 have the same size.

When a PROM (not shown) generates an L level select signal Φs, changeover switches S32 and S34
Is turned on, and the changeover switches S31 and S33 are turned off. The first DA converter 2 operates as a reference level voltage setting unit, and samples the input voltage Vin based on the control signal 104 from the logic circuit 9 to set the reference level voltage.

The second DA conversion section 3 operates as a capacitive load section for differential input balancing. The positive phase comparison input terminal and the negative phase comparison input terminal of the comparator 4 are connected to the power supply or the ground via the capacitive elements C1 to C4 and C5 to C8, and the combined capacitances of both are equal. In the comparator 4, the capacitive loads on both the differential inputs are balanced when viewed in terms of alternating current, and remove the in-phase signal component.

The A / D converter performs an initialization operation and a binary search operation. During the initialization operation, the precharge signal Φb becomes H level. At this time, the ground switches S9 and S10 are turned on. In the comparator 4, both the positive-phase comparison input terminal and the negative-phase comparison input terminal are at the ground potential, and the operating point (comparison reference voltage) for comparing the input voltage Vin and the reference level voltage is determined. The dynamic input is biased.

The logic circuit 9 has a control signal 10
4 is generated. At this time, the capacitance switches S5 to S8 select the ground potential. The capacitors C5 to C8 have their electric charges discharged and store the ground potential. Capacity switch S
1 to S4 select the input voltage Vin. In addition, the capacitive element C
Electric charges are stored in 1 to C4 and the input voltage Vin is sampled.

In the binary search operation, the capacitance switches S1 to S3 first select the reference voltage VF-, and the capacitance switch S4 selects the reference voltage VF +. The capacitance switch S1 is
The reference voltage VF- is selected until the three searches are completed. In the binary search, the search is performed three times, and the reference voltage selected by each of the capacitance switches S4 to S2 is VF + or V
It is decided which of F- is.

The first DA converter 2 includes a capacitance switch S2 ...
S4 selects the reference voltage VF + or VF- to set the reference level voltage. The first DA converter 2 generates a voltage that is a difference between the set reference level voltage and the sampled input voltage Vin, and inputs the voltage as a comparison target voltage Vcp1 to the negative phase comparison input terminal of the comparator 4. The second DA converter 3 inputs the ground potential as the comparison reference voltage Vcp2 to the positive phase comparison input terminal of the comparator 4.

The comparator 4 compares the comparison reference voltage Vcp1 with the comparison reference voltage Vcp2 and generates a comparison result signal 101. The logic circuit 6 determines whether the input voltage Vin is higher than the reference level voltage based on the comparison result signal 101, and generates the control signal 104.

In the case of the first search, the first DA converter 2
Sets a reference level voltage intermediate between the reference voltage VF + and the reference voltage VF-. Specifically, the capacitance switch S4 selects the reference voltage VF +, and the capacitance switches S2 and S3 select the reference voltage VF-. The input voltage Vin is compared with the set reference level voltage. The capacitance switch S4 determines the reference voltage to be selected based on the comparison result of the first search.

If the input voltage Vin is higher than the reference level voltage, it is determined that the selection of the capacitance switch S4 is the reference voltage VF +, and if the input voltage Vin is lower than the reference level voltage, the selection of the capacitance switch S4 is the reference voltage VF. -Determined to be

The second and third searches are performed in the same manner as the first search, and the reference voltages selected by the capacitance switches S3 and S2 are determined respectively. The A / D converter completes the conversion operation after performing three searches. The logic circuit 9 is
A conversion result signal 105 based on the conversion result is generated.

If the relative accuracy of the capacitive elements C1 to C4 is low, an error occurs in the reference level voltage that is set, which affects the characteristics of AD conversion. A / D converter is
The AD conversion characteristic is measured. If the measurement result is good,
If it is left as it is and the measurement result is bad, PROM
Is rewritten.

If the PROM has a bad measurement result, the H
A level select signal Φs is generated. The first DA converter 2 operates as a capacitive load for differential input balancing, and
The A conversion unit 3 operates as a reference level voltage setting unit. If the relative accuracy of the capacitive elements C5 to C8 of the second DA conversion section 3 is higher than that of the capacitive elements C1 to C4 of the first DA conversion section 2, the characteristics of AD conversion are improved and the occurrence of defects can be prevented. .

[0018]

In the conventional A / D converter described above, if the characteristics of AD conversion do not satisfy the standard due to manufacturing problems or the like, the operation as the setting unit of the reference level voltage is changed from one to the other. By switching to the DA converter, the defect occurrence rate is suppressed.

In the A / D converter, a multiplexer having a plurality of analog input terminals selects one input analog signal as the input voltage Vin in order to cope with the increase in the number of channels. The signal line through which the input voltage Vin is transmitted has a parasitic capacitance proportional to the number of analog input terminals. The parasitic capacitance on the signal line increases as the number of channels increases. When the parasitic capacitance on the signal line increases, the transmission speed of the input voltage Vin from the signal source having a high output impedance decreases, and the input voltage Vin cannot be sampled accurately.

As a measure for reducing the parasitic resistance on the signal line, the size of the transistor forming the multiplexer is increased to reduce the on-resistance. Increasing the transistor size also increases the parasitic capacitance,
There is a trade-off relationship between reducing the parasitic resistance and reducing the parasitic capacitance, and it becomes difficult to satisfy the conditions for both multichannel and high speed.

Further, once measured after the IC is manufactured and judged to be good, the second DA converter 3 is left unused without having the ability to sufficiently function as a reference level voltage setting unit. It will not be used effectively.

The present invention has been made in order to solve the problems of the above-mentioned conventional techniques, and is capable of satisfying both conditions of multichannel and high speed.
The purpose is to provide a converter.

[0023]

In order to achieve the above object, an A / D converter of the present invention comprises a comparator having a positive phase input terminal and a negative phase input terminal, and a negative phase input terminal and a positive phase input terminal. To a ground line, a first capacitor group including a plurality of capacitors having one end commonly connected to the negative-phase input terminal, and one end commonly connected to the positive switch. A second capacitor group composed of a plurality of capacitors connected to the phase input terminal and the other end of each capacitor of the first capacitor group are connected to a first signal line, two power supply lines having mutually different polarities, or A first multiplexer group consisting of a plurality of multiplexers selectively connected to a ground line, and the other end of each capacitor of the second capacitor group to a second signal line,
A second multiplexer group including a plurality of multiplexers selectively connected to the two power supply lines or the ground line, and a first multiplexer group for selectively connecting a predetermined number of input analog signals to the first signal line. An input multiplexer, a second input multiplexer that selectively connects a predetermined number of input analog signals to the second signal line, and a determination circuit that determines the polarity of the output of the comparator, An initialization mode in which the second switch is turned on, and the other end of each capacitor belonging to one of the first and second capacitor groups is connected to a corresponding signal line and belongs to the other capacitor group of the capacitor groups. The sampling mode in which the other end of each capacitor is connected to the ground line and the other end of the capacitors belonging to the one group are temporarily connected to the power supply line. Connected to one, then successively switched to other selectively the power supply line, and,
Operate sequentially in binary mode in which each other end of the capacitors of the other capacitor group is connected to the ground line,
The determination circuit determines a change in polarity of the output of the comparator in the binary mode.

In the A / D converter of the present invention, the two signal lines consisting of the input multiplexer, the multiplexer group, and the capacitor group are independently provided between the signal source for generating the input analog signal and the comparator. ,
Since the increase in the parasitic capacitance of the comparator caused by the increase in the number of channels is suppressed and the parasitic capacitance of the signal line is reduced, it is possible to satisfy both the conditions of increasing the number of channels and increasing the speed.

In the A / D converter of the present invention, the comparator has a positive phase output terminal and a negative phase output terminal, and the judging circuit selects one of the positive phase output terminal and the negative phase output terminal of the comparator. It is preferable to provide a selector that In this case, since the output side of the comparator has a switching function, the capacitor group and the input side of the comparator can be directly connected, so that the parasitic resistance and parasitic capacitance on the input side of the comparator can be reduced.

There is provided a voltage follower selectively connected between the output terminal of at least one of the first and second input multiplexers and the other end of each capacitor of the corresponding capacitor group, and the voltage follower comprises: It is also a preferred embodiment of the present invention to operate in another sampling mode instead of the above sampling mode. in this case,
By operating the voltage follower, an analog input signal from a signal source having a high output impedance can be accurately sampled.

Further, the A / D converter of the present invention comprises a comparator having a positive phase input terminal and a negative phase input terminal, and a first comparator for connecting the negative phase input terminal and the positive phase input terminal to the ground line, respectively. And a second switch, a first capacitor having one end connected to the negative phase input terminal, a second capacitor having one end connected to the positive phase input terminal, and a positive power supply and a negative power supply. A resistor ladder circuit having taps for outputting a plurality of output voltages, and a second end selectively connecting the other end of the first capacitor to a first signal line, a ground line, or each tap of the resistor ladder. 1 multiplexer and a second multiplexer for selectively connecting the other end of the second capacitor to a second signal line, a ground line, or each tap of the resistance ladder, and a predetermined number of input analog signals. A first input multiplexer for selectively connecting to the first signal line, a second input multiplexer for selectively connecting a predetermined number of input analog signals to the second signal line, and an output of the comparator A determination circuit for determining the polarity of the
An initialization mode of turning on the switch, a sampling mode in which one other end of the first and second capacitors is connected to a corresponding signal line, and the other end of the capacitor is connected to a ground line, The other end of one capacitor is sequentially switched to each tap of the resistor ladder, and the other end of the other capacitor is sequentially operated in a binary mode in which the other end is connected to a ground line. It is characterized in that the polarity change of the output of the comparator is determined in the mode.

In the A / D converter of the present invention, the resistance ladder circuit sets the reference level voltage, so that the DA conversion section using the resistance element is more monotonic than the DA conversion section using the capacitance element. As a result, the requirement for manufacturing accuracy is relaxed.

[0029]

DETAILED DESCRIPTION OF THE INVENTION A of the present invention will now be described with reference to the drawings.
The A / D converter of the present invention will be described in more detail based on an example embodiment of the / D converter. FIG. 1 is a circuit diagram of an A / D converter according to a first embodiment of the present invention. This A / D converter converts an input analog signal of 8 channels into a digital amount with a resolution of 3 bits.

The 8 channel input analog signal is the first
The input voltages Vin1 to Vin4 belonging to the input group and the input voltages Vin5 to Vin8 belonging to the second input group are assigned and processed.

The A / D converter includes a first DA conversion section 2 and a second DA conversion section.
DA converter 3, comparator 4, selector 5, control circuit 6 (determination circuit), first input multiplexer 7,
It comprises a second input multiplexer 8 and ground switches S9 and S10 (first and second switches). 1st D
The A conversion unit 2 includes capacitive switches S1 to S4 (first multiplexer group) and capacitive elements C1 to C4 (first capacitor group), and the second DA conversion unit 3 includes the capacitive switch S1.
5 to S8 (second multiplexer group) and the capacitive element C5
.About.C8 (second capacitor group). The first input multiplexer 7 is composed of selection switches M1 to M4, and the second input multiplexer 8 is composed of selection switches M5 to M4.
Composed of M8.

The first input multiplexer 7 and the second input multiplexer 8 have a function of selecting 4 inputs and 1 output.
The output terminal of the first input multiplexer 7 has an input voltage Vin
1 to Vin4 are input via the selection switches M1 to M4, respectively. The first input multiplexer 7 inputs the input voltage VinA from the output terminal to the first DA converter 2. Input voltages Vin5 to Vin8 are input to the output terminals of the second input multiplexer 8 via the selection switches M5 to M8, respectively. Second
The input multiplexer 8 receives the input voltage VinB from the output terminal.
Is input to the second DA converter 3.

The input voltage VinA or the ground potential is input to the output terminal of the first DA conversion section 2 via the capacitance switch S1 and the capacitance element C1, and the capacitance switch S2 and the capacitance element C2, and the capacitance switch S3 and the capacitance element S3. Input voltage VinA, via C3 or capacitive switch S4 and capacitive element C4,
The reference voltage VF +, VF- or the ground potential is input.

The output terminal of the second DA converter 3 receives the input voltage VinB or the ground potential via the capacitance switch S5 and the capacitance element C5, and the capacitance switch S6 and the capacitance element C6, and the capacitance switch S7 and the capacitance element C7. Alternatively, the input voltage VinB, the reference voltages VF +, VF−, or the ground potential is input via the capacitance switch S8 and the capacitance element C8.

The output terminal of the first DA converter 2 is connected to the negative phase comparison input terminal of the comparator 4, and the ground switch S
Connected to ground through 9. The output terminal of the second DA converter 3 is connected to the positive phase comparison input terminal of the comparator 4, and is connected to the ground via the ground switch S10. The comparator 4 inputs the comparison result signal 101 from the positive phase output terminal and the comparison result signal 102 from the negative phase output terminal to the selector 5, respectively. The comparison result signal 102 is an inverted signal of the comparison result signal 101.

The selector 5 selects either the comparison result signal 101 or the comparison result signal 102 based on the select signal Φs and inputs it to the control circuit 6 as the selection signal 103. The control circuit 6 inputs the control signal 104 to the first DA converter 2 or the second DA converter 3, and generates a conversion result signal 105.

First DA converter 2 or second DA converter 3
Generates a reference level voltage when the capacitance switches S1 to S4 or S5 to S8 select the reference voltage based on the control signal 104.

The first input multiplexer 7 is an internal signal corresponding to the analog input terminal of the first input group to be used.
One of sel1 to sel4 is generated, the corresponding one of the selection switches M1 to M4 is turned on, and the corresponding one of the input voltages Vin1 to Vin4 is input to the first DA conversion unit 2 as the input voltage VinA.

The second input multiplexer 8 is an internal signal corresponding to the analog input terminal of the second input group to be used.
One of sel5 to sel8 is generated, the corresponding one of the selection switches M5 to M8 is turned on, and the corresponding one of the input voltages Vin5 to Vin8 inputs the input voltage VinB to the second DA converter 3.

FIG. 2 is a table showing processing performed according to the analog input terminal used. The A / D converter performs processing belonging to the first input group or the second input group according to the analog input terminal used.

In the case of the process belonging to the first input group, any one of the input voltages Vin1 to Vin4 is input as the input voltage VinA. The first DA converter 2 operates as a reference level voltage setting unit, and the second DA converter 3 operates as a capacitive load unit for differential input. Select signal Φs is L
Set to level.

The selector 5 selects the comparison result signal 101 from the positive phase output terminal of the comparator 4 and outputs the selection signal 10
Occurs as 3. The control circuit 6 generates a control signal 104 for performing an operation belonging to the first input group based on the L-level select signal Φs.

In the case of the process belonging to the second input group, any one of the input voltages Vin5 to Vin8 is input as the input voltage VinB. The first DA conversion section 2 operates as a capacitive load section for differential input, and the second DA conversion section 3 operates as a reference level voltage setting section. Select signal Φs is H
Set to level.

The selector 5 has an H level select signal Φ.
Based on s, the comparison result signal 102 from the negative phase output terminal of the comparator 4 is selected and generated as the selection signal 103. The control circuit 6 generates a control signal 104 for performing a process belonging to the second input group based on the H-level select signal Φs.

Here, the operation of AD conversion will be described in detail. In the AD conversion operation, an initialization operation and a binary search operation are performed. First, the A / D converter performs a process belonging to the first input group and uses the first analog input terminal. The input analog signal from the first analog input terminal is input as the input voltage Vin1.

The first input multiplexer 7 has an internal signal se.
l1 is generated, the selection switch M1 is turned on, and the input voltage Vi
The n1 is input to the first DA converter 2 as the input voltage VinA.

During the initialization operation, the A / D converter generates an H level precharge signal Φb. Ground switch S9
And S10 are turned on. In the comparator 4, both the comparison reference voltage Vcp2 at the positive phase comparison input terminal and the comparison target voltage Vcp1 at the negative phase comparison input terminal become the ground potential.

The value of the comparison target voltage Vcp1 changes based on the set reference level voltage each time three searches are performed. The comparison reference voltage Vcp2 is kept at the ground potential until the three searches are completed. Comparator 4
Since the operating point (comparison reference voltage) for comparing the input voltage VinA with the reference level voltage is determined, the differential input is biased.

FIG. 3 shows an equivalent circuit of the first DA converter 2, the second DA converter 3, and the comparator 4 during the initialization operation. The capacitance switches S5 to S8 all select the ground potential based on the control signal 104. The combined capacitance CB including the capacitance elements C5 to C8 is discharged and samples the ground potential.

The capacitance switches S1 to S4 all select the input voltage VinA based on the control signal 104.
The combined capacitance CA0 composed of the capacitive elements C1 to C4 has a charge Q1
Is stored, and the input voltage VinA is sampled with the side to which the first DA converter 2 is connected as positive. The charge Q1 is shown as follows. Q1 = CA0 × VinA ... (1)

During the binary search operation, the A / D converter generates an L level precharge signal Φb. The ground switches S9 and S10 are turned off. Comparison target voltage Vcp1
Changes according to the reference level voltage set by the first DA converter 2, and the comparison reference voltage Vcp2 becomes the ground potential. In the binary search, the search is performed three times.

FIG. 4 shows the first operation during the binary search.
An equivalent circuit of the DA converter 2, the second DA converter 3, and the comparator 4 is shown. The combined capacitance CA1 is formed of the capacitive elements C1 to C4 connected to the reference voltage VF +, and the combined capacitance CA2
Are formed of capacitive elements C1 to C4 connected to the reference voltage VF-.

The positive phase comparison input terminal of the comparator 4 is connected to the ground via the combined capacitance CB, and the negative phase comparison input terminal of the comparator 4 is connected to the reference voltage via the combined capacitors CA1 and CA2. The combined capacity CB is the combined capacity CA
Equal to the sum of 1 and CA2. The comparator 4 balances the capacitive loads on both the differential inputs when viewed as an alternating current,
Common-mode signal components, power supply voltage fluctuation components, etc. are removed.

The combined capacitors CA1 and CA2 hold the sampled voltage with the side connected to the reference voltage being positive. The charge Q2 stored in the combined capacitors CA1 and CA2 is shown as follows. Q2 = CA1 × {(VF +) − Vcp1} + CA2 × {(VF −) − Vcp1} (2) Here, since there is a relation of Q1 = Q2 and CA0 = CA1 + CA2, the equations (1) and ( From 2), the comparison target voltage Vcp1 is
Shown below. Vcp1 = [{CA1 × (VF +)} + {CA2 × (VF-)}] / CA0−VinA ... (3)

FIG. 5 shows details of the reference level voltage set by the first DA converter 2. FIG. 10A is a table showing the relationship between the reference voltage selected by the capacitance switches S1 to S4 and the combined capacitance CA0 to CA2. The first DA converter 2 changes the values of the combined capacitors CA1 and CA2 based on the control signal 104 to set the reference level voltages Vf0 to Vf7.

FIG. 7B shows reference level voltages Vf0 to Vf7.
And the reference voltages VF + and VF- are shown. The reference level voltages Vf0 to Vf7 indicate potentials that are sequentially assigned from the negative electrode side to the positive electrode side by dividing the potential difference between the reference voltages VF + and VF− into eight equal parts. The reference level voltage Vf4 is an intermediate potential between the reference voltage VF + and the reference voltage VF-.

The first term of the equation (3) is the reference level voltage Vf0 to Vf7 set by the first DA converter 2. The comparison target voltage Vcp1 becomes negative when the input voltage VinA is higher than the set reference level voltage, and becomes positive when the input voltage VinA is lower than the set reference level voltage.

The comparator 4 compares the comparison reference voltage Vcp2, which is the ground potential, with the comparison target voltage Vcp1 to obtain Vcp
If 2> Vcp1, the comparison result signals 101 and 102 are set to H.
And L level, respectively, and if Vcp2 <Vcp1, the comparison result signals 101 and 102 are set to L level and H level, respectively. The selector 5 selects the comparison result signal 101 as the selection signal 103 based on the L level select signal Φs.

The control circuit 6 determines that the input voltage VinA is higher than the set reference level voltage when the selection signal 103 is at the H level, and the set reference level when the selection signal 103 is at the L level. It is determined that the input voltage VinA is lower than the voltage.

The control circuit 6 determines the reference voltage selected by the capacitance switch S4 in the first search,
The reference voltage selected by the capacitance switch S3 is determined by the third search, and the reference voltage selected by the capacitance switch S2 is determined by the third search.

In the first search, the input voltage VinA is compared with the reference level voltage Vf4. Control circuit 6
Generates the control signal 104 of the reference level voltage Vf4 and performs the first search. The capacitance switch S4 selects the reference voltage VF +, and the capacitance switches S2 and S3 select the reference voltage VF-.

When the first search result is VinA> Vf4, the control circuit 6 determines that the selection of the capacitance switch S4 is the reference voltage VF +, and performs the second search as the reference level voltage Vf6. Capacitance switch S3 and S4
Selects the reference voltage VF +, and the capacitance switch S2 selects the reference voltage VF-.

When the result of the first search is VinA <Vf4, the control circuit 6 determines that the selection of the capacitance switch S4 is the reference voltage VF-, and performs the second search as the reference level voltage Vf2. The capacitance switch S3 selects the reference voltage VF +, and the capacitance switches S2 and S4 select the reference voltage VF-.

If the second search result is VinA> Vf6, it is determined that the selection of the capacitance switch S3 is the reference voltage VF +, and the third search is performed as the reference level voltage Vf7. The capacitance switches S2 to S4 select the reference voltage VF +.

When the second search result is VinA <Vf6, it is determined that the selection of the capacitance switch S3 is the reference voltage VF-, and the third search is performed with the reference level voltage Vf5. The capacitance switches S2 and S4 select the reference voltage VF +, and the capacitance switch S3 selects the reference voltage VF-.

When the result of the second search is VinA> Vf2, it is determined that the selection of the capacitance switch S3 is the reference voltage VF +, and the third search is performed with the reference level voltage Vf3. The capacitance switches S2 and S3 select the reference voltage VF +, and the capacitance switch S4 selects the reference voltage VF-.

When the second search result is VinA <Vf2, it is determined that the selection of the capacitance switch S3 is the reference voltage VF-, and the third search is performed with the reference level voltage Vf1. The capacitance switch S2 selects the reference voltage VF +, and the capacitance switches S3 and S4 select the reference voltage VF-.

The third search result is VinA> Vf7 or Vi.
If nA <Vf7, it is determined that the selection of the capacitance switch S2 is the reference voltage VF + or VF-, respectively, and the conversion result signal 105 corresponding to Vf7 or Vf6 is generated, and the search is ended.

The third search result is VinA> Vf5 or Vi.
If nA <Vf5, it is determined that the selection of the capacitive switch S2 is the reference voltage VF + or VF-, respectively, the conversion result signal 105 corresponding to Vf5 or Vf4 is generated, and the search is ended.

The result of the third search is VinA> Vf3 or Vi.
When nA <Vf3, it is determined that the selection of the capacitance switch S2 is the reference voltage VF + or VF-, respectively, the conversion result signal 105 corresponding to Vf3 or Vf2 is generated, and the search is ended.

The third search result is VinA> Vf1 or Vi.
When nA <Vf1, it is determined that the selection of the capacitance switch S2 is the reference voltage VF + or VF-, respectively, and the conversion result signal 105 corresponding to Vf1 or Vf0 is generated, and the search is ended.

Next, the A / D converter performs the process belonging to the second input group and uses the fifth analog input terminal. The input analog signal from the fifth analog input terminal is input as the input voltage Vin5.

The second input multiplexer 8 has an internal signal se.
l5 is generated, the selection switch M5 is turned on, and the input voltage Vi
The signal n5 is input to the second DA converter 3 as the input voltage VinB.

The A / D converter performs an initialization operation and a binary search operation as a process belonging to the second input group. The initialization operation and the binary search operation are similar to the processing belonging to the first input group.

The input voltage is transmitted on the signal line via the multiplexer. The output terminal of the multiplexer is
It has a parasitic capacitance proportional to the number of analog input terminals. There is a parasitic capacitance of the multiplexer in the signal line through which the input voltage is transmitted.

Since the A / D converter (prior art) of FIG. 8 corresponds to an analog input terminal of 8 channels, one 8
An input multiplexer and one signal line are adopted.
The A / D converter (present invention) of FIG. 1 employs two 4-input multiplexers and two signal lines.

For example, the parasitic capacitance for one analog input terminal of the multiplexer is set to 1 pF. When the parasitic capacitance of the signal line is converted into one, the A / D converter of FIG. 8 becomes 1 pF × 8 = 8 pF, and the A / D converter of FIG.
F × 4 = 4 pF. According to the present invention, under the condition that the number of analog input terminals is the same, the parasitic capacitance of the signal line is halved as compared with the conventional example.

In the A / D converter of FIG. 1, since the output side of the comparator has a switching function, the capacitor group and the input side of the comparator can be directly connected.
It is possible to reduce the parasitic resistance and parasitic capacitance on the input side of the comparator.

For example, the series resistance formed by the selection switches M1 to M8 and the capacitance switches S1 to S8 on the signal line is set to 1 KΩ, and the input capacitance of the D / A converter is set to 4 pF.
Converting the time constant of the signal line into one, A in Fig. 8
/ D converter is (8pF + 4pF) × 1KΩ = 120ns
And the A / D converter of FIG. 1 is (4 pF + 4 pF) × 1
KΩ = 80 ns.

If the A / D converter has a resolution of 10 bits, a sampling time of about 10 times the time constant of the signal line is required to accurately sample the input voltage from the analog input terminal. According to the present invention, under the condition that the number of analog input terminals is equal, the sampling time becomes 2/3 as compared with the conventional example. When the number of analog input terminals is large, the sampling time can be further shortened.

According to the above-described embodiment, since the two signal lines consisting of the input multiplexer, the multiplexer group, and the capacitor group are independently present between the signal source for generating the input analog signal and the comparator, it is possible to increase the number of signals. Since the increase in the parasitic capacitance of the comparator that occurs with the channelization is suppressed and the parasitic capacitance of the signal line is reduced,
It is possible to satisfy the conditions of both multi-channel and high speed.

FIG. 6 shows an A / D of the second embodiment of the present invention.
It is a circuit diagram of a converter. The present embodiment example is different from the previous embodiment example in that the process belonging to the first input group can deal with a signal source having a high output impedance as compared with the process belonging to the second input group. The process belonging to the second input group is the same as that of the previous embodiment, and the description thereof is omitted.

The A / D converter has a buffer amplifier 10. The buffer amplifier 10 operates as a voltage follower, generates an input voltage VinC from the input voltage VinA, and inputs the input voltage VinC to the first DA converter 2.

The A / D converter performs the process belonging to the first input group, and performs the initialization operation and the binary search operation using the first analog input terminal.

In the initialization operation, the differential input of the comparator 4 is biased. First, the capacitance switches S1 to S4
Selects the input voltage VinC. The combined capacitance CA0 including the capacitive elements C1 to C4 samples the input voltage VinC as the first sampling for the input voltage Vin1. Next, the capacitance switches S1 to S4 select the input voltage VinA. The combined capacitance CA0 is 2 with respect to the input voltage Vin1.
As the second sampling, the input voltage VinA is sampled. Sampling is performed twice for the input voltage Vin1. After that, the operation of the binary search becomes the same as that of the previous embodiment.

The input voltage belonging to the first input group is sampled twice through the buffer amplifier 10 and sampling not through the buffer amplifier 10. In the first sampling, the buffer amplifier 10
Since the impedance conversion (voltage follower) operation is not affected by the high output impedance of the signal source, the input voltage VinC is accurately sampled. In the second sampling, since the error between VinA and VinC due to the influence of the offset of the buffer amplifier 10 is suppressed, the input voltage VinA is accurately sampled.

In the process belonging to the second input group, the sampling of the input voltage is performed once, so that the sampling speed is higher than that in the process belonging to the first input group.

The A / D converter can perform accurate sampling without being affected by the output impedance of the signal source by the process belonging to the first input group, and can perform high-speed sampling by the process belonging to the second input group.

According to the above embodiment, the voltage follower operates so that the analog input signal from the signal source having a high output impedance can be accurately sampled.

FIG. 7 shows an A / D of the third embodiment of the present invention.
It is a circuit diagram of a converter. In this embodiment, a plurality of resistors sets the reference level voltage. The A / D converter includes a resistance ladder circuit 11, a first DA conversion unit 12, and a second DA conversion unit 13.

The resistance ladder circuit 11 is composed of resistances R1 to R8 and resistance switches S1 to S8. The resistors R1 to R8 are
The reference voltage VF− to the reference voltage VF + are connected in series in this order. One ends of the resistance switches S1 to S8 are respectively connected to the taps of the resistances R1 to R8 connected in series,
The other ends of the resistance switches S1 to S8 are all connected to the output terminals of the resistance ladder circuit 11.

Any one of the resistance switches S1 to S8 is turned on based on the control signal 104. The resistance ladder circuit 11 outputs the reference level voltages Vf0 to Vf7 set by the resistance switches S1 to S8 from the output terminal to the first DA conversion unit 1.
2 and input to the second DA converter 13.

The first DA converter 12 has a function switch S11.
To S13 (first multiplexer) and a capacitive element C11 (first capacitor). The input voltage VinA is input to one end of the capacitive element C11 via the functional switch S11, the ground potential is input via the functional switch S12, and the reference level voltage is input via the functional switch S13. The other end of the capacitive element C11 is connected to the negative phase comparison input terminal of the comparator 4.

The second DA converter 13 has a function switch S14.
.About.S16 (second multiplexer) and a capacitive element C12 (second capacitor). The input voltage VinB is input to the one end of the capacitive element C12 via the functional switch S14, the ground potential is input via the functional switch S15, and the reference level voltage is input via the functional switch S16. The other end of the capacitive element C12 is connected to the positive phase comparison input terminal of the comparator 4.

Function switches S11-S13 and S14-S16
One of the two turns on depending on the processing performed by the A / D converter. The capacitive element C11 or C12 corresponds to the combined capacitance CA or CB.

Now, the operation of the A / D converter will be described. Since the process belonging to the second input group is performed in the same manner as the process belonging to the first input group, its description is omitted.

In the case of processing belonging to the first input group, the first DA converter 12 operates as a reference level voltage setting unit. The function switch S12 is turned off until the processing belonging to the first input group is completed.

During the initialization operation, the ground switches S9 and S1
0 turns on. The function switch S11 is turned on and the function switch S13 is turned off. The capacitive element C11 has an input voltage VinA
To sample. The electric charge is discharged to the capacitive element C12. The comparison reference voltage Vcp2 becomes the ground potential.

During the binary search operation, the ground switches S9 and S10 are turned off. The function switch S11 turns off and the function switch S13 turns on. The reference level voltage from the resistance ladder circuit 11 is applied to the capacitive element C11.
The comparison target voltage Vcp1 is the difference voltage between the set reference level voltage and the sampled input voltage VinA.

The second DA conversion section 13 operates as a capacitive load section for differential input. The function switches S14 and S16 are
It is turned off until the processing belonging to the first input group is completed. The function switch S15 is turned on until the processing belonging to the first input group is completed.

The comparator 4, the selector 5, and the control circuit 6 operate in the same manner as in the previous embodiment.

According to the above embodiment, the resistance ladder circuit sets the reference level voltage, so that the monotonicity of the DA conversion section using the resistance element is guaranteed as compared with the DA conversion section using the capacitance element. Therefore, the requirement for manufacturing accuracy is relaxed.

Although the present invention has been described above based on its preferred embodiments, the A / D converter of the present invention is not limited to the configuration of the above-mentioned embodiments, and the above-mentioned embodiments are not limited thereto. The A / D converter in which various modifications and changes are made from the above configuration is also included in the scope of the present invention.

[0104]

As described above, in the A / D converter of the present invention, two signal lines for dividing a plurality of analog input terminals into two groups are independently present, and one signal line is provided. The parasitic capacitance of is reduced by half. A selector having a selection function is arranged after the comparator to reduce the parasitic capacitance and parasitic resistance on the signal line. in this case,
Since the sampling time can be shortened, the conversion operation can be speeded up.

If the sampling times are designed to be the same, the number of analog input terminals can be doubled,
Further, one of the two divided input groups can be made to correspond to the input voltage from the signal source having a high output impedance, and the other can be made to correspond to the input voltage required to operate at high speed. In this case, it is possible to perform processing that is highly adaptable to the intended use.

[Brief description of drawings]

FIG. 1 is a circuit diagram of an A / D converter according to a first embodiment of the present invention.

FIG. 2 is a table showing processing performed according to an analog input terminal used.

FIG. 3 shows a first DA conversion unit 2 and a second DA during an initialization operation.
An equivalent circuit of the conversion unit 3 and the comparator 4 is shown.

FIG. 4 shows an equivalent circuit of a first DA conversion unit 2, a second DA conversion unit 3 and a comparator 4 during a binary search operation.

FIG. 5 shows details of a reference level voltage set by the first DA converter 2.

FIG. 6 is a circuit diagram of an A / D converter according to a second embodiment of the present invention.

FIG. 7 is a circuit diagram of an A / D converter according to a third embodiment of the present invention.

FIG. 8 is a circuit diagram of an A / D converter described in Japanese Patent No. 2952931.

[Explanation of symbols]

2, 12 First DA conversion unit 3, 13 Second DA conversion unit 4 Comparator 5 Selector 6 Control circuit (decision circuit) 7 First input multiplexer 8 Second input multiplexer 9 Logic circuit 10 Buffer amplifier 11 Resistance ladder circuit 101, 102 Comparison result Signal 103 Selection signal 104 Control signal 105 Conversion result signals C1 to C4, C5 to C8 Capacitive elements (first and second capacitor groups) C11, C12 Capacitive elements (first and second capacitors) S1 to S4, S5 to S8 capacitance switch (first and second multiplexer group) S11 to S13, S14 to S16 function switch (first and second multiplexer)
Multiplexer)

─────────────────────────────────────────────────── ─── Continuation of the front page (56) Reference JP-A-3-231518 (JP, A) JP-A-63-300627 (JP, A) JP-A-5-14202 (JP, A) JP-A 2000-59220 (JP, A) JP 2000-201077 (JP, A) JP 7-193507 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) H03M 1/00-1/88

Claims (5)

(57) [Claims] 1. A comparator having a positive-phase input terminal and a negative-phase input terminal, first and second switches for connecting the negative-phase input terminal and the positive-phase input terminal to a ground line, respectively, and having one end commonly A first capacitor group composed of a plurality of capacitors connected to the negative phase input terminal; a second capacitor group composed of a plurality of capacitors having one end commonly connected to the positive phase input terminal; The other end of each capacitor of the first capacitor group is
Signal line, two power lines with different polarities,
Alternatively, a first multiplexer group including a plurality of multiplexers selectively connected to a ground line, and the other end of each capacitor of the second capacitor group are
Second multiplexer group consisting of a plurality of multiplexers selectively connected to the signal line, the two power supply lines, or the ground line, and a predetermined number of input analog signals are selectively connected to the first signal line A first input multiplexer, a second input multiplexer that selectively connects a predetermined number of input analog signals to the second signal line, and a determination circuit that determines the polarity of the output of the comparator, An initialization mode in which the first and second switches are turned on, and the other end of each capacitor belonging to one of the first and second capacitor groups is connected to a corresponding signal line, and the other of the capacitor groups is connected. A sampling mode in which the other end of each capacitor belonging to the capacitor group is connected to the ground line, and the other end of the capacitor belonging to the one group is Once connected to one of the power supply lines, then selectively switched to the other of the power supply lines in sequence, and in binary mode in which each other end of the capacitors of the other capacitor group is connected to the ground line. A / D, wherein the determination circuit is operable to determine the polarity change of the output of the comparator in the binary mode.
converter. 2. The comparator includes a positive-phase output terminal and a negative-phase output terminal, and the determination circuit includes a selector that selects one of a positive-phase output terminal and a negative-phase output terminal of the comparator. A / D converter described in 1. 3. A voltage follower selectively connected between at least one output terminal of the first and second input multiplexers and the other end of each capacitor of a corresponding capacitor group, the voltage follower. The A / D converter according to claim 1 or 2, which operates in another sampling mode instead of the sampling mode. 4. A comparator having a positive-phase input terminal and a negative-phase input terminal, first and second switches for connecting the negative-phase input terminal and the positive-phase input terminal to a ground line, respectively, one end of which is the reverse A first capacitor connected to the phase input terminal; a second capacitor having one end connected to the positive phase input terminal; and a tap connected between the positive power supply and the negative power supply for outputting a plurality of output voltages. A resistor ladder circuit, a first multiplexer that selectively connects the other end of the first capacitor to a first signal line, a ground line, or each tap of the resistor ladder, and the second capacitor A second multiplexer for selectively connecting the other end of the first signal line to a second signal line, a ground line, or each tap of the resistance ladder; and a predetermined number of input analog signals for selectively selecting the first signal. A first input multiplexer connected to the line; a second input multiplexer selectively connecting a predetermined number of input analog signals to the second signal line; and a determination circuit for determining the polarity of the output of the comparator. An initialization mode in which the first and second switches are turned on, one end of the first and second capacitors is connected to a corresponding signal line, and the other end of the capacitor is connected to a ground line. And a binary mode in which the other end of the one capacitor is sequentially switched to each tap of the resistance ladder and the other end of the other capacitor is connected to a ground line. The A / D is characterized in that the judging circuit judges a polarity change of the output of the comparator in the binary mode.
converter. 5. The comparator includes a positive phase output terminal and a negative phase output terminal, and the determination circuit includes a selector that selects one of a positive phase output terminal and a negative phase output terminal of the comparator. A / D converter described in 1.