JP3414281B2 - Test equipment - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a test device, and more particularly to a test device having a plurality of channels.

[0002]

2. Description of the Related Art Conventionally, a test device for testing the operation of a circuit or a CPU has been known. For example, JP-A-9
Japanese Patent Publication No. 269359 discloses an integrated circuit test device including a plurality of microcomputers (microcomputers) and each microcomputer is directly connected to an integrated circuit device. The program and data information necessary for the test are supplied to the microcomputer, and each microcomputer tests the integrated circuit by sending back the test result to the tester.

[0003]

In the above-mentioned prior art, since different test programs can be executed for each microcomputer, a plurality of types of integrated circuits can be tested at the same time, but the configuration of the test apparatus becomes complicated and large. There is a problem that the cost increases.

In particular, when trying to test the operation of a plurality of CPUs in an ECU (electronic control unit) mounted on a vehicle, there is a strong demand for quickly testing the operation of a plurality of CPUs with a simple device.

The present invention has been made in view of the above problems of the prior art, and an object thereof is to provide an apparatus capable of testing the operation of a plurality of types of processors with a simple configuration.

[0006]

In order to achieve the above object, a first invention is to connect an ECU having a plurality of CPUs.
A test device for continuously testing, which is provided for each of a plurality of channels and has a plurality of CPUs of the ECU.
Each has an interface card connected thereto, a memory connected to each interface card and having at least two ports, and a processing unit connected to each memory and capable of uniformly reading out data stored in each memory. and, each interface card for each CPU
Interface corresponding to the type and its debugging method
The processing data of each CPU is provided.
Each interface card has a function to store in memory
Can be freely attached to and detached from the test equipment, and EC
Configure the test equipment according to U,
It is characterized in that the ECU is tested. By using the interface card, it is possible to eliminate the difference in the type of the device under test connected to each channel. In addition, by writing data from the test target using one port of the memory having two or more ports and reading the data uniformly using the other ports, even if a plurality of test targets exist, Data can be processed uniformly.
Here, “unified processing” means processing a plurality of data as one unit. In addition, “universally readable” means not only unified reading but also reading separately for each channel. Further, by making the interface card detachable, it is possible to easily and quickly respond to the type of the test object.

[0007] The second invention according to the first invention, the the interface card and the memory, characterized in that that will be connected by a common bus.

[0008] The ECU is connected directly to each channel.
In addition to being connected indirectly (via other members)
Good.

[0009]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows a block diagram of the configuration of this embodiment. The ECU (electronic control unit) 10 as a test target includes a plurality of CPUs 10a, 10b, 10c, 1
It has 0d. CPU 10a is 16 bit, CPU
10b is 32 bits, CPU 10c is 16 bits, CP
U10d is a 32-bit CPU. 32 bit C
The PUs 10b and 10d are NBDs (Non-Break-
Debug-port).

On the other hand, a measuring device ( test device) 12 for testing the ECU 10 has interface cards (I / F) 12a to 12d provided for each channel and a DPRAM provided corresponding to each interface card 12a to 12d. (Dual port RAM) 14a-14
d, personal computer (personal computer) 16, interface cards 12a to 12d and DPRAM 14a to
14d connecting buses 200a to 200d and DPRA
Bus 300 connecting M14a to 14d and personal computer 16
Is configured.

The interface cards 12a and 12c are connected to the CPUs 10a and 10c in the ECU 10 via buses 100a and 100c, respectively, and CP
The data processed by the U10a (data from the sensor, etc.) is stored in the DPRAM 14a, and the data processed by the CPU 10c is stored in the DPRAM 14c.

The interface cards 12b and 12d are connected to the ECU via NBD buses 100b and 100d, respectively.
It is connected to CPUs 10b and 10d in
The data from the U10b is processed by the built-in NBD processing unit (the data is transmitted and received with the 32-bit high-speed CPUs 10b and 10d serially) and stored in the DPRAM 14b, and the data from the CPU 10d is processed by the built-in NBD processing unit and the DPRAM 14d. To store.

That is, the interface card 12a
12d provide interfaces corresponding to the types of the CPUs 10a to 10d in the ECU 10 and their debugging methods, and have a function of storing the processing data of the CPUs 10a to 10d in the DPRAMs 14a to 14d. The interface cards 12a to 12d and the DPRA
It is preferable that the buses 200a to 200d between the M14a to 14d be a common bus.
It is preferable that 2a to 12d be detachably attached to the measuring device 12. This allows the ECU to be tested
This is because the configuration of the measuring device 12 can be easily optimized according to 10.

The DPRAMs 14a to 14d have two ports, and one of the ports is used for the CPUs 10a to 14d.
Write the data from 10d. Further, the personal computer 16 reads the data written in the DPRAMs 14a to 14d by using another port. The DPRAMs 14a-1a
4d may have three or more ports, and may be a FIFO (First-In-First-Ou).
t) A memory may be used. The essence is to speed up the process by writing data from the CPUs 10a to 10d at a certain port and reading the data written at a port different from that port.

The personal computer 16 is, for example, a notebook personal computer that can be brought into a vehicle, and is connected to the I / F box via a PC card. DPRAMs 14a to 14d are mapped in the memory in the personal computer 16, and the data read from the DPRAMs 14a to 14d are stored in predetermined areas of the memory in the personal computer 16, respectively. Therefore, the CPU in the personal computer 16
By sampling the memory, the DPRAM 14a ...
Data written in 14d, that is, CPU 10a-
It becomes possible to process the data of 10d uniformly.

The configuration of this embodiment is as described above, and when testing the ECU 10 using the measuring device 12, first, each CPU in the ECU 10 is installed in each channel of the measuring device 12.
10a-10d are connected. And CPU10a-1
At 0d, the data output from the vehicle-mounted sensor is processed and output to each channel of the measuring device 12. Measuring device 12
Interface cards 12a to 12d of the CPU1
DPRAM 14a by inputting data from 0a to 10d
Write to ~ 14d. At this time, the CPUs 10a to 10d
, The synchronous data is written in the DPRAMs 14a to 14d as the processing result. After the data is stored in the DPRAMs 14a to 14d, the personal computer 16 sets the DP at a predetermined timing.
The RAMs 14a to 14d are accessed to read the data, and the read data is written to its own memory. The personal computer 16 uses the DPRAM 14 on its own memory map.
Since a to 14d are mapped, the DPRAMs 14a to 14d can be sampled by sampling their own memory.
Can be sampled uniformly. Therefore, even if synchronized data is output from the CPUs 10a to 10d, the synchronization can be tested by uniformly sampling.

As described above, in the present embodiment, by providing the interface card, the data can be processed uniformly regardless of the difference in the CPUs in the ECU 10, and the EC
Debug that can be regarded as one system for the entire U (EC
Even if each CPU in U10 operates in synchronization, the result can be tested. Moreover, since the interface card is configured to be removable, it is possible to quickly respond to any ECU.

In this embodiment, the CPU 10a
It is also possible to process the data from 10d to 10d by the personal computer 16 and send the processing result back to the CPUs 10a to 10d. Further, the data from one CPU (for example, the CPU 10a) is used as a trigger, and the personal computer 16 causes the other CPU 10 to operate.
Request data transmission from b to 10d (one CP
U is treated as a master).

In the personal computer 16, DPRAM 14a ...
Instead of processing 14d data uniformly, DPR
Of course, it is possible to test only the specific data (for example, the DPRAM 14a) among the data of the AMs 14a to 14d, read the data, and test the operation of the specific CPU (for example, the CPU 10a).

[0021]

As described above, according to the present invention, it is possible to test the operation of a plurality of types of processors with a simple structure.

[Brief description of drawings]

FIG. 1 is a configuration block diagram of an embodiment of the present invention.

[Explanation of symbols]

10 ECU, 10a-10d CPU, 12 measuring device ( test device), 12a-12d interface card, 14a-14d DPRAM.

Claims (2)

(57) [Claims] 1. An ECU including a plurality of CPUs is connected.
A test device for testing by using the ECU provided in each of a plurality of channels ,
An interface card to which a plurality of CPUs are respectively connected , a memory connected to each interface card and having at least two ports, and a processing unit connected to each memory and capable of uniformly reading data stored in each memory , And each interface card has a CPU type and its
An interface that provides a bag system
The processing data of each CPU is stored in the memory.
The interface card has a function to attach / detach each interface card to / from the test device.
The test equipment depending on the ECU under test.
A test device that is configured to perform a test of the ECU . 2. The test apparatus according to claim 1, wherein the interface card and the memory are connected by a common bus.