JP3413779B2 - FM stereo receiver - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an FM stereo receiver, and more particularly to an improvement for improving the S / N of a stereo sub signal. 2. Description of the Related Art In an FM stereo receiver, the S / N ratio of a sub-signal (E _L -E _R ) / 2, which is disadvantageous to the main signal (E _L + E _R ) / 2, in terms of S / N ratio. As an improvement method, a sub-signal is divided into bands by a narrow-band BPF group, the frequency spectrum of the sub-signal is instantaneously and instantaneously analyzed, and the frequency band components not transmitted are cut, and then the remaining frequency band components are combined. There is. However, if the analysis of the frequency spectrum of the sub-signal is performed by the sub-signal itself, a malfunction due to noise detection may occur when the S / N is deteriorated in a weak electric field or the like. Accordingly, the present inventor has previously disclosed a method of analyzing the frequency spectrum of a sub signal using a main signal having a frequency correlation with the sub signal.
No. 349005 (JP-A-5-160799) was filed. FIG. 5 shows the basic configuration of the above-mentioned prior application,
In the figure, 1 is IF amplifier and FM demodulator, 2 bandpass filters, BPF (19 kHz), 3 sub-carrier signal generator (f _p (38kHz)), the synchronous detection circuit 4, the first 5 The BPF group includes BPFs of 5-1 to 5-n. Reference numeral 6 denotes a second BPF group, and BPs of 6-1 to 6-n
F. 7 and 10 are first and second constituent circuits, and 8
Denotes a signal processing circuit, and 9 denotes a matrix circuit. In FIG. 5, first, an IF signal is input to an IF amplification and FM demodulator 1 and FM demodulated. A BPF 2 (19 kHz), a synchronous detection circuit 4, and a first BPF group 5 are connected to the output of the IF amplification and FM demodulator 1. B
The PF 2 (19 kHz) extracts a pilot signal (19 kHz) and supplies the pilot signal to the subcarrier signal generator 3. The pilot signal generator 3 generates a subcarrier signal (38 kHz) synchronized with the pilot signal,
It is supplied to the other input of the synchronous detection circuit 4. In the synchronous detection circuit 4, FM is performed by the subcarrier signal (38 kHz).
The demodulation output signal is synchronously detected, and the sub-signal (38 kHz ± 15 kHz) in the FM demodulation output signal is converted into a low-frequency signal. In a first BPF group 5, n main signals (15 kHz or less) in an FM demodulated output signal are divided into n frequency domains by n BPFs 5-1 to 5-n. Is output.
In the second BPF group 6, n sub-signals (15 kHz or less) in the output signal of the synchronous detection circuit 4 are separated into n frequency-divided BPFs 6-1 to 6-n, which divide the sub-signals into n frequency domain channels. Is output. [0006] Each BPF 6-1 of the first BPF group 6
6-n correspond to each of the BPFs 5-1 to 5-1 of the second BPF group 5.
It is assumed that the characteristics are the same as those of 5-n. The n output main signal components of the first BPF group 5 are input to the combining circuit 7 and the signal processing circuit 8, and the n output sub signal components of the second BPF group 6 are input to the signal processing circuit 8. . Synthesis circuit 7
Then, the n output main signal components of the first BPF group 5 are combined, a combined main signal {(E _L + E _R ) / 2} ′ is formed again, and supplied to the matrix circuit 9. FIG. 6 shows an example of the configuration of the signal processing circuit 8.
In FIG. 6, reference numerals 8-1 to 8-n denote signal processing units, which are amplitude detectors 21-1 to 21-n and comparators 22-1 to 22-2, respectively.
2-n, reference voltage generating circuits 23-1 to 23-n, and gain control circuits 24-1 to 24-n. In the signal processing circuit 8, the amplitudes of the n main signal components from the first BPF group 5 are detected by the amplitude detection circuit 21-.
1 to 21-n. Each detected amplitude is compared with reference voltage generation circuits 23-1 to 23 by comparison circuits 22-1 to 22-n.
A second BP, which is compared to the level set at −n and is the same as the frequency channel having a greater amplitude level
Only the gain of the sub-signal component of the frequency group of the F group 6 is controlled and passed by the corresponding one of the gain control circuits 24-1 to 24-n, and the obtained sub-signal component is synthesized by the synthesis circuit 10. supplying a synthetic sub signal to the matrix circuit _{9 {(E L -E R)} / 2} ' after. That is, a frequency analysis (n channels) of the main signal (E _L + E _R ) / 2 is performed, and a sub-signal channel component corresponding to a channel having a low amplitude level among the main signal components is suppressed, whereby the sub-signal is suppressed. Is reduced and the SN ratio is improved. In the matrix circuit 9, the combined main signal (E _L + E _R ) / 2 and the combined sub signal ｛(E _L -E _R ) /
The addition and subtraction of 2｝ ′ are performed to generate stereo signals E _L ′ (left signal) and E _R ′ (right signal). As described above, in the prior application, the main signal (E
_Using the frequency correlation between _L + E _R ) / 2 and the sub-signal (E _L -E _R ) / 2, the S / N of the sub-signal whose S / N deteriorates remarkably in a weak electric field or the like is improved by the sub-signal S. / N is better than the main signal (if the sub-signal S / N is improved by the sub-signal itself when the S / N is deteriorated, a malfunction may occur due to noise). However, it has been found that such a system of the prior application still has room for improvement as described below. That is, in the method of the prior application, not only is there no effect in a strong electric field having a good S / N (because there is no S / N deterioration of the sub-signal), but also a case where normal stereo reproduction cannot be performed may occur.
For example, in the case of a signal of E _L = −E _R (the L signal and the R signal have the same frequency, the same amplitude, and opposite phases), the main signal becomes 0, and the originally output stereo signal (E _L ′ = −E _R ′) is generated. A defect that E _L ′ = E _R ′ = 0 occurs. [0012] An object of the present invention is to provide the above-mentioned prior application,
Another object of the present invention is to propose a control method for eliminating the above-mentioned problem at the time of reproducing the stereo signal when the S / N of the sub signal is good due to a strong electric field or the like. To achieve the above object, an FM stereo receiver according to the present invention divides a main signal in an FM demodulated output signal into main signal components of a plurality of frequency domain channels. First frequency dividing means for performing
Second frequency dividing means for dividing a detection output signal obtained by synchronously detecting the demodulated output signal with the subcarrier signal into sub signal components of a plurality of frequency domain channels, and a first level for detecting a level of each main signal component a detection means, and second level detecting means for detecting the level of each sub-signal components, and respective detection signals of the detection signal and the second level detecting means of said first level detecting means to the signal meter output signal a first adding means for adding in accordance with the addition coefficient corresponding,
Comparison means for comparing each addition output signal of the first addition means with a reference signal; gain control means for controlling the gain of each sub-signal component according to each comparison output signal of the comparison means;
Second adding means for adding each output signal of the gain control means, third adding means for adding each main signal component,
The gist of the invention is to provide a matrix means for obtaining a stereo signal from the combined main signal from the third adding means and the combined sub-signal from the second adding means. In the FM stereo receiver of the present invention, the level detection signal of each main signal component and the level detection signal of each sub-signal component are converted into an addition coefficient corresponding to the FM demodulation output signal.
Therefore adding, comparing the respective addition output signal and the reference signal. Then, the gain of each sub-signal component is controlled in accordance with each of the comparison output signals and then synthesized, and the synthesized sub-signal is sent to the matrix means together with the synthesized main signal. An embodiment of the present invention will be described below. FIG. 1 shows an embodiment of an FM stereo receiver according to the present invention. The same reference numerals as those in FIG. 5 denote the same or similar circuits.
The difference from FIG. 5 is that a signal meter voltage indicating the electric field strength is input from the amplification and FM demodulator 1 to the signal processing circuit 31 and the configuration thereof is different from that of FIG. FIG. 2 shows an example of the configuration of the signal processing circuit 31, in which n
It comprises channel signal processing units 31-1 to 31-n.
2, the same reference numerals as those in FIG. 6 denote the same or similar circuits, and the configuration different from FIG. 6 is that the amplitude detection circuits 41-1 to 41-n of each sub-signal component and the amplitude detection signals of Voltage control addition circuit 4 for adding the amplitude detection signal of each sub signal component according to the signal meter voltage
2-1 to 42-n are provided. In the above embodiment, first, the amplitudes of the n main signal components from the first BPF group 5 for the main signal are detected by the amplitude detection circuits 21-1 to 21-n. The signal is applied to one input terminal of each of the voltage control addition circuits 42-1 to 42-n. Each amplitude of the n sub-signal components from the second BPF group 6 for sub-signals is detected by an amplitude detection circuit 4
1-1 to 41-n, and the respective amplitude detection signals are applied to the other input terminals of the voltage control addition circuits 42-1 to 42-n. In each of the voltage control addition circuits 42-1 to 42-n, in accordance with the signal meter voltage, each output (DC voltage) of the main signal amplitude detection circuits 21-1 to 21-n and the sub signal amplitude detection. After adding each output (DC voltage) of the circuits 41-1 to 41-n, the added output (DC voltage) is applied to each of the comparison circuits 22-1 to 22-n. Comparison circuit 22
-1 to 22-n, reference voltage generating circuits 23-1 to 23-
n, the gain control circuits 24-1 to 24-n, and the operation of the combining circuit 10 are the same as those in FIG. Next, voltage control addition circuits 42-1 to 42-n
Will be described with reference to FIG. FIG. 3A shows the input / output relationship of the voltage control addition circuits 42-1 to 42-n. In this circuit, if the two added input signals are V ₁ and V ₂ and the added output signal is V ₃ , the following is obtained. V ₃ = kV ₁ + (1−k) V ₂ k: Addition coefficient 0 ≦ k ≦ 1 (1) The addition coefficient k changes according to the control input signal Vc. FIG. 3B shows the relationship between the addition coefficient k and the control input signal Vc.
When Vc = 0, V ₃ = V ₁ , and when Vc = Vx, V ₃ = V ₂ . V ₃ is 0 <Vc <Vc in the range of Vx
The value of equation (1) is obtained by k corresponding to [0020] Thus, the output of the main signal amplitude detection circuit 21 - 1 to 21-n in FIG. 2 as V _1, sub signal amplitude detection circuit as V ₂ 41-1 to 41-n output, signal meter as Vc By taking the voltage, the voltage controlled addition circuit according to the present invention can be obtained. That is, when the electric field strength is low (the signal meter voltage is low), the voltage control addition circuits 42-1 to 42-1 are used.
The output of 42-n is the main signal amplitude detection circuit 21.
The output signals of −1 to 21-n become dominant, and when the electric field strength is high (the signal meter voltage is high), the amplitude of the sub-signal amplitude detection circuit 41-1 is output from the voltage control addition circuits 42-1 to 42-n. The output signals of .about.41-n are dominant. FIG. 4 shows an example of the relationship between the signal meter voltage and the electric field strength, the output S / N of the receiver (at the time of stereo demodulation without using the SN ratio improvement technique), and the electric field strength. FIG.
(A) and the relationship shown in FIG.
It is possible by setting in the amplification and FM demodulator 1. Therefore, if the voltage at which the signal meter voltage saturates in the strong electric field region is Vx, the relationship shown in FIG. 3 can be satisfied. Further, in this embodiment, for the sake of simplicity of explanation, each frequency channel of the sub-signal is controlled in a switching manner by a signal processing circuit 31 centered on the sub-signal gain control circuits 24-1 to 24-n. Although it is added to the synthesizing circuit 10, it may be controlled in an analog manner. As described above, the sub signal S /
When there is no deterioration of N, there is a possibility that normal stereo reproduction cannot be performed by the method of the prior application. it is possible to allow the normal stereo reproduction when the sub-signal S / N when an electric field is not degraded.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing one embodiment of the present invention. FIG. 2 is a block diagram illustrating a configuration example of a signal processing circuit in the embodiment. 3 is an operation explanatory diagram of a voltage control addition circuit of the signal processing circuit of FIG. 2; FIG. 4 is an explanatory diagram showing the relationship between the electric field strength, the signal meter voltage, and the S / N of the output of the receiver. FIG. 5 is a block diagram showing a method of the prior application. FIG. 6 is a block diagram showing a configuration of a signal processing circuit in the method of the prior application. [Description of Signs] 1 IF amplification and FM demodulator 2 BPF (19 kHz) 3 Subcarrier signal generator 4 Synchronous detection circuits 5, 6 BPF group 7, 10 Synthesis circuit 9 Matrix circuit 31 Signal processing circuits 21-1 to 21- n, 41-1 to 41-n Amplitude detection circuits 42-1 to 42-n Voltage control addition circuits 22-1 to 22-n Comparison circuits 23-1 to 23-n Reference voltage generation circuits 24-1 to 24-n Gain control circuit

Claims (1)

(57) [Claim 1] First frequency dividing means for dividing a main signal in an FM demodulated output signal into main signal components of a plurality of frequency domain channels, and Second frequency division means for dividing a detection output signal synchronously detected by the subcarrier signal into sub signal components of a plurality of frequency domain channels; first level detection means for detecting the level of each main signal component; A second level detecting means for detecting the level of each sub-signal component; and an addition coefficient corresponding to each signal detected by the first level detecting means and each detected signal of the second level detecting means according to a signal meter output signal. first adding means, said first comparison means for comparing the respective addition output signal and the reference signal adding means, each sub-signal according to the comparison output signal of said comparing means for adding in accordance with Gain control means for controlling the gain of each minute; second addition means for adding each output signal of the gain control means; third addition means for adding each main signal component; and third addition means. And a matrix means for obtaining a stereo signal from the combined main signal and the combined sub-signal from the second adding means.