JP3412800B2 - Semiconductor device having voltage generating circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention generally relates to semiconductor devices, and more particularly to a booster circuit and a substrate voltage generating circuit used inside the semiconductor device.

[0002]

2. Description of the Related Art Generally, in a semiconductor device, it is necessary to generate a voltage different from a power supply voltage VDD and a ground voltage VSS supplied from the outside inside the semiconductor device. For example, in a semiconductor memory device such as a DRAM, when a potential VDD (HIGH) is stored in a capacitor that constitutes a memory cell, a cell transistor connected to the memory cell is turned on, and the memory cell is connected to the bit line through the cell transistor. Supply charge to the cell. At this time, in order to charge the memory cell at high speed, (VD
It is necessary to apply a potential of (D + Vth + α). Where V
th is the threshold voltage of the cell transistor, which is the voltage V
In order to charge the memory cell with DD, it is necessary to apply a potential higher than the voltage VDD by the threshold voltage to the gate. Further, α is a voltage for an overdrive for charging the memory cell at a high speed, and by supplying the gate with a potential higher by this overdrive, the high speed charging can be performed.

In order to internally generate a voltage higher than the power supply voltage supplied from the outside, a booster circuit is provided inside the semiconductor device. FIG. 7 shows an example of a conventional booster circuit. The booster circuit 200 of FIG. 7 includes NMOS transistors 201 and 202, an inverter 203, a capacitor 204, a booster sensor 205, and an oscillator 206. Note that the capacitor 204 generally has a node connecting a source and a drain of a transistor as one end, a gate of the transistor as the other end, and a capacitance between the gate and the source / drain by using the gap.

A boosted voltage VDH is generated at the output terminal OUT of the booster circuit 200. When the current from the output terminal OUT is consumed inside the semiconductor device, the boosted voltage VD
H descends. The boost sensor 205 monitors the boost voltage VDH, and drives the oscillator 206 when the boost voltage VDH becomes lower than a predetermined threshold voltage. By driving the oscillator 206, the boosted voltage VDH which is the output of the booster circuit 200 is pushed up to a predetermined threshold voltage or higher.

Specifically, first, when the output of the oscillator 206 is HIGH, the output of the inverter 203 is LO.
W. NMOS that operates as a diode at this time
A current flows through the transistor 201, and the potential of the node A is
The potential (VDD-Vth) is lower than the power supply voltage VDD by the threshold voltage Vth of the NMOS transistor 201. Next, when the output of the oscillator 206 becomes LOW, the output of the inverter 203 becomes HIGH (potential VDD). Since the output of the inverter 203 is capacitively coupled to the node A, the potential of the node A becomes (2VDD-Vth). At this time, the boosted voltage VDH is lower than the potential of the node A, and the NMOS transistor 202 is turned on. Therefore, the charge of the node A is supplied to the output terminal OUT, and the boosted voltage VDH rises.

By the oscillator 206 repeatedly switching between HIGH and LOW, the above operation is repeated a plurality of times, and the boosted voltage VDH is pushed up to a predetermined threshold voltage or higher. When the boosted voltage VDH becomes equal to or higher than a predetermined threshold voltage, the operation of the oscillator 206 controlled by the boost sensor 205 stops.

[0007]

The booster circuit 200 is arranged at one place in the semiconductor chip and supplies the boosted voltage to the internal circuit in the semiconductor device from there. FIG. 8 is a diagram showing the arrangement of the booster circuits in the semiconductor device. In FIG. 8, the booster circuit 200 is arranged at one place in the semiconductor chip 210, and the power supply voltage VDD is supplied from the VDD pad 212 via the VDD wiring 211.

When the scale of the semiconductor device 210 is small, the current supplied from the booster circuit 200 to the internal circuit is small, so that there is no particular problem with the configuration shown in FIG. However, as the scale of the semiconductor device 210 increases, the booster circuit 20
The current supplied from 0 to the internal circuit becomes large, and a voltage drop occurs in the VDD wiring 211 near the booster circuit 200. If the power supply voltage VDD is lowered in the vicinity of the booster circuit 200 in this way, it adversely affects the operation of other circuits using the power supply voltage VDD, which is not preferable. The power supply voltage VDD
As a result, the operating efficiency of the booster circuit 200 itself also decreases.

Further, in the configuration shown in FIG. 8, the booster circuit 20
Since 0 occupies a large chip area at a specific place in the semiconductor chip 210, there is a problem that the layout of other circuits is limited. Generally, the capacitor 204 of the booster circuit 200 is a large element having an area of several thousand square μm, and occupies a considerable percentage of the total chip area. Therefore, if the booster circuit 200 and other circuits are to be accommodated within the limited chip area, the degree of freedom in layout of the other circuits is naturally reduced.

The same problem also exists in the substrate voltage generating circuit that generates a potential lower than the ground potential with the same structure as the booster circuit. Therefore, an object of the present invention is to provide a semiconductor device in which the peripheral power supply voltage is prevented from being lowered by the booster circuit or the substrate voltage generating circuit. A further object of the present invention is to provide a semiconductor device that avoids the layout of other circuits in the chip being restricted by the booster circuit or the substrate voltage generating circuit.

[0011]

According to a first aspect of the present invention, a semiconductor device has a plurality of capacitors, a plurality of drivers for driving the plurality of capacitors, and a plurality of the capacitors through the plurality of capacitors. A booster circuit for generating a voltage higher than a power supply voltage including a rectifying circuit capacitively coupled to the driver is included, and the plurality of capacitors and the plurality of drivers are dispersedly arranged in the chip.

In the above invention, the capacitance of the booster circuit and the driver are divided into a plurality of parts, which are arranged in a distributed manner in the chip. Therefore, the supply of the power supply voltage to each circuit portion is dispersed, and it is possible to prevent the power supply voltage from dropping. Further, compared to the case where the entire circuit is arranged at one place, the area of each dispersed circuit portion is small, so that a margin can be given to the layout of other circuits.

According to a second aspect of the present invention, in the semiconductor device according to the first aspect, the rectification circuit is capacitively coupled to the plurality of drivers through the plurality of capacitors in a one-to-one correspondence. And a plurality of the rectifying circuits are dispersedly arranged in the chip. In the above invention, in addition to the capacitor and the driver, the rectifying circuit is also divided into a plurality of parts, which are distributed and arranged in the chip. Therefore, the supply of the power supply voltage to the rectifying circuit is also dispersed, so that the effect of preventing the power supply voltage from dropping can be further enhanced.

According to a third aspect of the present invention, in the semiconductor device according to the first aspect, the power source wiring for supplying the power source voltage is further included, and the plurality of drivers are separated from each other by a predetermined distance or more. It is characterized in that it is connected to the power supply wiring. In the above invention, since the driving driver is connected to the power supply wiring at a predetermined distance or more, the power supply voltage drop can be sufficiently suppressed.

According to a fourth aspect of the present invention, in the semiconductor device according to the second aspect, the power source wiring for supplying the power source voltage is further included, and the plurality of drivers are separated from each other by a predetermined distance or more. The plurality of rectifying circuits are connected to the power supply wiring and are connected to the power supply wiring at a predetermined distance or more. In the above invention, since the driving driver and the rectifying circuit are connected to the power supply wiring at a predetermined distance or more, the power supply voltage drop can be sufficiently suppressed.

According to the invention of claim 5, the semiconductor device is
It is characterized in that it includes a booster circuit including a plurality of capacitors for generating a voltage higher than the power supply voltage, and the plurality of capacitors are dispersedly arranged in the chip. In the above invention, since the boosting capacitors of the booster circuit are dispersedly arranged in the chip, compared with the case where the entire booster circuit is arranged in one place,
It is possible to give a margin to the layout of other circuits.

According to the invention of claim 6, the semiconductor device is
A booster circuit including a plurality of drivers for driving a capacitance for generating a voltage higher than a power supply voltage is included, and the plurality of drivers are dispersedly arranged in a chip.
In the above invention, the drivers for driving the boosting capacitors of the booster circuit are arranged in a distributed manner, so that the supply of the power supply voltage to the booster circuit is dispersed and the drop of the power supply voltage can be prevented.

According to the invention of claim 7, the semiconductor device is
Substrate voltage generation including a plurality of capacitors, a plurality of drivers that drive the plurality of capacitors, and a rectifying circuit that is capacitively coupled to the plurality of drivers through the plurality of capacitors and that generates a substrate voltage lower than a ground voltage A plurality of capacitors and a plurality of drivers are distributed and arranged in a chip including a circuit.

In the above invention, the capacitance of the substrate voltage generating circuit and the driver are divided into a plurality of parts, which are arranged in a distributed manner in the chip. Therefore, the supply of the power supply voltage to each circuit portion is dispersed, and it is possible to prevent the power supply voltage from dropping.
Further, compared to the case where the entire circuit is arranged at one place, the area of each dispersed circuit portion is small, so that a margin can be given to the layout of other circuits.

According to an eighth aspect of the present invention, in the semiconductor device according to the seventh aspect, a plurality of the rectifying circuits are capacitively coupled to the plurality of drivers through the plurality of capacitors in a one-to-one relationship. And a plurality of the rectifying circuits are dispersedly arranged in the chip. In the above invention, in addition to the capacitor and the driver, the rectifying circuit is also divided into a plurality of parts, which are distributed and arranged in the chip. Therefore, the supply of the power supply voltage to the rectifying circuit is also dispersed, so that the effect of preventing the power supply voltage from dropping can be further enhanced.

According to a ninth aspect of the present invention, in the semiconductor device according to the seventh aspect, the semiconductor device further includes power supply wiring for supplying a power supply voltage, and the plurality of drivers are separated from each other by a predetermined distance or more. It is characterized in that it is connected to the power supply wiring. In the above invention, since the driving driver is connected to the power supply wiring at a predetermined distance or more, the power supply voltage drop can be sufficiently suppressed.

According to a tenth aspect of the present invention, the semiconductor device according to the eighth aspect further includes a power supply wiring for supplying a power supply voltage, wherein the plurality of drivers are separated from each other by a predetermined distance or more. It is characterized in that it is connected to a power supply line, and the plurality of rectifying circuits are connected to the power supply line at a predetermined distance or more. In the above invention, since the driving driver and the rectifying circuit are connected to the power supply wiring at a predetermined distance or more, the power supply voltage drop can be sufficiently suppressed.

According to another aspect of the invention, the semiconductor device includes a substrate voltage generating circuit including a plurality of capacitors for generating a substrate voltage lower than the ground voltage, and the plurality of capacitors are dispersed in the chip. It is characterized by being arranged. In the above invention, since the capacitance of the substrate voltage generating circuit is distributed and arranged in the chip, there is more room in the layout of other circuits than when the entire substrate voltage generating circuit is arranged in one place. You can have it.

According to a twelfth aspect of the present invention, the semiconductor device includes a substrate voltage generating circuit including a plurality of drivers for driving a capacitance for generating a substrate voltage lower than the ground voltage, and the plurality of drivers include a chip. It is characterized in that they are distributed in the interior. In the above invention, the drivers for driving the capacitance of the substrate voltage generating circuit are arranged in a dispersed manner, so that the supply of the power supply voltage to the substrate voltage generating circuit is dispersed and the drop of the power supply voltage can be prevented.

[0025]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the accompanying drawings. FIG. 1 shows a first embodiment of a booster circuit according to the present invention. The booster circuit 10 of FIG.
S transistors 11 and 12, inverters 13 to 1
5, the capacitors 16 to 18, the boost sensor 19, and the oscillator 20. The inverters 13 to 15 are drivers that drive the capacitors 16 to 18 that are boosting capacitors, and the NMOS transistors 11 and 12 form a rectifying circuit for generating a boosted voltage.

The operation of the booster circuit 10 is the same as that of the booster circuit 2 of FIG.
The same as 00. That is, the output terminal OU of the booster circuit 10
The boosted voltage VDH is generated at T. When the current from the output terminal OUT is consumed inside the semiconductor device, the boosted voltage VDH drops. The boost sensor 19 monitors the boost voltage VDH, and drives the oscillator 20 when the boost voltage VDH becomes lower than a predetermined threshold voltage. By driving this oscillator 20, the booster circuit 10
The boosted voltage VDH, which is the output of, is pushed up to a predetermined threshold voltage or higher.

Specifically, first, when the output of the oscillator 20 is HIGH, the outputs of the inverters 13 to 15 are LOW. NM that operates as a diode at this time
A current flows through the OS transistor 11, and the potential of the node A becomes lower than the power supply voltage VDD by the threshold voltage Vth of the NMOS transistor 11 (VDD−Vth). Next, when the output of the oscillator 20 becomes LOW, the outputs of the inverters 13 to 15 become HIGH (potential VDD). Since the outputs of the inverters 13 to 15 are capacitively coupled to the node A, the potential of the node A is (2VDD-V
th). At this time, the boosted voltage VDH is lower than the potential of the node A, and the NMOS transistor 12 is turned on. Therefore, the charge of the node A is supplied to the output terminal OUT, and the boosted voltage VDH rises.

By the oscillator 20 repeatedly switching between HIGH and LOW, the above operation is repeated a plurality of times, and the boosted voltage VDH is pushed up to a predetermined threshold voltage or higher. When the boosted voltage VDH becomes equal to or higher than a predetermined threshold voltage, the operation of the oscillator 20 controlled by the boost sensor 19 is stopped. In the booster circuit 10 of FIG. 1, a plurality of (three in the figure as an example) boosting capacitors 16 to 18 are provided, and the same number of boosting capacitor driving inverters 13 to 15 are provided. To achieve the same boosting capability as the booster circuit 200 of FIG.
The area of each of the capacitors 16 to 18 is 1 of the area of the capacitor 204.
It may be about / 3, and the boosting capacity driving capability of each of the inverters 13 to 15 may be about 1/3 of that of the inverter 203. If the inverters 13 to 15 are distributed and arranged in the chip, the current consumed by each of the inverters 13 to 15 is also distributed in the chip, and the reduction of the peripheral power supply voltage due to the booster circuit 10 can be suppressed. . Since the capacitors 16 to 18 are arranged in a dispersed manner, the booster circuit 10
Does not occupy a large area at a specific position in the chip, and can provide a layout with a margin for other circuits.

FIG. 2 is a diagram showing an example of the arrangement of the booster circuit 10 in the semiconductor device. In FIG. 2, the booster circuit 10
However, the power supply voltage VDD is supplied from the VDD pad 32 via the VDD wiring 31 at three locations in the semiconductor chip 30. In FIG. 2, the booster circuit 10 is shown as three circuits. This is because the booster circuit 10 includes the inverters 13 to 15 and the capacitors 16 to 18 which are the circuit portions having the largest current consumption and chip occupying area. It is shown that they are distributed and arranged in different places. Other NMOS
The transistors 11 and 12, the boost sensor 19, and the oscillator 20 are circuit portions that are relatively small in terms of area and current consumption, and are not shown.

As shown in FIG. 2, the booster circuits 10 are arranged in a distributed manner as a plurality of (three in the figure as an example) circuit portions, and each portion receives the power supply voltage VDD from the VDD wiring 31. Therefore, the power supply voltage VD for the booster circuit 10
The supply of D is distributed in the semiconductor chip 30, and the power supply voltage V
The decrease in DD can be suppressed. At this time, the plurality of circuit parts of the booster circuit 10 are separated by VDD or more by a predetermined distance or more.
If it is connected to the wiring 31, the decrease in the power supply voltage VDD can be made so small that it can be ignored.

FIG. 3 is a diagram showing another example of the arrangement of the booster circuit 10 in the semiconductor device. FIG. 3A shows an example in which the conventional booster circuit 200 is arranged in the semiconductor memory device, and FIG. 3B shows an example in which the booster circuit 10 of the present invention is arranged in the semiconductor memory device. 3A and 3B
In the above, the semiconductor memory device 35 includes a plurality of memory cell matrices 36 and a peripheral circuit 37. As shown in FIG. 3A, since the conventional booster circuit 200 is arranged at one place in the semiconductor memory device 35, an unused area 38 indicated by a dotted line is generated. As shown in FIG. 3B, in the booster circuit 10 of the present invention, the booster capacitor is divided into a plurality of capacitors 16 to 18 (see FIG. 1) and the semiconductor memory device 3 is divided.
Since they are arranged in a distributed manner within 5, it is possible to reduce the area of each distributed circuit portion. Therefore, FIG.
As can be seen from the comparison between (A) and FIG. 3 (B), the unused area 38 can be eliminated and the layout of the peripheral circuit 37 can have a margin.

FIG. 4 shows a second embodiment of the booster circuit according to the present invention. 4, the same elements as those of FIG. 1 are referred to by the same numerals, and a description thereof will be omitted. In the booster circuit of the second embodiment shown in FIG. 4, the same number of rectifying circuits as boosting capacitors are provided. The booster circuit 10A of FIG.
Transistors 11-1 to 11-3, NMOS transistors 12-1 to 12-3, inverters 13 to 15,
And capacitors 16 to 18, a boost sensor 19, and an oscillator 20. In the booster circuit 10A of FIG. 4, the NMOS transistors 11 and 12 of the booster circuit 10 of FIG. 1 are three NMOS transistors 11-1 to 11-3 and 12-1.
To 12-3, except for the booster circuit 10
It has the same configuration as.

In the booster circuit 10A, the inverter 13
And the capacitor 16 is the NMOS transistors 11-1 and 12
-1 is driven, and the inverter 14 and the capacitor 17 are NMOS
The transistors 11-2 and 12-2 are driven. Furthermore,
The inverter 15 and the capacitor 18 are NMOS transistors 1
Drive 1-3 and 12-3. In this configuration, since the NMOS transistors 11 and 12 in FIG. 1 are divided into a plurality of parts, the current supply from the power supply voltage VDD can be further dispersed than in the case of FIG. Therefore, in terms of preventing the voltage drop of the power supply voltage VDD and improving the efficiency of the booster circuit, the circuit configuration of FIG. 4 is more desirable than the circuit configuration of FIG.

The booster circuit 10A has a boosted voltage V supplied from each of the NMOS transistors 12-1 to 12-3.
To ensure that DH is at the same potential, NMO
The sources of the S transistors 12-1 to 12-3 need to be shared by the signal line L. However, the boosted voltage VDH can be supplied to another circuit from an arbitrary point on the signal line L. Therefore, it is not necessary to route a long signal line in the chip to supply the boosted voltage VDH.

However, the booster circuit 10A of FIG. 4 is provided with a plurality of NMOS transistors 11 and 12,
The chip occupying area is larger than that of the booster circuit 10 of FIG. Therefore, the booster circuit 10A of FIG. 4 is preferably used when the chip area has a margin. FIG. 5 shows a first embodiment of the substrate voltage generating circuit according to the present invention. 5, the same elements as those of FIG. 1 are referred to by the same numerals,
The description is omitted. The substrate voltage generation circuit uses a substrate voltage V that is a potential lower than the ground potential in order to keep the potential of the substrate lower than the ground potential in the semiconductor device.
Generate BB.

The substrate voltage generating circuit 40 of FIG.
Transistors 41 and 42, inverters 43 to 45,
And capacitors 46 to 48, a substrate voltage sensor 49, and an oscillator 50. The inverters 43 to 45 have a capacity of 4
The NMOS transistors 41 and 42 are drivers for driving 6 to 48, and form a rectifying circuit for generating the substrate voltage VBB.

Output terminal O of substrate voltage generating circuit 40 of FIG.
A substrate voltage VBB is generated at the UT. When the substrate potential VBB rises and becomes higher than a predetermined threshold voltage inside the semiconductor device, the substrate voltage sensor 49 monitoring the substrate voltage VBB drives the oscillator 50. By driving this oscillator 50, the substrate voltage generation circuit 40
Substrate voltage VBB, which is the output of, is lowered below a predetermined threshold voltage.

Specifically, first, when the output of the oscillator 50 is LOW, the outputs of the inverters 43 to 45 are H level.
It is IGH. NM that operates as a diode at this time
A current flows through the OS transistor 42, and the potential of the node A is higher than the ground voltage VSS by the NMOS transistor 42.
Higher than the threshold voltage Vth of (VSS + Vth)
Becomes Next, when the output of the oscillator 50 becomes HIGH, the outputs of the inverters 43 to 45 become LOW (potential VS).
S). The outputs of the inverters 43 to 45 are node A
Therefore, the potential of the node A is the potential VS.
The potential is lower than S. At this time, the substrate voltage VBB is higher than the potential of the node A, and the NMOS transistor 41 is turned on. Therefore, charges are supplied from the output terminal OUT to the node A, and the substrate voltage VBB drops.

By the oscillator 50 repeatedly switching between HIGH and LOW, the above operation is repeated a plurality of times, and the substrate voltage VBB is lowered to a predetermined threshold voltage or less. When the substrate voltage VBB becomes equal to or lower than the predetermined threshold voltage, the operation of the oscillator 50 controlled by the substrate voltage sensor 49 stops. In the substrate voltage generation circuit 40 shown in FIG.
Capacitors 46 to 48 are provided, and the same number of inverters 43 to 45 for driving the capacitors are provided. As in the case of the booster circuit, if the inverters 43 to 45 are distributed and arranged in the chip, the current consumed by each of the inverters 43 to 45 is also distributed in the chip, and the peripherals by the substrate voltage generation circuit 40 are distributed. It is possible to suppress a decrease in power supply voltage. At this time, if a plurality of circuit portions of the substrate voltage generation circuit 40 are connected to the VDD wiring at a predetermined distance or more, the decrease in the power supply voltage VDD can be made small enough to be ignored. In addition, since the capacitors 46 to 48 are dispersedly arranged,
The substrate voltage generation circuit 40 does not occupy a large area at a specific position in the chip, and it is possible to provide a layout with a margin for other circuits.

FIG. 6 shows a second embodiment of the substrate voltage generating circuit according to the present invention. 6, the same elements as those of FIG. 5 are referred to by the same numerals, and a description thereof will be omitted. Figure 6
In the substrate voltage generating circuit of the second embodiment, the same number of rectifying circuits as capacitors are provided. The substrate voltage generating circuit 40A shown in FIG. 6 includes NMOS transistors 41-1 to 41.
-3, NMOS transistors 42-1 to 42-3, inverters 43 to 45, capacitors 46 to 48, a substrate voltage generation sensor 49, and an oscillator 50. The substrate voltage generation circuit 40A shown in FIG. 6 corresponds to the substrate voltage generation circuit 4 shown in FIG.
0 NMOS transistors 41 and 42 are three NM
It has the same configuration as the substrate voltage generation circuit 40 except that it is divided into OS transistors 41-1 to 41-3 and 42-1 to 42-3.

In the substrate voltage generating circuit 40A, the inverter 43 and the capacitor 46 are the NMOS transistor 41-1.
And 42-1 are driven, and the inverter 44 and the capacitor 47 drive the NMOS transistors 41-2 and 42-2. Further, the inverter 45 and the capacitor 48 drive the NMOS transistors 41-3 and 42-3. In this configuration, since the NMOS transistors 41 and 42 in FIG. 5 are divided into a plurality of parts, the current supply from the power supply voltage VDD can be further dispersed than in the case of FIG. Therefore, in terms of preventing the voltage drop of the power supply voltage VDD and improving the efficiency of the substrate voltage generating circuit, the circuit configuration of FIG. 6 is more preferable than the circuit configuration of FIG.

However, the substrate voltage generating circuit 40A of FIG.
By providing a plurality of MOS transistors 41 and 42, the chip occupying area becomes larger than that of the substrate voltage generating circuit 40 of FIG. Therefore, the substrate voltage generation circuit 4 of FIG.
0A is preferably used when the chip area has a margin. Although the present invention has been described based on the embodiments, it is not limited to the above embodiments, and various modifications and changes can be made within the scope of the claims.

[0043]

According to the first aspect of the invention, the capacitance of the booster circuit and the driver are divided into a plurality of parts, which are arranged in a distributed manner in the chip. Therefore, the supply of the power supply voltage to each circuit portion is dispersed, and it is possible to prevent the power supply voltage from dropping.
Further, compared to the case where the entire circuit is arranged at one place, the area of each dispersed circuit portion is small, so that a margin can be given to the layout of other circuits.

According to the second aspect of the invention, in addition to the capacitor and the driver, the rectifying circuit is also divided into a plurality of pieces, which are arranged in a distributed manner in the chip. Therefore, the supply of the power supply voltage to the rectifying circuit is also dispersed, so that the effect of preventing the power supply voltage from dropping can be further enhanced. According to the third aspect of the invention, since the driving driver is connected to the power supply wiring at a predetermined distance or more, the power supply voltage drop can be sufficiently suppressed.

In the fourth aspect of the invention, the driving driver and the rectifying circuit are connected to the power supply wiring at a predetermined distance or more, so that the power supply voltage drop can be sufficiently suppressed. In the invention of claim 5, since the boosting capacitors of the boosting circuit are arranged in a distributed manner in the chip, the layout of other circuits is improved compared to the case where the entire boosting circuit is arranged in one place. You can have a margin.

According to the sixth aspect of the present invention, the drivers for driving the boosting capacitors of the booster circuit are arranged in a distributed manner, so that the supply of the power supply voltage to the booster circuit is distributed and the drop of the power supply voltage is prevented. Can be done. According to the invention of claim 7,
The capacitance of the substrate voltage generating circuit and the driver are divided into a plurality of parts, which are distributed and arranged in the chip. Therefore, the supply of the power supply voltage to each circuit portion is dispersed, and it is possible to prevent the power supply voltage from dropping. Further, compared to the case where the entire circuit is arranged at one place, the area of each dispersed circuit portion is small, so that a margin can be given to the layout of other circuits.

In the eighth aspect of the invention, in addition to the capacitor and the driver, the rectifying circuit is divided into a plurality of parts, which are arranged in a dispersed manner in the chip. Therefore, the supply of the power supply voltage to the rectifying circuit is also dispersed, so that the effect of preventing the power supply voltage from dropping can be further enhanced. In the invention of claim 9, the driving driver is connected to the power supply wiring at a predetermined distance or more, so that the power supply voltage drop can be sufficiently suppressed.

According to the tenth aspect of the invention, since the driving driver and the rectifying circuit are connected to the power source wiring at a predetermined distance or more, it is possible to sufficiently suppress the power source voltage drop. According to the invention of claim 11, since the capacitances of the substrate voltage generating circuit are distributed and arranged in the chip, the layout of other circuits is different from the case where the entire substrate voltage generating circuit is arranged in one place. Can be afforded.

According to the twelfth aspect of the present invention, since the drivers for driving the capacitance of the substrate voltage generating circuit are arranged in a distributed manner, the supply of the power source voltage to the substrate voltage generating circuit is dispersed and the power source voltage is reduced. Can be prevented.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a first embodiment of a booster circuit according to the present invention.

FIG. 2 is a diagram showing an example of arrangement of a booster circuit according to the present invention in a semiconductor device.

FIG. 3 is a diagram showing another example of arrangement of a booster circuit according to the present invention in a semiconductor device.

FIG. 4 is a circuit diagram of a second embodiment of the booster circuit according to the present invention.

FIG. 5 is a circuit diagram of a first embodiment of a substrate voltage generating circuit according to the present invention.

FIG. 6 is a circuit diagram of a second embodiment of the substrate voltage generating circuit according to the present invention.

FIG. 7 is a circuit diagram showing an example of a circuit configuration of a conventional booster circuit.

FIG. 8 is a diagram showing an arrangement of a conventional booster circuit in a semiconductor device.

[Explanation of symbols]

10, 10A booster circuit 19 Boost voltage sensor 20 oscillators 30 semiconductor devices 31 VDD wiring 32 VDD pad 35 Semiconductor Storage Device 36 memory cell matrix 37 Peripheral circuit 40, 40A Substrate voltage generation circuit 49 Substrate voltage sensor 50 oscillators 200 step-up circuit 205 Boost voltage sensor 206 oscillator

Front Page Continuation (72) Inventor Yasuro Matsuzaki 4-1-1 Kamitadanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture, Fujitsu Limited (56) Reference JP-A-6-283667 (JP, A) JP-A-8- 306870 (JP, A) JP 8-251912 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) H02M 3/07 G11C 11/407 G11C 11/413

Claims (12)

(57) [Claims] 1. A voltage higher than a power supply voltage including a plurality of capacitors, a plurality of drivers for driving the plurality of capacitors, and a rectifying circuit capacitively coupled to the plurality of drivers via the plurality of capacitors is generated. Including a booster circuit, the output side ends of the plurality of capacitors are directly connected to each other.
Are indirectly connected in parallel to a common node through the same circuit configuration.
A semiconductor device in which the plurality of capacitors and the plurality of drivers are connected to each other and are distributed and arranged in a chip. 2. The rectifying circuit is a plurality of rectifying circuits capacitively coupled to the plurality of drivers through the plurality of capacitors in a one-to-one correspondence, and the plurality of rectifying circuits are dispersed to form an on-chip chip. 2. The semiconductor device according to claim 1, wherein the semiconductor device is arranged in. 3. The semiconductor device according to claim 1, further comprising a power supply wiring for supplying the power supply voltage, wherein the plurality of drivers are connected to the power supply wiring at a predetermined distance or more from each other. . 4. The power supply wiring for supplying the power supply voltage is further included, the plurality of drivers are connected to the power supply wiring at a predetermined distance or more from each other, and the plurality of rectification circuits are at a predetermined distance or more from each other. The semiconductor device according to claim 2, wherein the semiconductor device is separated and connected to the power supply wiring. 5. A booster circuit including a plurality of capacitors for generating a voltage higher than a power supply voltage , the output side of the plurality of capacitors.
One end of is directly or indirectly through the same circuit configuration
Of the semiconductor device , wherein the plurality of capacitors are distributed and arranged in a chip. 6. comprising a booster circuit including a plurality of drivers for driving the capacity to produce a higher voltage than the power supply voltage, the
One end on the output side of multiple drivers is connected via the same circuit
And indirectly connected in parallel to a common node, and the plurality of drivers are dispersedly arranged in a chip. 7. A substrate voltage lower than a ground voltage including a plurality of capacitors, a plurality of drivers for driving the plurality of capacitors, and a rectifying circuit capacitively coupled to the plurality of drivers via the plurality of capacitors. An output side of the plurality of capacitors including a substrate voltage generating circuit for generating
One end of is directly or indirectly through the same circuit configuration
Of the semiconductor device , wherein the plurality of capacitors and the plurality of drivers are distributed and arranged in a chip. 8. The rectification circuit is a plurality of rectification circuits capacitively coupled to the plurality of drivers through the plurality of capacitors in a one-to-one relationship, and the plurality of rectification circuits are dispersed in a chip. 8. The semiconductor device according to claim 7, wherein the semiconductor device is arranged in. 9. The semiconductor device according to claim 7, further comprising a power supply wiring for supplying a power supply voltage, wherein the plurality of drivers are connected to the power supply wiring at a predetermined distance or more from each other. 10. A power supply line for supplying a power supply voltage, wherein the plurality of drivers are connected to the power supply line at a predetermined distance or more from each other, and the plurality of rectifying circuits are separated from each other by a predetermined distance or more. 9. The semiconductor device according to claim 8, wherein the semiconductor device is connected to the power supply wiring. 11. includes a substrate voltage generating circuit including a plurality of capacitors for generating a low substrate voltage than the ground voltage, the
One end of the output side of multiple capacitors directly or the same circuit configuration
A semiconductor device, which is indirectly connected in parallel to a common node via a plurality of capacitors and in which the plurality of capacitors are dispersed and arranged in a chip. 12. A substrate voltage generation circuit including a plurality of drivers for driving a capacitance for generating a substrate voltage lower than a ground voltage , wherein one end on an output side of the plurality of drivers is the same.
Indirectly connected in parallel to a common node via one circuit configuration
And the plurality of drivers are dispersedly arranged in the chip.