JP3405569B2 - Cell inversion device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is used for transmitting and receiving fixed bit rate data (CBR data) such as audio and video in an ATM communication device for converting input information into cells which are fixed length packets and communicating. The present invention relates to a cell inverse conversion device used on the receiving side.

[0002]

2. Description of the Related Art As is well known, in the ATM communication system in wideband ISDN, all data to be communicated is converted into a fixed length packet (referred to as a cell) of 53 bytes and exchanged / transmitted. Therefore, when attempting to communicate data that is not in the cell format, such as conventional data, call data when making a telephone call, and video data, it is necessary to convert these data into cells by some method. That is, in order to realize such communication, the transmitting side needs to convert non-cell format data into cells, and the receiving side needs to convert cell to the original data format. The former process is called cell conversion, and the latter process is called cell inverse conversion.

Here, FIG. 16 shows a schematic structure of an ATM network using a broadband ISDN, and FIG. 17 shows a format of a cell used for communication of this ATM network. The data format used in this type of conventional ATM network communication includes X. It was possible to roughly divide it into packet data such as 25 and fixed bit rate data such as audio and video. Now, assuming that fixed bit rate data is exchanged / transmitted by the above-mentioned ATM communication system, the following has been considered as a configuration of a cell inverse conversion device which performs cell inverse conversion on the receiving side.

That is, FIG. 18 is a block diagram showing an example of a cell inverse conversion device used in a conventional ATM device for converting a data string of a fixed bit rate into cells and communicating the cells. As shown in the figure, this conventional cell inverse conversion device includes a filter circuit (VFIL) 1, a fluctuation absorption buffer memory (RI).
BF) 2, inverse conversion circuit (RASM) 3, speed conversion dual port memory (ROBF) 4, STM processing circuit (S)
TM) 5, sequence control circuit (SEQ) 6, timer circuit (TIM) 7, memory management circuit (MEMC) 8a, and register circuit (REG) 10a.

The filter circuit (VFIL) 1 is a functional circuit that determines whether or not the input cell is addressed to itself.
The fluctuation absorption buffer memory (RIBF) 2 is a buffer memory that temporarily stores cells in order to absorb fluctuations in arrival delay of cells. Also, an inverse conversion circuit (RASM)
Reference numeral 3 is a circuit for performing order control of cells extracted from the RIBF 2, header error processing, and processing for extracting CBR data from the cell information section. The dual port memory (ROBF) 4 for speed conversion is a CBR after inverse conversion. It is a memory with a FIFO structure that stores data and performs speed conversion with the output side.

The STM processing circuit (STM) 5 is a ROBF.
The sequence control circuit (SEQ) 6 is a timing supply circuit for controlling the operation timing of each of the above circuits. The timer circuit (TIM) 7 is a timer for starting the operation of the inverse conversion circuit (RASM) 3 after the fluctuation absorption delay time has elapsed since the first cell arrival, and the memory management circuit (ME
MC) 8a is a circuit for detecting underflow and overflow of ROBF4 and RIBF2. The register circuit (REG) 10a is a register having an input / output port through which an external CPU or the like sets various parameters at the time of start-up and monitors the operating state of the cell inverse conversion device (self device).

Next, the operation of cell inverse conversion by this type of conventional device will be described by taking the case of voice communication as an example.
For example, when making a call between the telephone A and the telephone B shown in FIG. 16, first, the telephone A lifts the handset and dials the telephone number of the telephone B, which is the other party of the call. By this dial operation, dial information is transmitted to a call control processor (not shown) of the ATM exchange 300a, and the processor secures a virtual channel for connecting the telephones A and B to the ATM network 400, and the channel identifier Based on the VCI and the general delay fluctuation time of the ATM network 400 at that time, the optimum fluctuation absorption time T is notified to the CPU (not shown) of the voice cell assembling / decellizing apparatus connected to the telephones A and B.

The CPU of the voice cell conversion / decellization device converts these initial setting parameters into the cell conversion / inverse conversion device 20.
0a and 200b to start the operation of each device. This cell conversion / inverse conversion device 200a, 200
The activation of operation b is performed according to the sequence shown in FIG. That is, the channel identifier VCI and the fluctuation absorption delay time T are required control parameters for the VCI register, fluctuation absorption timer register, window size register, and start control register of the register circuit (equivalent to REG 10a in FIG. 18) in the device. , The window size W (the use of this parameter will be described later), and the start command are initialized.

As a result, the fixed bit rate data string transmitted from the telephone set A is sequentially divided into the length of the information portion of the cell (for example, 47 bytes), and the VC is added to the information portion.
It is converted into a cell string to which an adaptation header composed of I and a sequence number (SN) indicating the generation order of cells (used as a reproduction order on the receiving side) is added, and sequentially transmitted. On the other hand, the receiving side waits for the arrival of the cell to which the VCI is added, and performs the cell reverse conversion process for the cell addressed to itself.

The cell receiving operation on the receiving side will be described below with reference to the configuration of the cell inverse conversion device shown in FIG. First, the channel identifier VC is sent from an external CPU or the like.
I, the fluctuation absorption delay time T, the window size W, and other initialization parameters are set, and the cell inverse conversion device to which the start command is input receives the cell (valid cell) waiting for the same VCI as the set VCI. I'm waiting for you.

When the first cell (see FIG. 17) reaches the receiving section, it is input to the filter circuit (VFIL) 1 and the VCI contained in the header of the cell and the register circuit (R) of its own device.
EG) 10a is compared with the VCI set. When the cell is determined to be a valid cell by filtering the cell, the VCI portion of the header is removed from the cell, and the cell is stored in the address Rip (1) of the fluctuation absorption buffer (RIBF) 2. After that, the second cell is similarly processed and stored in the address Rip (2), and the third cell is also stored in the Rip (3) in the same manner. Will be done. By repeating this operation, cells are queued in the RIBF 2 in the order of reception. FIG. 20 shows a state where cells form a queue in RIBF2.

When the first valid cell is stored in RIBF2, the timer circuit (TIM) 7 is activated at the same time.
When the set fluctuation absorption delay time T elapses, the TIM 7 sends the RIBF 2 to the inverse conversion circuit (RASM) 3 in the next stage.
The data read from is permitted and the cell reverse conversion operation is started.

The cell inverse conversion operation of the inverse conversion circuit (RASM) 3 at this time is performed as follows. That is, RAS
M3 is controlled by a sequence control circuit (SEQ) 6 that operates at the cell cycle on the input side. RASM3 activated by SEQ6 takes out a cell from RIBF2 in every cell cycle, extracts CBR data from the information part of the cell, and uses dual port memory (ROB) for speed conversion.
F) The operation of outputting to 4 is repeated.

However, when a cell in the middle of the received cell string is lost (cell discard) or due to some error,
Since there may be a case where a cell having the same VCI but not addressed to itself is received (cell mixture), in order to detect cell discard and mixture by referring to the adaptation header,
The error recovery process is performed every time the cell is taken out. Because of this error recovery processing, the transmission side increments the sequence number SN of the adaptation header by one (range 0-7) every time a cell is sent out, so the SN of the cell extracted from RIBF2 on the reception side. Also,
Naturally, it should increase by 1 each time it is taken out. Therefore, cell discard / mixing can be detected by checking the SN continuity of the cells taken out from the RIBF 2.

The error recovery process is carried out by the calculation based on the "cell loss / misdelivery detection definition" shown in Table 1 using the window size W which is initialized. A flowchart of the processing operation at this time is shown in FIG. Here, TN is the expected value of the SN of the read cell that the inverse conversion circuit (RASM) 3 has, and the window size W is a parameter used to detect the discarding of a plurality of cells, that is, the jump of two or more SNs. is there. The TN is based on the SN of the cell that arrived first.

In the error recovery process based on the flowchart shown in FIG. 21, the SN of the input cell and the expected value TN
Whether the reception is normal (S21e) or abnormal is determined by whether or not (S21d, YES or NO), and when the reception is abnormal, compare the difference (TN-SN) with the initially set window size WS. At (S21i), it is determined whether an abnormality due to cell mixture (S21j) or an abnormality due to cell discard (S21m). Then, in the case of an abnormality due to cell discard, dummy data corresponding to the cell is output to the ROBF 4 for the discarded cell (S21n), and in the case of abnormality due to cell mixture, the mixed cell is output. Discard from RIBF2 (S21l). In addition, since the bit error of the adaptation header must be eliminated in order to correctly handle these processes,
SN represented by 3 bits in the adaptation header
Protects with 3 bits of CRC code (SNP) and 1 bit of parity (P), corrects 1-bit error, and
A process of detecting an error of more than one bit and discarding the corresponding cell is performed.

[0017] By the way, since the above-mentioned cell inverse conversion processing is driven by the sequence control circuit (SEQ) 6 which operates in the cell cycle, flow control is performed between the ROBF 4 and the RIBF 2. Next, the reason why the flow control is necessary and the outline of the control will be described. Now, taking voice communication at a line speed of 150 Mbps as an example, cells are generated and transmitted in a cycle of about 6 ns. Therefore, if there is no fluctuation in cell arrival, RIBF2 is set between cell arrivals. Therefore, the cell can be taken out about 2000 times. Therefore, even if the fluctuation absorption delay time T is set to 16 ms, R is still set by the time the timer expires and the inverse conversion circuit (RASM) 3 is activated.
Since only 3 cells are stored in the IBF2 at most, the RASM3 processes the data of the RIBF2 almost at the same time as the start-up, and all the extracted data are ROBF4.
Will be output to. Moreover, since the data reading from the ROBF4 is performed at the speed of the STM processing circuit (STM) 5 side (in this example, the data output from the ROBF4 is 47 bytes in 6 ms).
Is placed in a state in which overflow easily occurs.

Here, the control for avoiding the overflow is required. In the flow control here, the empty area of the ROBF4 is measured in the cell cycle and the RIBF is measured.
The inverse conversion process is performed only when there is a free area in which the data extracted by extracting the cell from 2 can be stored in the ROBF 4. Furthermore, considering the RIBF2, since the cell extraction from the RIBF2 is the cell cycle as described above, the cell extraction speed is faster than the cell input, so that an underflow state can usually occur. The RIBF2 has a structure in which the cell cannot be read in the underflow state, but the next cell arrives before the ROBF4 has a free space.
OBF4 usually does not underflow and ST
The data reproduced on the M5 side is not interrupted.

However, in the former case, when the line quality is poor or a switch or the like causes more cell discards than the value set in the window size W, or when the fluctuation delay is larger than the set value. Is determined to be a cell mixture, and SN
Since the cells are discarded from the RIBF2 until one cycle has occurred, the RIBF2 underflow occurs, and in the latter case, the RIBF2 underflow is not recovered even in the situation where data must be output to the ROBF4. Also, when many uncorrectable errors occur in the header, RIBF2 underflow similarly occurs.

The underflow that occurs in such a case causes the underflow of ROBF4, and the condition for fluctuation absorption initially set cannot be satisfied, resulting in STM.
The data reproduced on the side will be damaged.

As a countermeasure against this reproduction data failure, conventionally, failures such as underflow and overflow of RIBF2 and ROBF4, cell mixing, cell discard and header error described above are notified to the register circuit (REG) 10a by each error status. Utilizing the fact that the status information is periodically monitored by an externally provided CPU or the like, and when an abnormality occurs, the CPU or the like resets the reverse conversion circuit (RASM) 3 and executes the startup sequence. The function configuration was such that it can be restored by restarting it.

The regular monitoring and reset control have been carried out according to the flow chart shown in FIG. 22, for example. The condition for starting the reset (S22f) in this example is RO
When an underflow occurs in BF4 (S22e, YE
S). In addition, in order to obtain the information of the previous reset after the restart, the error information and the like obtained by the regular monitoring is held in the register of the external CPU or the like (S22).
The firmware is programmed as in d). However, in order to detect the RIBF2 underflow, (S
22b, S22c), regular monitoring timing (S22a)
Had to be set to an interval equal to the fluctuation absorption delay time.

As described above, in the conventional device, it is necessary to periodically monitor the operation by the external control device such as the CPU in order to cope with the recovery of the cell reproduction failure on the cell reproduction side caused by the failure of the line quality or the exchange. . This regular monitoring interval may change depending on the media or call being communicated,
The firmware on the external control device side requires complicated processing, and the shorter the regular monitoring interval, the greater the load on the firmware.

[0024]

As described above, in the above-mentioned conventional cell inverse conversion device, the cells on the STM side caused by cell discard or increase in delay fluctuation caused by line quality or failure of the exchange, header error, etc. In order to recover the reproduction failure, it is necessary to regularly monitor the error status from an external control device such as a CPU, and firmware for that purpose is indispensable. Moreover, since the regular monitoring interval may change depending on the medium or call being communicated, the firmware requires complicated processing, and particularly when the regular monitoring interval is short, the load on the firmware increases significantly. There was a problem.

It is an object of the present invention to eliminate this problem and to provide a cell reverse conversion device capable of easily recovering from a failure without requiring complicated firmware processing associated with regular monitoring from an external control device. .

[0026]

The present invention is used as a receiving side module of an ATM communication device for converting information into cells which are fixed length packets and performing communication, and restores input cells to original fixed bit rate data. In a cell inverse conversion device used for fixed bit rate communication, a filter circuit that extracts a cell addressed to itself from an input cell and a fluctuation that temporarily accumulates the extracted cell and absorbs the fluctuation of arrival of the cell. An absorption buffer memory, a cell inverse conversion circuit that takes in cell data from the fluctuation absorption buffer memory and extracts original fixed bit rate data, a timer circuit that manages the operation start timing of the cell inverse conversion circuit, and the cell inverse conversion circuit. It has a dual port memory that performs speed conversion between the conversion circuit and the output side, and an interface function with the external control device, and operates. A register circuit that stores operating conditions information indicating the operating conditions of the parameters and the device required for lifting, and holds the parameters and operating condition information as they are even when a reset command is given, and an overflow of the fluctuation absorption buffer memory and A memory management circuit that manages underflow of the dual port memory, monitors an error in the fluctuation absorption buffer memory and the dual port memory based on the management result, and gives the reset command to the register circuit when an error occurs. Automatically initializes the timer circuit, the fluctuation absorption buffer memory, and the dual port memory, and after the initialization is completed, restarts the operation based on the parameters and the operation state information held in the register circuit. Error monitoring that self-recovers the cell reverse conversion operation Characterized by comprising a circuit.

[0027]

According to the present invention, the overflow of the fluctuation absorption buffer memory and the underflow of the dual port memory for speed conversion are managed by the memory management circuit, and the result is notified to the error monitoring circuit. When an error occurs in each of the memories, the error monitoring circuit gives a reset command to the register circuit to automatically initialize the timer circuit, the fluctuation absorbing buffer memory and the dual port memory. The register circuit resets itself based on the reset command, but at that time, the VCI, the fluctuation absorption time T, which has been already stored,
Parameters such as the window size W required to start the operation and operation state information such as past error information are not retained as initialization targets and are retained. As a result, after the initialization is completed, the error monitoring circuit restarts the operation based on the parameters and the operation state information held in the register circuit to restore the cell reverse conversion operation by itself.

As described above, according to the present invention to which the self-resetting function is added when a memory error occurs, it is not necessary to perform this kind of reset control from an external CPU or the like, and inevitably the firmware for the control is required. Becomes unnecessary. Further, at the time of starting the self-reset, the information necessary for starting the operation is still held in the register circuit. Therefore, based on the held information, restarting after the above error is performed by the external C
It can be automatically performed without depending on the PU or the like, and restoration to the cell inverse conversion operation can be performed quickly. Further, since the register circuit also retains the error information that causes the reset, an external CPU or the like searches for this error information, and immediately after the reset of the cell inverse conversion device, the previous reset You can refer to the cause.

[0029]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described in detail below with reference to the accompanying drawings. FIG. 1 is a block diagram showing an embodiment of the present invention directed to a cell inverse conversion device used on the receiving side of a device for converting a data string of a constant bit rate into cells and communicating. In the cell inverse conversion device of the present invention, the circuits having the same functions as those of the conventional device are designated by the same reference numerals. As shown in FIG. 1, this cell inverse conversion device includes a filter circuit (VFIL) 1, a fluctuation absorption buffer memory (RIBF) 2, an inverse conversion circuit (RASM) 3, a speed conversion dual port memory (ROBF) 4, and an STM. Processing circuit (STM) 5, sequence control circuit (SEQ) 6, timer circuit (TIM) 7, memory management circuit (MEMC1)
8 and a memory management circuit (MEMC2) 9, a register circuit (REG) 10, and an error monitoring circuit (MONI) 11.

Here, the filter circuit (VFIL) 1 is a circuit section for discriminating whether or not the input cell is addressed to itself, and the fluctuation absorbing buffer memory (RIBF) 2 absorbs the arrival delay fluctuation of the cell. , A buffer memory that temporarily stores cells. Inverse conversion circuit (RASM) 3
Is a circuit for controlling the order of cells fetched from RIBF2 and header error processing, and processing for extracting CBR data from the information part of the cell. Dual port memory (ROBF) 4 for speed conversion is CBR data after reverse conversion. Is a FIFO structure memory that stores the data and performs speed conversion with the output side.

The STM processing circuit (STM) 5 is ROBF4.
The sequence control circuit (SEQ) 6 is a timing supply circuit for controlling the operation timing of each of the above circuits. The timer circuit (TIM) 7 is a timer for starting the operation of the inverse conversion circuit (RASM) 3 after the fluctuation absorption delay time has elapsed from the first cell arrival, and the memory management circuits 8 and 9 are provided.
(MEMC1,2) are RIBF2 and ROBF4 respectively
Is a circuit for detecting the underflow and the overflow.

The register circuit (REG) 10 is an external C
PU can set various parameters at startup,
A register having an input / output port for monitoring the operating state of the cell inverse conversion device, and an error monitoring circuit (M
ONI) 11 is RIBF2 overflow and ROB
This circuit detects an error such as underflow of F4 and issues a reset instruction to the reset register of the register circuit (REG) 10 when an error occurs.

The detailed structure of the essential parts of the cell inverse conversion device according to this embodiment is shown in FIGS. For example, FIG. 2 shows the configuration around the fluctuation absorption buffer memory (RIBF) 2 of the apparatus of this embodiment. 3 is a configuration diagram of the filter circuit (VFIL) 1, particularly FIG. 3A shows the overall configuration, and FIG. 3B shows the detailed configuration of the MWC 12 therein.

FIG. 4 shows the configuration of the timer circuit (TIM) 7. FIG. 5 is a block diagram of the inverse conversion circuit (RASM) 3, and in particular, FIG.
FIG. 2B shows the detailed configuration of the MRC 31 therein. Figure 6 shows a dual port memory for speed conversion (ROB
F) 4 shows the configuration around 4 and FIG. 7 shows a memory management circuit (ME
The configuration of MC1) is shown. Further, FIG. 8 shows a configuration of the register circuit (REG) 10, and FIG. 9 shows a detailed configuration of the error monitoring circuit (MONI) 11.

The general operation of the cell inverse conversion device of the present invention will be described below with reference to these drawings. First, an initialization parameter such as a channel identifier VCI, fluctuation absorption delay time T and window size W is set from an external CPU or the like, and the cell inverse conversion device to which a start command is input is the same VCI as the set VCI. Waiting until a cell with (valid cell) is input.

When the first cell reaches the receiving section, it is input to the filter circuit (VFIL) 1 and FIL 11 therein.
As shown in FIG. 3, the VCI included in the cell header is compared with the VCI set in its own register, and the cell length is checked. At this time, the received data is VFIL
It is output to the address WAD (1) generated by MWC12 of 1 and when this cell is valid (VALID is on) after the final data of the cell is written and the cell length is normal (ERR is OFF), the address pointer of the MWC 12 is incremented to WAD (2), and the data writing of one cell is completed. On the other hand, when the cell is not valid or abnormal, the address pointer is not incremented and the data of the next cell is overwritten.

Similar processing is performed on the second and subsequent cells, and the second cell is sequentially addressed to the address WAD (2), the third cell to the WAD (3), and so on, in sequence.
Will be stored in. By repeating this operation, RIB
Cells are queued in F2 in the order in which they are received, and the internal data structure of RIBF2 at this time is equivalent to that shown in FIG.

At the same time, each time a valid cell arrives at VFIL1, VFIL1 notifies TIM7 of the arrival of a cell by turning on VALID. The TIM7 is triggered by the first arrival of a valid cell after startup, and starts the fluctuation absorption timer 71 (see FIG. 4). Then, when the fluctuation absorption time elapses, the TFL turns on. TFL is RI for the inverse conversion circuit (RASM) 3
This is a control signal for permitting the removal of cells from BF2.

When TFL is turned on and RASM3 is activated, a sequence control circuit (SEQ) which operates in a cell cycle
The MRC 31 (see FIG. 5) is driven by 6 and cell extraction is started. Cell extraction is performed from the oldest cell stored in RIBF2. Therefore, at startup, the read address pointer of MRC31 is RAD.
It starts from (1). The cell recovered from the RIBF 2 is subjected to error recovery processing by the SNC 32 (see FIG. 5). Since the error recovery process is the same as the conventional process, its detailed description is omitted here.

The result of the error recovery processing is fielded back to the MRC 31 by the DIS signal, the read pointer of the MRC 31 is incremented at the time of normal reception, at the time of header error and at the time of cell mixing, and in the next cell cycle, from the next address [eg, RAD (2)] cell is read. When discarding cells, do not increment the pointer,
It is controlled to read the cell from the same address again in the next cell cycle. Also, when RIBF2 underflows (IUF is on) and when ROBF4 is full (FLW
No cell removal operation is performed when (ON).

When the error recovery process is completed, the cell is handed over to the RASM 33 (see FIG. 5). RASM3
3 removes the adaptation header for cells that have been normally received (reverse cell conversion), and adds 47 to the information section of the cell.
The byte CBR data is output to ROBF4, and when the cell is discarded, the 47-byte dummy data (all-mark data) is output to ROBF4. Then, STM
When the processing circuit (STM) 5 outputs the first one-cell data to the ROBF 4, the processing circuit (STM) 5 starts reading the data at the speed of the terminal. Through a series of these operations, the cell input from the ATM side is converted back to the original CBR data and output from the STM side.

Since the reverse conversion processing in the RASM3 described above is driven by the sequencer (SEQ) 6 that operates in the cell cycle, the cell extraction from the RIBF2 and the output of the reverse conversion data to the ROBF4 are performed by the STM.
5 is processed at a speed higher than the speed at which data is output from ROBF4. In this embodiment, the ROBF4 has a capacity of 12
Since it is 8 bytes, when CBR data for two cells (94 bytes) is being accumulated, the output of the data of the third cell causes an overflow. Therefore, when the free capacity of ROBF4 becomes 47 bytes or less, RIBF2 The cell is taken out from the cell (flow control is turned on).

The memory management circuit 9 [ME] detects the free space, underflow and overflow of the ROBF 4.
MC (2)]. As shown in FIG. 6, the write address (WAD) of ROBF4 is input to MEMC (2).
D) and the read address (RADD) are input, and by calculating these inputs by the arithmetic function circuit as shown in the figure, the flow control signal (FLW), the underflow signal (OUF), the overflow signal (OV).
F) is generated. Here, the OVF is sent to the register circuit (REG) 10 and the error monitoring circuit (MONI) 11,
Further, the OUF is output to the REG 10, and the FLW is output to the inverse conversion circuit (RASM) 3.

The cell receiving operation in the normal state of the cell inverse conversion apparatus according to the embodiment of the present invention has been described above. Next, the operation of self-resetting at the time of error will be described in detail. The cell reverse conversion device of the present invention is characterized by having a self-reset function that automatically resets when an error occurs and autonomously stands up without the control of an external CPU or the like. There are two types of error conditions for self-resetting: overflow of RIBF2 and underflow of ROBF4. The causes of these errors and the operation of the self-reset function will be described below.

First, the underflow of BOBF4 will be described. Underflow of ROBF4 is this R
If there is no CBR data to be output to OBF4,
That is, it is caused by the underflow of RIBF2. That is, as a cause of underflow of ROBF4,
If the arrival of the next cell does not arrive even after the fluctuation absorption delay time has elapsed, or the cell header has an error, a cell having an error or a cell discard exceeding the window size W occurs.
There are two cases in which the SNC 32 in 3 (see FIG. 5) determines that the cells are mixed and discards the header error cell or the cells determined to be mixed from the RIBF 2 as a result.

The error caused by the former is E1. When the setting of the fluctuation absorption time does not match the network condition (inappropriate).

E2. When the opposite side intentionally stops sending cells due to call interruption, etc.

E3. When cells are dropped in bursts due to network or equipment failure.

Etc. can occur in

The error caused by the latter is E4. Of the burst cell discard, when the scale is relatively small (tens of ms).

E5. If there are consecutive errors in the header.

Etc.

Next, focusing attention on RIBF2, the overflow is E6. When the speed of writing data to RIBF2 is much higher than the speed of outputting data on the STM side.

E7. When a cell that exceeds the capacity of RIBF2 arrives before the fluctuation absorption time elapses.

E8. When the cell cannot be taken out due to the failure of the circuit after RASM3.

Occurs in.

In the apparatus of this embodiment, the underflow of ROBF4 or RIBF is caused by the causes of E1 to E8.
When an overflow of 2 occurs, it becomes the target of self-reset. FIG. 10 shows an example of the error detection operation when the arrival of the next cell does not occur even after the fluctuation absorption delay time has elapsed, and FIG. 11 shows the error detection operation when the ROBF4 underflows due to the header error cell. Shows an example.

To activate the cell inverse converter, it is necessary to set initialization parameters such as the channel identifier VCI, the fluctuation absorption delay time T and the window size W from an external CPU or the like. These initialization parameters are values set in the register circuit (REG) 10 at the time of initial startup. However, since it is necessary to refer to the same register even when restarting from the self-reset, the device of the present invention is configured such that the contents of the register storing these parameters are not initialized at the time of the self-reset. I am trying.

An outline of the self-reset operation when an underflow of ROBF4 or an overflow of RIBF2 occurs will be described below with reference to the flowchart shown in FIG. First, the error monitoring circuit (MONI) 11 receives an OUF signal indicating an underflow of ROBF4,
The IOF signal indicating the overflow of RIBF2 is input, and these signals are monitored by the cell cycle clock output from the sequence control circuit (SEQ) 6 (S14a). When either of the signals is ON (S14a, YES), the MONI 11 outputs SELF.
The RST signal is turned on (see FIG. 9), and a reset command is issued to the RST REG (reset register) 101 (see FIG. 8) in the REG 10. At the same time, the external terminal I
The NT signal is turned on (S14b). With this INT signal, it becomes possible to notify the external CPU or the like that the self-reset has been performed.

Upon receiving the reset command, the REG 10 sends a reset signal (RS
T) is transmitted. With this reset signal, the cell inverse conversion device initializes the fluctuation absorption timer 71 (see FIG. 4) of the timer circuit (TIM) 7, the addresses of RIBF2 and ROBF4, and executes self reset (S1).
4c). However, at the time of this self-reset, REG10
Holds the initial parameters held in the respective parameter registers in its own circuit, which will be described later, and the error information stored in the error registers, not as an initialization target, but holds them as they are. Therefore, when the external CPU or the like cannot recover by self-resetting, it is possible to divide the recovery procedure by referring to the contents of the error register and to perform the recovery by the optimum coping method. The content of the error is configured to disappear when it is read from the outside.

After the completion of the self-reset, the cell inverse conversion device turns off the INT signal for notifying the external CPU or the like that the self-reset has been performed, and after this self-reset, the initial value held in the REG 10 is retained. It restarts by referring to the parameters and recovers to the state where the first received cell arrives. However, if the error as described above occurs again despite the recovery work by the self-reset, the self-reset is repeated again. In addition, if recovery is not possible due to self-reset, setting error (internal setting) at startup of the cell reverse conversion device, setting error of other external devices such as terminals (external setting), line failure or cell reverse conversion Although a device failure (failure) or the like may occur, in such a case, the coping operation is performed in accordance with a procedure (see FIG. 15) separated from the self-restoration processing described above.

Here, a specific configuration example of the REG 10 will be described. In FIG. 8, the above-mentioned initial parameters and error information are VCI REG102, W REG1.
03, T REG 104 and the like and the error register (ERR REG) 105. Of these, the error register (ERROR
The contents of G) 105 are shown in FIGS. 12 and 13. As can be seen from FIG. 12A, the error register 105
Has a flag area corresponding to each error, and has a structure for holding the error information by turning on the corresponding flag according to the occurrence status of the error. As a result, for example, the specific contents of the error register 105 when the above-mentioned errors E1 to 8 occur are changed as shown in FIGS. 13A to 13E in accordance with the error. Become.

That is, when the above errors E1 to 8 occur, various error flags are turned on as shown in FIGS. 13A to 13E, and the error counter [FIG. 12B to FIG. )] Is also counting up. Therefore, when separating the work for restoration, for example, when TERR and IUF are on, the fluctuation absorption time is set to a value larger than the previous time and the operation is restarted. When IOF is on, the fluctuation absorption time is set to the previous time. Set it smaller and perform the startup operation.

When the error is resolved after the resetting, it can be understood that the cause is that the setting of the fluctuation absorption time is inappropriate (internal setting). However, if an error still occurs due to such a reset operation, it is possible that there is an external setting, a line failure, or a failure.
You have to entrust U and others to try to restore it. According to the configuration of the present invention, even under such a situation, the external CPU or the like can easily deal with the isolation based on the contents of the error register that is continuously held in the REG 10 even when the self reset is performed. Like
FIG. 15 is a flow chart showing an example of a procedure for carrying out the isolation of the recovery work including the case where the self-reset does not recover.

[0065]

As described above, according to the present invention,
When an error such as a fluctuation absorption buffer memory overflow or dual port memory underflow occurs, the parameters necessary to start the operation and operation status information (operation past error information, etc.) indicating the operation status of the device itself are held in the register circuit. The timer circuit, fluctuation absorption buffer memory, and dual port memory are automatically initialized as they are, and after the initialization is completed, the operation is restarted based on the parameters and operation state information held in the register circuit to perform the cell reverse conversion operation. Since it is designed to self-recover, it is necessary to deal with the recovery of the cell regeneration failure on the STM side caused by the cell discard and the increase of delay fluctuation caused by the line quality and the failure of the switching equipment or the header error. The device itself can automatically perform the resetting process. In both cases, after the initialization is completed, the operation is started up based on the parameters and the operation state information held in the register circuit, so that, for example, the fluctuation absorption time by the timer circuit is set to be shorter than that before (before the initialization due to an error). It is easy to move to control such as setting to a larger (or smaller), and it becomes possible to quickly recover to the cell reverse conversion operation after completion of initialization, and further, from an external CPU etc. to start the operation. There is no need for firmware processing related to regular monitoring of.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a cell inverse conversion device according to the present invention.

FIG. 2 is a detailed configuration diagram around RIBF in the cell inverse conversion device of the present invention.

FIG. 3 is a detailed configuration diagram of VFIL in the cell inverse conversion device of the present invention.

FIG. 4 is a detailed configuration diagram of a TIM in the cell inverse conversion device of the present invention.

FIG. 5 is a detailed configuration diagram of RASM in the cell inverse conversion device of the present invention.

FIG. 6 is a detailed configuration diagram around the ROBF in the cell inverse conversion device of the present invention.

FIG. 7: MEMC in the cell inverse converter of the present invention
The detailed block diagram of (1).

FIG. 8 is a detailed configuration diagram of a REG in the cell inverse conversion device of the present invention.

FIG. 9 is a detailed configuration diagram of MONI in the cell inverse conversion device of the present invention.

FIG. 10 is a time chart showing an example of error detection in the cell inverse conversion device of the present invention.

FIG. 11 is a time chart showing another example of error detection in the cell inverse conversion device of the present invention.

FIG. 12 is a detailed configuration diagram of an error register in a REG of the cell inverse conversion device of the present invention.

13 is a diagram showing each aspect of data at the time of various errors in the error register shown in FIG.

FIG. 14 is a flowchart showing an error monitoring operation in the cell inverse conversion device of the present invention.

FIG. 15 is a flowchart showing fault isolation when the cell reverse conversion device of the present invention cannot be recovered by self-resetting.

FIG. 16 is a schematic configuration diagram of an ATM network in a broadband ISDN.

FIG. 17 is a diagram showing a format of a cell used for ATM network communication.

FIG. 18 is a block diagram showing the configuration of a conventional cell inverse conversion device of this type.

FIG. 19 is a flowchart showing a startup control sequence of a conventional cell inverse conversion device.

FIG. 20 is a diagram showing a data structure stored in the RIBF of the cell inversion device.

FIG. 21 is a flowchart showing a process of cell discard and mixture detection in the cell reverse conversion device.

FIG. 22 is a flowchart showing a periodic device monitoring operation in the conventional cell inverse conversion device.

[Explanation of symbols]

1 Filter circuit (VFIL) 2 Fluctuation absorption buffer memory (RIBF) 3 Inverse conversion circuit (RASM) 4 Speed conversion dual port memory (ROBF) 5 STM processing circuit (STM) 6 Sequence control circuit (SEQ) 7 Timer circuit (TIM) 8 Memory management circuit 1 (MEMC1) 9 Memory management circuit 2 (MEMC2) 10 register circuit (REG) 101 Reset Register (RST REG) 102 VCI register (VCI REG) 103 Window size register (W REG) 104 Fluctuation absorption time register (T REG) 105 Error register (ERR REG) 11 Error monitoring circuit (MONI)

Continuation of front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) H04L 12/56 H04L 13/08

Claims (3)

(57) [Claims] 1. A cell used for fixed bit rate communication, which is used as a receiving side module of an ATM communication device for converting information into a cell of a fixed length packet for communication and for restoring an input cell to original fixed bit rate data. In the inverse conversion device, a filter circuit that extracts cells addressed to itself from the input cells, a fluctuation absorption buffer memory that temporarily stores the extracted cells and absorbs fluctuations in arrival of the cells, and fluctuations absorption A cell reverse conversion circuit that takes in cell data from the buffer memory and extracts the original fixed bit rate data, a timer circuit that manages the operation start timing of the cell reverse conversion circuit, and a speed of the cell reverse conversion circuit and the output side. It has a dual port memory for conversion and an interface function with an external control device, and has the Register circuit that stores operating state information indicating the operating state of the data and its own device, and retains the parameter and operating state information as they are even when a reset command is given, an overflow of the fluctuation absorption buffer memory, and the dual port memory A memory management circuit for managing the underflow of the timer circuit, monitoring the error of the fluctuation absorption buffer memory and the dual port memory based on the management result, and when the error occurs, the reset command is given to the register circuit to provide the timer circuit. , The fluctuation absorption buffer memory and the dual port memory are automatically initialized, and after the initialization is completed, the operation is restarted based on the parameter and the operation state information held in the register circuit to perform the cell reverse conversion operation. And an error monitoring circuit for self-recovering Cell inverse conversion device according to claim. 2. A timer circuit sends out an operation start timing signal of the inverse cell conversion circuit at each preset fluctuation absorption delay time, starts measurement of a cell arrival interval at each set time, and 2. The cell inverse conversion device according to claim 1, wherein a time-out signal is notified to the register circuit when the cell arrival interval exceeds the set time. 3. The operation state information includes an overflow detection signal of the fluctuation absorption buffer memory, an underflow detection signal of a speed conversion dual port memory, a time-out signal indicating that a cell arrival interval has exceeded a set time, and the cell. The cell inverse conversion device according to claim 1, wherein at least error information of the inverse conversion circuit is used.