JP3401221B2 - Storage device - Google Patents

Description

Detailed Description of the Invention

[0001]

The present invention relates to a workstation,
The present invention relates to a storage device such as a personal computer, and particularly to a configuration for reducing the power consumption of the storage device .

[0002]

2. Description of the Related Art Conventionally, various studies have been made to reduce the power consumption of peripheral devices such as workstations and personal computers and peripheral control LSIs (Large Scale Integrated) for controlling them.

For example, a peripheral control LSI has a dedicated input terminal for designating a low power consumption mode, and is kept in the low power consumption mode for a period instructed by an output signal from an external microprocessor or a low power consumption controller. Composed. As a result, in a peripheral control LSI, for example, in a digital circuit that operates with a reference clock, some or all of the clocks are stopped for the specified period to reduce power consumption. or,
Also in the analog circuit inside the peripheral control LSI, the power consumption is reduced by cutting off part or all of the current source circuit during the designated period.

Further, as another conventional example, a hard disk,
For peripheral devices such as CDROM (Compact Disk Read Only Memory) and floppy disk, a small hard disk device, DRR04, issued by Alps Electric Co., Ltd.
As described in the 0C product specification (1st edition), in order to reduce the size and weight of the system, a structure that suppresses power consumption except when a command is received from a microprocessor or the like constituting a host computer and is executed Has become.

FIG. 20 shows a schematic diagram of the structure of the DRR040C. This DRR040C is a disk 180 made of a magnetic material.
1 and a head 1802 for reading the magnetic information recorded on the disk 1801, and the head 1802 for the disk 180
Head actuator 18 for moving to a desired position on
03, a spindle motor 1804 for rotating the disc 1801, an actuator control circuit 1805 for controlling the operation of the head actuator 1803, and DRR0.
CPU (Central Processin) that controls the operation of the entire 40C
g Unit) 1806, a spindle motor control circuit 1807 which controls the spindle motor 1804 by a control signal from the CPU 1806, a D / A converter 1808 which converts digital information from the CPU 1806 to analog information and passes it to the actuator control circuit 1805, A READ / WRITE circuit 18 that shapes the waveform of the signal read from the head 1802 and converts it into a pulse train.
10, a hard disk controller 1811 for converting the pulse train generated by the READ / WRITE circuit 1810 into parallel data, the READ / WRITE
The CPU 1806 converts analog information such as head positioning detected by the circuit 1810 into digital information.
The signal read from the A / D converter 1809, the disc 1801 or the signal given from the AT bus 1812 is temporarily stored in the AT bus 1812 and the disc 180.
A buffer 1813, C for adjusting the speed difference of reading 1
The AT bus control circuit 1814 is controlled by the PU 1806 and controls the AT bus 1812.

Here, the AT bus means a bus having a PC / AT (this is a registered trademark of IBM Corporation in the United States) interface.

When the DRR040C receives a command from the AT bus and is not executing the command, the DRR040C controls as follows to suppress power consumption.

1. When all commands received from the AT bus are complete, the DRR040C enters idle mode (1). When in the idle mote (1) state, the CPU 1806 in the DRR040C stops the hard disk controller 1811, and the READ
The power of the / WRITE circuit 1810 is cut off.

2. If the AT bus is not accessed for 5 seconds after entering the idle mode (1), D
The RR040C enters idle mode (2). When in the idle mode (2) state, the CPU 1806 in the DRR040C causes the actuator control circuit 18
05, D / A converter 1808, A / D converter 1
The power of 809 is cut off.

3. The DRR040C enters the standby mode when it is not accessed from the AT bus for a certain period of time (default is 3 minutes) after entering the idle mode (2). When in the standby mode, DRR0
The CPU 1806 in 40C turns off the power supplies of the spindle motor control circuit 1807 and the spindle motor 1804. Further, the CPU 1806 also enters a sleep state.

4. Upon receiving the sleep command from the AT bus, the DRR040C enters the sleep mode, which is a completely low power consumption mode. When in the sleep mode, the DRR040C further puts the AT bus control circuit 1814 in the sleep state from the standby mode. DRR040C is A when in sleep mode
The drive can be started only by RESET without receiving a command from the T bus. DRR04
By operating as described above, 0C can reduce power consumption when a command is received from the host computer and is not being executed.

[0012]

Among the above-mentioned conventional techniques, in the former case, a microprocessor or controller external to the peripheral control LSI instructs the low power consumption mode. Therefore, in order to realize the maximum reduction in power consumption, an external microprocessor or the like needs to give instructions in a low power consumption mode many times, which causes a problem that the load of the external microprocessor or the like is too large. there were.

Further, since the external microprocessor or the like cannot accurately grasp the operation state inside the peripheral control LSI which instructs the power consumption reduction, it is not possible to perform the control for the power consumption reduction in detail and the maximum. However, there is a problem that the low power consumption cannot be realized.

On the other hand, in the latter conventional example, in the standby mode, the current consumed in the AT bus control circuit 14 is not taken into consideration, and there is a problem in that the power consumption increases. In the sleep mode, which is a completely low power consumption mode, commands are not accepted at all and can be activated only by a reset from the host computer, etc., and the responsiveness is not taken into consideration, and the overhead of the host computer is large. There was a problem of becoming.

An object of the present invention is to provide a configuration for reducing power consumption of peripheral devices and peripheral device control devices.

Another object of the present invention is to provide a storage device capable of reducing power consumption to the maximum while reducing the load on an external processor or the like.

A further object of the present invention is to provide a storage device capable of eliminating power consumption while waiting for a command from an external processor or the like.

Still another object of the present invention is to provide a storage device having good responsiveness even when the power consumption in a command waiting state from an external processor or the like is reduced.

Another further object of the present invention is to use SCSI (Sm
All computer system interface) It is an object of the present invention to provide a storage device that can easily reduce the current consumption of the system.

[0020]

In order to achieve the above object, according to the present invention, there is provided a peripheral control device connected to a bus to which external processing means such as a processor is connected, the access from the external processing means. It has an activation start detection means for detecting the start, an activation end detection means for detecting the end of the access operation, and a power consumption control means. The output of the activation start detection means reduces the power consumption control means. The power mode is released, and the output of the activation end detecting means controls the power consumption control means to return to the low power consumption mode.

The access of the peripheral control device by the external processing means is started when the command is set from the external processing means to the peripheral control device or when the status of the peripheral control device is detected by the external processing means.

Further, in the present invention, the bus connecting the host computer and the main CPU to the peripheral equipment is SCS.
In a SCSI system composed of I-bus, a peripheral device control device by a host computer or L for peripheral control
The ID recognition means for detecting the SCSI ID during the selection phase, which is the start of SI access, is the activation start detection means described above.

[0023]

According to the present invention, when the peripheral control device or the peripheral control LSI is waiting for a command from the host computer such as an external microprocessor, the low power consumption mode is set and the command setting / status from the host computer is set. When access such as detection is started, the low power consumption mode is released. As a result, it is possible to reduce cumulative and useless power consumption loss inside the device or the LSI, and realize thorough power consumption reduction.

The activation start detecting means, the activation end detecting means, and the power consumption controlling means described above are located inside the peripheral device control device and the peripheral control LSI. The peripheral device control device is a control device for peripheral devices with respect to the main CPU, and includes, for example, a file controller, a display controller, a keyboard controller, a printer controller,
It means a communication controller, and the peripheral control LSI means those semiconductor integrated circuits.

In the present invention, the power consumption control means, in the sleep mode which is a low power consumption mode, is a clock source of a digital circuit of a main part inside the device or LSI,
Alternatively, by cutting off the power supply of the analog circuit, the operation of the main part of the device or LSI is stopped and the low power consumption state is maintained. And the host computer and main CP
When access is started by command setting or status detection from U, the activation start detection means that is always operating detects the start of access, and based on this detection,
The power consumption control means releases the low power consumption mode. Further, when the activation end detection means detects the end of the operation accompanying the start of access, the power consumption control means sets the low power consumption mode again.

In the SCSI system according to the present invention, the SCSI ID recognition means is separated from other functional blocks, and the other functional blocks are set in the sleep mode in a command waiting state or the like.
It is possible to easily reduce the power consumption of the SI system.

The outline of the present invention has been described above, but the present invention is not limited to these descriptions. Other aspects of the present invention will be apparent from the embodiments of the present invention described below.

[0028]

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 3 shows an example of the configuration of an information processing device in which the peripheral device control device or peripheral control LSI of the present invention is used. This information processing apparatus has a basic configuration such as a workstation and a personal computer, and has a main CPU 1
4, ROM 15 and RAM 16 are connected to the bus 50. A file controller 17, a display controller 18, a keyboard controller 19, a printer controller 20, a communication controller 21 and the like are connected to the bus 50. In addition, these controllers include a file device 22, a liquid crystal display, a CRT display 23, and
A keyboard 24, a printer 25, and a communication path are connected.

Peripheral control device or peripheral control LS of the present invention
I means a file controller 17, a display controller 18, a keyboard controller 19, a printer controller 20, a communication controller 21, and the like in such an information processing apparatus.

FIG. 1 is a diagram showing a peripheral control device or a one-chip peripheral control LSI according to an embodiment of the present invention. The power consumption control circuit 2 shown in FIG.
When I is not receiving command settings or accesses other than commands from the main CPU 14 via the bus 50, the internal clock is stopped and the register groups 8-10, I
It is a power consumption control unit that stops the operations of the / O control circuits 11 to 13 and sets the sleep mode to prevent the loss of power consumption, and also has a function of an activation detection unit. At this time, the power consumption control circuit 2, the address latch 3, the latch 6, the address decoder 4, and the gate 5 are always operating.

After that, when a command is set from the main CPU 1806, the power consumption control circuit 2 causes the main CPU 14 to perform chip select, write strobe, etc., and the output of the address coder 4 and the gate 5.
Command setting start, that is, activation is detected and the internal clock is set to the register groups 8 to 10 and the I / O control circuits 11 to 11.
Supply to 13.

As a result, the register groups 8 to 10 and I / O
The control circuits 11 to 13 become operable and the latch 6
The command held in the register is transferred to the command register in each register group 8-10. Therefore, the main CPU
The command from 1806 is in the execution state. When this command processing is completed, the I / O control circuits 11 to 13 output a command end signal to the NOR gate 1 as the activation end detection means, and these NOR gate 1 outputs are input to the power consumption control circuit 2. To be done. Power consumption control circuit 2
This stops the internal clock output again and returns to the low power consumption mode.

Next, in access other than command setting from the main CPU 14, the power consumption control circuit 2 detects access start, that is, activation by chip select, write strobe, or read strobe, and controls LSI or control. Enables the device and releases the low power consumption mode. At this time, the address latches 3 and 6 are always in operation. Write data is output to the inside via the latch 6, and read data is output to the outside via the gate 7. Further, such an intermittent access is short in one cycle, and therefore the activation end detection means provided in the power consumption control circuit 2 detects the end thereof, and returns to the low power consumption mode.

Next, an example of the internal configuration of the power consumption control circuit 2 will be described with reference to the block diagram of FIG. 2 and the timing charts of FIGS. When the address and command data are sent from the main CPU 14 together with control signals such as chip select and write strobe, the power consumption control circuit 2 operates the gate 26 and the gate 28 from the chip select and write strobe as shown in FIG. The RS flip-flop 29 is set via the
₁ ).

At this time, the command data is held in the latch 6 by the latch enable signal output from the gate 43, and similarly, the address is held in the address latch 3 by the output address latch enable of the gate 28. R
The output of the S flip-flop 29 is cycled by the edge-triggered flip-flops 31 and 32, and the output of the flip-flop 32 activates the internal clock via the gate 33 to release the low power consumption mode (time point t ₂ ). .

As a result, the internal write strobe output from the flip-flop 34 is output, and the command write strobe output is input to the flip-flop 41 via the address decoder 4 (time point t ₃ ). At this time, the command held in the latch 6 by the command write strobe is transferred to the command registers of the register groups 8 to 9, and the processing in each I / O control circuit 11 to 13 starts. Further, the output of the flip-flop 41 is set to a state in which it can receive the command end signal via the gate 1 of the I / O control circuits 11 to 13.

After that, when the command processing of each of the I / O control circuits 11 to 13 is completed, the command end signal via the gate 1 is input to the gate 38 of the power consumption control circuit 2 (time point t ₄ ) and the gate 39, The RS flip-flop 29 is reset via the flip-flop 40 (time point t ₅ ). The output of the gate 29 is a flip-flop 31,
The gate 33 is controlled via 32 to stop the internal clock and return to the low power consumption mode (time point t ₆ ).

Next, an access operation other than command setting of the main CPU 14 will be described with reference to FIG. The sequence for releasing the low power consumption mode is the same as that in the case of FIG. 4, but regarding the return to the low power consumption mode, the internal write strobe output from the flip-flop 34 of FIG.
Alternatively, when the internal read strobe which is the output of the flip-flop 36 is asserted (time point t ₁₀ ), the gate 35,
The RS flip-flop 29 is reset as shown in FIG. 5 via 37 and 39 and the flip-flop 40 (time point t ₁₁ ). The output of the RS flip-flop 29 controls the gate 33 via the flip-flops 31 and 32,
The internal clock is stopped to return to the low power consumption mode (time point t ₁₂ ). That is, in this embodiment, the flip-flops 34, 36, 40 and the gate groups 35, 37,
38 and 39 function as activation end detecting means.

In the above description of the embodiments, the power consumption reduction in the digital circuit has been described. However, regarding the analog circuit, the output of the flip-flop 32 or the output of the RS flip-flop 29 of FIG. By cutting off the current source inside, low power consumption can be realized.

Now, the second embodiment of the present invention will be described in detail with reference to the drawings starting from FIG. The second embodiment relates to a system in which the present invention is applied to SCSI (Small Computer System Interface). SCS
The I system is applied when a SCSI bus is used as the bus 27 (FIG. 3) to which the above-mentioned various peripheral devices and peripheral control devices are connected.

General SCS for controlling SCSI bus
As the I control LSI, for example, advanced SCSI controllers 53C90A and 53C90B manufactured by NCR, Inc.
There are some data sheets described in, but no consideration is given to low power consumption. Regarding the basic protocol of the SCSI bus, for example, on March 9, 1990, ANSI (American National standard for
information system), see SCSI-2, etc.

FIG. 6 shows the principle configuration of the second embodiment. In the figure, the SCSI system comprises a SCSI bus 601 and a SCSI controller 602.
The SI controller 602 is a SCSI ID recognition unit 603.
And the other functional blocks 604 are separated and independent in terms of power supply. Still another function block 604 has a sleep function. Note that reference numeral 605 is a sleep release signal that signifies the start of activation. This functional block 604 is
As will be described in detail later, when all the commands in the command queue are completed, the clock input is disconnected and the sleep mode, which is a low power consumption mode, is entered.
In the command waiting state, the SCSI system stops the operation except for the ID recognition unit 603 and consumes no current. Therefore, the current consumption can be suppressed to be small.

The ID recognition unit 603 has a function of detecting that the SCSI system is selected as another SCSI system via the SCSI bus. The ID recognition unit 603 has a function as the activation start detection means, and thus the other SCS
When it is detected that the I system is selected, a wakeup signal for activating a minimum required part or all of the circuits is sent to the function block 604. In other words, the clock can be input to and activated in the minimum required part or all of the circuits. Further, the ID recognition unit 603 and the other functional block 604 are separated from each other in power source, and the functional block 604 is powered off in the sleep state. Since the connection is made when the sleep release signal 605 sent from the ID recognition unit 603 is received, the power consumption in the sleep mode can be minimized.

Also, the LS for SCSI control in this embodiment
I has a sleep state activation register or a sleep state activation input signal, and when the sleep state setting value is set or the sleep state activation signal is asserted, the circuits except for the ID recognition unit 603 sleep. It becomes a state. Further, when the SCSI control LSI receives the sleep release signal sent from the ID recognition unit 603, it releases the sleep for each circuit block according to the value set in the register that manages the sleep release information for each circuit block. Therefore, the current consumption can be controlled to be minimum depending on the selection state of the ID recognition unit 603 and the system configuration. Further, the SCSI control LSI
Has a sleep release signal 605 of an external circuit to which the ID recognition unit 603 is output, in addition to the normal interrupt signal.
When the CSI control LSI recognizes that it has been selected from another SCSI system, the ID recognition unit 603 asserts the sleep release signal 605 of the external circuit. A power supply circuit for the functional block can be connected, and the sleep state can be easily restored.

FIG. 7 shows a specific configuration for realizing the principle of the second embodiment described above. 1801-181 in the figure
Reference numeral 3 indicates the same element as that of the conventional structure shown in FIG. Internal CPU 180
SCS which is controlled by 6 and controls the SCSI bus 601
The sleep signal 837 provided from the I-bus control circuit 701 and the internal CPU 1806 shuts off the power supply to all circuits except some of the SCSI bus control circuit 701, and outputs from the SCSI bus control circuit 701. By the sleep release signal 833, the internal CPU 1806, S
The power supply control circuit 835 as a power consumption control means for controlling the power supply to the CSI bus control circuit 701 and the buffer 1813 is a new component.

FIG. 8 shows a block diagram of an example of the SCSI bus control circuit 701. For convenience of illustration, the right side of the figure is SC
It is connected to the SI bus 601 and the left side of the figure is the internal bus 181.
Please note that it is connected to No. 5 and the left and right are reversed from FIG. 7. The SCSI bus control circuit 701 is roughly divided into functional blocks 841, 842 and 843 which are divided by broken lines.

In the figure, the internal CPU data bus 801 is a data bus for accessing the SCSI bus control circuit 701 from the CPU 1806 and constitutes a part of the internal bus 1815. The read / write controller 802 outputs the RD /, WR output by the CPU 1806, the hard disk controller 1811, and the like.
/, CS /, DACK /, DWR /, DRD /, etc., the internal register 8 of the SCSI bus control circuit 701.
03-811, 815-818, 1608, FIFO8
19 is a circuit for generating a timing signal for accessing 19 or the like. In this specification, “/” after the signal name means an inverted signal. Internal registers 803, 804, 8
05,806,807,808,809,810,81
1 is a transfer count value register, a destination ID register, a command register, a config 1 register, a config 2 register, a synchronous offset register, a synchronous transfer cycle register, a timeout register, and a clock conversion register, and the CPU 1806 stores values in these register groups. By setting, the SCSI protocol can be controlled.

Further, 812 is a SCSI data bus single-ended receiver, and 813 is a SCSI data bus single-ended 48 mA sink driver. 814
Is a SCSI bus control signal single-ended receiver, 8
Reference numeral 24 is a SCSI bus control signal single-ended 48 mA sink driver. 815, 816, 817, 818
Are a transfer counter, a status register, an interrupt register, and a sequence step counter, respectively.
By reading these register groups, the 1806 can
The SI protocol execution status can be known.

Reference numerals 819 and 820 denote FIFOs having a function of temporarily storing the data transferred from the CPU 1806 or the buffer 1813 to the SCSI bus, or the SCSI bus or the buffer 1813 to the CPU 1806.
821 is the SCS from the CPU 1806 and the buffer 1813.
A parity detector and a parity generator for data transferred from the I bus or the SCSI bus to the CPU 1806 and the buffer 1813. 823 is a sequencer,
Setting registers 803-811 and receiver 814
SCS according to the value of SCSI bus control signal given by
I protocol can be controlled. Further, the result is output to the status register 816 and the interrupt register 817.

Reference numeral 825 denotes I as a main part in this embodiment.
The D recognition unit corresponds to the ID recognition unit 603 as the activation start detection unit shown in FIG. 6 and is included in the functional block 841. The ID recognition unit 825 monitors the values of the SCSI bus control signals BSY / and SEL /, and when BSY / is at a high level and SEL / is at a low level, the ID of this embodiment is detected.
OWNID and SCSI data bus SDBO / ~ S
Compared with the value of DB7 /, if they match, the sleep release signal 833 is output.

Reference numeral 826 is a sleep control circuit. The sleep control circuit 826 receives the sleep control signal 82 from the sleep setting signal 830 given from the sequencer 823.
8, the sleep control signal 829 and the sleep signal 827 are asserted, and the sleep control signal 828, 829,
It has a function of negating the sleep signal 827. The clock 834 is a clock signal obtained by ANDing the sleep control signals 828 and 829 and used as the clocks of the functional block 842 and the functional block 843, respectively.

Reference numeral 835 is a current control circuit as a power consumption control means, which is composed of a switch 836 and a power supply Vcc which are controlled by a sleep signal 837 given from the CPU 1806. The current control circuit 835 includes a power supply Vcc2 that supplies current to a functional block 841 including an ID recognition unit 825, a sleep control circuit 826, a receiver 812, and a receiver 814, and functional blocks 842 and 8.
The power supply Vcc1 for supplying a current to 43 is supplied independently of each other. That is, the current control circuit 835
Is a sleep signal 837 provided from the CPU 1806.
Controls the switch 836 so that Vcc1 is turned off and the sleep release signal 833 supplied from the ID recognition unit 825 turns Vcc1 on.

Next, detailed configurations of the receiver 812 and the receiver 814 will be described with reference to FIGS.

For the receiver 812, as shown in FIG. SDBO / to SDB7 / 1101, 1106, 1
110, 1114, 1118, 1122, 1126, 1
Receivers 1102, 1107, 1111 and 11 with hysteresis for inputting 130 and SDBP / 1134 respectively
15, 1119, 1123, 1127, 1131, 11
35 and three-stage synchronizing circuits 1104, 1108, 1112 for synchronizing the output signals thereof with a clock 1103 (which is a clock equivalent to the clock 834 in FIG. 8).
1116, 1120, 1124, 1128, 1132
1136. 3-stage periodic circuit 1104-
Reference numerals 1136 denote internal signals 110 of SDBO to SDBP.
5 to 1137 are output.

On the other hand, the receiver 814 basically has the structure shown in FIG.
2, the SCSI control bus signal BSY / 120
1, SEL / 1205, REQ / 1209, ACK / 1
213, I / O / 1217, C / D / 1221, MSG
/ 1225, ATN / 1229, RST / 1233 (refer to the above-mentioned SCSI protocol standard for the function of these signals) receivers with hysteresis 1202, 1206, 1210,
1214, 1218, 1222, 1226, 1230,
1234 and the signals output by these clocks 1103
Three-stage periodic circuit 1203, 1207, 12 synchronized by
11, 1215, 1219, 1223, 1227, 12
31 and 1235. Three-stage periodic circuit 12
03 to 1235 are BSY internal signals 1204 and S, respectively.
EL internal signal 1208, REQ internal signal 1212, AC
K internal signal 1216, I / O internal signal 1220, C / D
The internal signal 1224, the MSG internal signal 1228, the ATN internal signal 1232, and the RST internal signal 1236 are output.

In the present embodiment, the receiver 814 receives the sleep signal 827 from the sleep control circuit 826 as is apparent from FIG. This sleep signal 827
Therefore, the receiver 814 in the present embodiment corresponds to
REQ / 1209, ACK / 1213, I / O / 1
217, C / D / 1221, MSG / 1225, ATN
The receiver circuit portion for inputting / 1229 and RST / 1233 has the configuration shown in FIG. Although the receiver circuit portion corresponding to MSG / 1225 is shown in FIG. 10, REQ / 1209, ACK / 1213, I
/ O / 1217, C / D1221, ATN / 1229,
The RST / 1233 has the same configuration.

Here, as described above, the sleep signal 8
Reference numeral 27 is a signal that puts the receiver 814 in the sleep mode. When the sleep signal 827 is activated, the circuit of FIG. 10 becomes REQ / 1209, AGK / 1.
213, I / O / 1217, C / D / 1221, MSG
The REQ internal signal 1212 to the RST internal signal 1236 are kept inactive regardless of the values of / 1225, ATN / 1229 and RST / 1233.
In the figure, reference numerals 1001, 1002 and 1003 respectively denote an inverter circuit, a 2-input NOR circuit and a 2-input OR circuit, and their operations will be described later.

BSY1201, SEL / 1205
The receiver circuit portion corresponding to No. 2 is a signal necessary for ID recognition of the SCSI protocol as shown in FIGS. 18 and 19, and the structure shown in FIG. It is because there is, S other than these
Since it is not a signal necessary for ID recognition of the CSI protocol,
The configuration of FIG. 10 controlled by the sleep signal 827 will be adopted.

Next, the structure of an example of the ID recognition unit 825 shown in FIG. 8 will be described with reference to FIG. The BSY internal signal 1204 and the SEL internal signal 1208 are input from the receiver 814 to the ID recognition unit 825, and the SDB0 is input from the receiver 812.
~ SDB7 internal signals 1105 to 1133 are input.
Then, the sleep release signal 833 is output. In the figure, 901 is an OWN ID register holding the ID of the SCSI system of the present embodiment, 902 is an inverter, and 9
03 to 912 are 2-input AND circuits, and 913 is an 8-input OR circuit.
Circuit. Details of the operation of the ID recognition unit 825 will be described later.

Next, an example of the configuration of the sleep control circuit 826 shown in FIG. 2 will be described with reference to FIG. As is clear from FIG. 8, the sleep control circuit 826 includes an ID recognition unit 8
Sleep release signal 833 from 25 and sequencer 82
The sleep setting signal 830 from 3 is input. Then, the sleep control signal 82 which puts the functional block 843 of the SCSI bus control circuit 703 of this embodiment into the sleep state.
8 and a sleep control signal 829 that puts the functional block 842 into the sleep state are output signals.

In FIG. 13, reference numeral 1301 is a sleep release selection register, and 1302 and 1303 are 2-input ANs.
D gates 1304 and 1305 are sleep control signals 82.
A set / reset type latch circuit which holds 8 and 829, respectively, and 1306 is a 2-input OR gate.

Now, the operation of the above-described second embodiment of the present invention will be described with reference to FIG.

First, prior to the description of the main part of this embodiment, S
The general sequence of CSI is shown in FIG. 17, FIG. 18, and FIG.
Will be described briefly. The SCSI system is composed of a host computer as an initiator that issues commands such as the main CPU 14 shown in FIG. 3 and a peripheral device as a target such as the file controller 17 shown in FIG.

As shown in FIG. 17, the SCSI system is in the bus free phase after reset by power-on. This bus free phase is a state where the SCSI bus is not used by any SCSI system. As shown in FIG. 18, when the SCSI system is in the bus free phase, BSY / 1201, SEL
/ 1205, SDB0 / to SDB7 / 1101 to 113
0, SDBP / 1134 is held in a negated state, that is, at a high level. Next, the initiator starts the arbitration phase to acquire the bus right. That is, BSY / 1201 is asserted, and SDB
0 / to SDB7 / 1101 to 1130, SDBP113
The OWN ID, which is the device number of the initiator, is output to 4. The initiator checks the ID on the SCSI bus in the arbitration phase, and acquires the bus right when the OWN ID is the highest priority ID. When the initiator acquires the bus right, it asserts SEL / 1205.

Next, the initiator starts the selection phase to select the target to which the command is issued. That is, BSY / 1201 is negated, and SDB0 / to SDB7 / 1101 to 1130, SD
In addition to OWN ID, BP / 1134 outputs PARTNER ID which is the device number of the target. The target is BSY / 1201 negated, SEL / 120
When 5 is detected to be asserted, the ID on the SCSI bus is compared with the OWN ID of the target.

When the ID on the SCSI bus and the OWN ID of the target match, the target is B
Assert SY / 1201 to respond to the initiator. When confirming that BSY / 1201 is asserted, the initiator negates SEL / 1205 and ends the selection phase. When the selection phase ends, SCSI enters the information transfer phase. In the information transfer phase, in the selection phase, commands between the connected initiator and target,
Send and receive data, messages and status.

When all commands, data, messages and statuses have been exchanged, the target is set to BSY /
1201 is negated and the bus free phase is entered.
Even if all commands, data, messages, and status have not been sent and received, if the target takes a long time to process, the target will be BSY / 1.
You can negate 201 and enter the bus-free phase. In this case, the target can start the arbitration phase when the internal processing is completed, select the initiator in the reselection phase, and continue to exchange commands, data, messages, and statuses. In addition, the initiator adds the queue tag message to the command to be transferred to the target, so that the target can simultaneously receive the commands from the plurality of initiators.

In the conventional SCSI control LSIs 53C90A and 53C90B manufactured by NCR, for example, BSY / is negated by constantly monitoring all signals of the SCSI bus by the receiver and checking by the sequencer when in the access waiting state. Detects that SEL / is in the asserted state and sets the ID on the SCSI bus to FI
The operation of the selection phase is performed by importing it into the FO and comparing it with its own ID in the sequencer. Therefore, even when waiting for a command from the initiator, the SCSI including the sequencer and internal circuits is always available.
The entire bus control circuit is operating and power consumption increases.

Now, the operation of this embodiment will be described. C
The PU 1806 (FIG. 7) outputs a sleep signal 837 to the power supply control circuit 835 when all the commands given from the SCSI bus 601 are completed and the command queue defined by the SCSI protocol becomes empty. The power supply control circuit 835 turns off Vcc1, sets the ID recognition unit 825 and the sleep control circuit 8 of the SCSI bus control circuit 701.
26, a receiver 812, a receiver 814, and a power block driving all circuits of the functional blocks 842 and 843 except a functional block 841 composed of two 2-input AND circuits, and enters a sleep mode.

As shown in FIGS. 10 and 12, the receiver 814 of this embodiment is BSY / 1201, SEL / 12.
With the exception of the input circuit 05, the sleep signal 827 is input, and when the sleep signal 827 is at the high level in the sleep state, the output of the 2-input NOR circuit 1002 (FIG. 10) is always fixed at the low level. Also, the output of the 2-input OR circuit 1003 is always fixed at the high level. Therefore, even if MSG / 1225 of the SCSI bus changes, the internal signal 1228 is fixed to the low level and does not change. In general, these circuits are made in CMOS and do not consume current when the signal does not change, so when in sleep mode, the receiver 814 is configured to be BSY / 1201, SEL.
Current is not consumed except for the / 1207 input circuit.

Next, when the SCSI bus enters the arbitration phase and enters the selection phase, BS
Y / 1201 becomes high level and SEL / 1205 becomes low level. Since the ID recognition unit 825 has the configuration shown in FIG. 9, the output of the inverter 902 becomes high level, and the output of the 2-input AND gate 903 becomes high level. Then, the ID value held in the OWN ID register 901 and SDB0 / to SDB7 / 1105 to 113
When the values of 3 match, the sleep release signal 833 becomes high level.

For example, if OWNID is set to "3", the SDB3 internal signal 1117 becomes high level when SDB3 / 1114 is at low level, and the output of the 2-input AND circuit 908 becomes high level. Therefore,
The output of the 8-input OR circuit 913 becomes high level. Therefore, the output of the 2-input AND circuit 912 becomes high level, the sleep release signal becomes high level, and it functions as an activation start signal. Therefore, the current control circuit 835
Turns on Vcc1 and sets the functional blocks 843 and 84.
Turn on the power of 2.

On the other hand, the sleep control circuit 826 has the configuration shown in FIG.
When the sleep release signal 833 becomes high level, the sleep state latch 1304 and the sleep state latch 1305 are reset according to the value of the sleep release selection register 1301, and the sleep control signal 82
8,829 is negated. Sleep control signal 828
Sets only the sequencer 823, the parity generator / detector 821 and the FIFO 819 to the sleep state. The sleep control signal 829 sets the circuits in the SCSI bus control circuit 701 other than the circuit controlled by the sleep control signal 828 to the sleep mode. For example, when the value of the sleep release selection register 1301 is “10” and the sleep release signal 833 goes high, the 2-input AND circuit 1
The output of 302 goes high, and the 2-input AND circuit 1
The output of 303 goes low.

Therefore, the sleep state latch 1304 is reset and the sleep state latch 1305 remains set. Therefore, the sleep control signal 828 becomes low level and the sleep control signal 829 becomes high level.
Therefore, only the sequencer 823, the parity detection / generator 821 and the FIFO 819 are released from the sleep state. The sequencer 823 is the parity detection / generator 8
After confirming that a parity error has not occurred in 21 and an ID error has not occurred,
Wake other circuits out of sleep mode. If a parity error or ID error occurs, the sequencer 823, the parity detection / generator 821 and the FI
The FO 819 goes into sleep mode again. This is the reason why the functional blocks 842 and 843 are controlled by separate sleep control signals 829 and 828 in this embodiment.

The CPU 1806 waits for an interrupt signal from the SCSI bus control circuit 701 for a certain period of time. If the interrupt signal does not come, the CPU 1806 outputs the sleep signal 837 to the power supply control circuit 835 again to function the SCSI bus control circuit 701. The power supplies driving all circuits except the block 841 are cut off.

According to the first embodiment of the present invention described above in detail, the current consumption in the command waiting state can be minimized without impairing the responsiveness.

Next, a third embodiment of the present invention will be described with reference to FIGS.

In general, since each SCSI bus uses an open collector or open drain driver of 48 mA sink, as shown in FIG. 14, the signal line of each SCSI bus is a system of a scale in which reflection is not a problem. Even if there is, it is necessary to attach 220Ω and 330Ω terminating resistors, and the terminating resistor is always 5V / 550Ω × 18 = 16.
A current of 4 mA flows.

Therefore, in the present embodiment, as shown in FIG. 15, SCSI bus control circuit 1500, SCSI bus 601, 220Ω × 18 resistors 1502, 330Ω ×
18 resistors 1503, 440Ω × 18 resistors 150
4,660Ω × 18 resistors 1506 and switch 1
It is composed of 501 and 1505.

The configuration of the SCSI bus control circuit 1500 in this embodiment is shown in FIG. In the figure, the external CPU data bus 801 is the CPU 1806.
(FIG. 7) is a data bus for accessing the SCSI bus control circuit 1500. In the figure, blocks denoted by the same reference numerals as those in FIG. 8 are blocks having the same functions as those in FIG. 8 and will not be described in detail here. 1601
Is a sequencer for controlling the SCSI bus control circuit 1500 of this embodiment, and 1602 and 1603 are selectors. 1604 and 1606 are SCSI data bus single-ended 48 mA sink drivers, which correspond to the drivers 813 and 824 in the previous embodiment. Reference numerals 1605 and 1607 denote SCSI data bus single-ended 24 mA sink drivers. Selector 16
The function of 02, 1603 is 48 mA as described later.
It has a function of switching between the sync drivers 1604 and 1606 and the 24 mA sync drivers 1605 and 1607.
Reference numeral 1608 denotes a selector switching register, which is a CPU 180.
The selector switching information written by 6 is held.

Although the schematic configuration of the hard disk device shown in FIG. 7 is not shown here, the power supply control device 835 is not necessary in this embodiment, and the bit switch for giving selector switching information to the CPU 1806 is C.
It is functionally added as an input means to the PU 1806.

Next, the operation of this embodiment will be described.
In this embodiment, the CP is based on the bit switch operation by the user.
U1806 is the SCSI bus control circuit 1500,
A control signal is generated by the selectors 1602 and 1603 so as to select either the 48 mA sync driver or the 24 mA sync driver. That is, the CPU 1806 fetches the value of the bit switch and writes the value in the selector switching register 1608 using the internal CPU data bus 801. The selector switching register 1608 outputs the selector switching signal 1609 to each selector 1602 according to this value.
Send to 1603.

For example, when connecting to a relatively large system in which the SCSI system shown in FIG. 16 is connected to 8 units, the external CPU 1806 is set to 48 mA by the user.
The value of the bit switch switched to support the sync driver is written in the selector switching register 1608, and the selector switching register 1608 uses the value to control the signal 16
09, the selectors 1602 and 1603 are 48 mA.
The sync driver 1604, 1606 is selected.

The user also sets the switch 1501 in FIG. 15 to the connected state and the switch 1505 to the disconnected state. By connecting in this way, a SCSI bus driver that complies with the SCSI protocol can be configured, and a maximum of 6
Up to 8 units can be connected. However, a current of 48 mA × 18 = 864 mA is consumed in the all-terminal arsato state, and a current of 164 mA is consumed even in the all-terminal negated state.

Next, in the case of incorporating in a relatively small system such as a notebook computer in which reflection is not a concern, 4 is required.
8mA sync driver is not required, so external CPU 18
06 is a selector that switches the selectors 1602 and 1603 to 2 based on the bit switch that is switched to support the 24 mA sink driver.
Set to select 4mA sync driver. or,
The user sets the switch 1505 in FIG. 15 to the connected state and the switch 1501 to the disconnected state. By connecting in this way, a SCSI bus driver using a 24 mA sink driver can be constructed. In the asserted state of all terminals, the consumption current is 24 mA × 18 = 432 mA, and in the negated state of all terminals, the consumption current is 82 mA, and the consumption current can be about half that in the case of using the 48 mA sink driver.

That is, since the SCSI control LSI of this embodiment has both a SCSI bus driver with a small pull-in current and a 48 mA sink SCSI bus driver, a 48 mA sink SCSI bus driver is used in a normal SCSI system. In the case of a small-scale SCSI system which is used and does not care about reflection, by using a SCSI bus driver with a small pull-in current, it is possible to reduce the current consumption at the time of asserting each terminal. Furthermore, when using a SCSI bus driver with a small pull-in current, by using a termination resistor according to the pull-in current, a 48 mA sink SCSI bus driver is used, and compared with the case of using termination resistors of 220Ω and 330Ω. Since the resistance value of the terminating resistor becomes large, the current consumption at the time of negating each terminal can be reduced in the case of a small-scale SCSI system in which reflection is not a concern.

Further, the SCSI system of this embodiment is
Small current draw SCSI bus driver, 48mA
The sink SCSI bus driver can be switched. When using a SCSI bus driver with a small pull-in current, a terminating resistor is connected according to the pull-in current. When using a 48 mA sink SCSI bus driver, 220Ω and 330Ω are used.
By connecting the Ω terminating resistor, the optimum SCSI bus driver can be selected according to the size of the system, and the current consumption can be minimized.

[0089]

According to the present invention, the power consumption of the storage device can be reduced. In addition, memory that can reduce the power consumption to the maximum while reducing the burden on the external processor etc.
A device can be provided. Further, in the peripheral control device, it is possible to reduce power consumption in a command waiting state from an external processor or the like and maintain good responsiveness. In particular, it is possible to easily reduce the current consumption of the SCSI system.

[Brief description of drawings]

FIG. 1 is a circuit block diagram showing an embodiment of a peripheral control device according to the present invention,

FIG. 2 is a circuit configuration diagram showing an example of a power consumption control circuit 2 shown in FIG.

FIG. 3 is a block diagram showing an example of an information processing device in which a peripheral control device or a peripheral control LSI of the present invention is used,

FIG. 4 is a first timing chart for explaining the operation of the embodiment shown in FIG.

5 is a second timing chart for explaining the operation of the embodiment shown in FIG.

FIG. 6 is a schematic configuration diagram for explaining the principle of a second embodiment in which the present invention is applied to a SCSI system.

FIG. 7 is an SC which is the second embodiment of the present invention shown in FIG.
Schematic configuration diagram when the SI system is applied to a hard disk device,

8 is a circuit block diagram showing an example of the SCSI bus control circuit 701 of FIG.

9 is a circuit diagram showing an example of an ID recognition unit 825 in the SCSI bus control circuit shown in FIG.

10 is a partial circuit diagram of an example of the receiver 814 shown in FIG.

11 is a circuit diagram of an example of a receiver 812 shown in FIG.

12 is a schematic circuit diagram of an entire receiver 814 shown in FIG.

13 is a circuit diagram of an example of a sleep control circuit 826 shown in FIG.

FIG. 14 is a circuit diagram for explaining a termination resistance of a SCSI bus to which the present invention is applied;

FIG. 15 is a circuit diagram showing an example of a SCSI bus according to a third embodiment of the invention.

FIG. 16 is a block diagram showing an example of a SCSI bus control circuit according to a third embodiment of the present invention,

FIG. 17 is an S to which the second and third embodiments of the present invention are applied.
State transition diagram in CSI system,

FIG. 18 is an S to which the second and third embodiments of the present invention are applied.
Explanatory diagram for explaining a schematic sequence of a SCSI protocol in a CSI system,

FIG. 19 is an S to which the second and third embodiments of the present invention are applied.
Another explanatory diagram for explaining a schematic sequence of a SCSI protocol in a CSI system,

FIG. 20 is a schematic diagram showing an example of a conventional hard disk device using an AT bus.

[Explanation of symbols]

2 ... Low power consumption control circuit, 3 ... Address latch, 4 ... Address decoder, 6 ... Latch, 7 ... Gate, 8-10 ...
Register group, 11 to 13 ... I / O control circuit, 601 ... S
CSI bus, 602 ... SCSI controller, 603 ...
ID recognition unit, 604 ... Functional block other than ID recognition unit,
605 ... Sleep release signal.

─────────────────────────────────────────────────── ─── Continuation of the front page (72) Kunio Watanabe Inventor, Kunio Watanabe 292 Yoshida-cho, Totsuka-ku, Yokohama, Kanagawa Hitachi, Ltd. Microelectronics Equipment Development Laboratory (72) Shinichi Kojima 111 Nishiyote-cho, Takasaki-shi, Gunma Address, Hitachi, Ltd., Semiconductor Design and Development Center (72) Inventor, Koji Shida, 5-20-1, Kamimizuhonmachi, Kodaira-shi, Tokyo Hitachi, Ltd., Semiconductor Design and Development Center (56) Reference JP-A-3- 225516 (JP, A) (58) Fields surveyed (Int.Cl. ⁷ , DB name) G06F 13/10 G06F 1/00

Claims (4)

(57) [Claims] 1. A storage device connected to a bus connected to a processor , comprising: a storage medium; and a controller connected to the processor via the bus and controlling access from the processor. The controller writes write data to the storage medium.
Less processing or processing of read data from the storage medium
Access from the processor to perform at least one
First block for detecting the start of the access in response to the access
In response to the lock and the instruction of the first block,
Processing of write data to a storage medium and recovery from the storage medium
Second processing for performing at least one of processing
And the first block detects the start of the access.
The second block is crossed over to the second block.
A second block that is controlled to an activation mode in which a clock is supplied and is controlled to the activation mode.
Processing of write data to a storage medium and from the storage medium
At least one of the read data processing and the write data processing to and from the storage medium.
Process the read data and / or
Answer from the activation mode to the second block
The activation is performed by stopping the clock supply.
To the low power consumption mode, which consumes less power than the
A storage device characterized in that two blocks are controlled . 2. The storage device according to claim 1, wherein the controller including the first block and the second block is configured by one semiconductor integrated circuit. 3. Supplying the clock to the second block
Supply and / or stoppage shall be performed by the first block
The storage device according to claim 1, wherein the storage device is a storage device. 4. The second block is stored in the storage medium.
Write data processing and read data from the storage medium
The end signal indicating the end of at least one of the
The first block is transmitted to the first block, and the first block is transmitted from the second block.
In response to an end signal, the clock to the second block is
The storage device according to claim 3, wherein the supply of power is stopped.