JP3400605B2 - Processing unit for control - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a control processing device having a high-speed microcomputer, and more particularly to a control processing device which needs to be compatible with multiple types of vehicles, be easily mounted, and be inexpensive.

[0002]

2. Description of the Related Art Conventionally, in a control processing device used for an automobile, for example, in the case of engine control, if the number of cylinders of the engine and the configuration of attached sensors are different, the control device is optimized for each engine to be controlled. Microcomputers with various I / O configurations (timers, counters, number of analog input / output terminals, etc.) were selected and used. As a device of this kind, for example, Japanese Examined Patent Publication No. 3-40277 is described in the official gazette.

[0003]

In the conventional control processing apparatus as described above, depending on the type of engine, I / O
Microcomputers with different configurations are required. Therefore, there is a problem that standardization of the control device cannot be achieved in the case of producing a large amount of small quantities and the cost is increased.

The present invention has been made in view of the above problems, and an object thereof is to enable timer output processing of more than the number of built-in timers and to freely set output terminals. It is an object of the present invention to provide a control processing device capable of widely utilizing the timer output function and having an inexpensive configuration as a whole.

[0005]

SUMMARY OF THE INVENTION The above object is, constant frequency
Section for counting the number of pulses, and the counter section
A comparison data section for storing comparison data to be compared with
Output section and a comparison section that compares the comparison data with the counter section
And the output part that can specify the output value and the control that controls them
In the control processing device having a unit, the control unit is
When the matching condition of the comparison unit is satisfied, the output end of the output unit
The child and the output value are set, and the comparison data and the current
When the time difference is smaller than a predetermined time, the above
By adding a predetermined time to the current time
Set the operation time of the output value as new comparison data
It is achieved by a control processing device characterized in that

As a more preferable specific example of the present invention, the output signal of the output unit of the control processing device is a fuel injection signal, an ignition signal, or a PWM signal.

[0007]

In the control processing apparatus according to the present invention having the above-described configuration, the number of timer outputs and the output terminals can be flexibly changed by the program for realizing the virtual timer output. Therefore, it is possible to control from 4 cylinders to 12 cylinders or more cylinders by one type of control processing device.

[0008]

Embodiments of the present invention will be described below with reference to the drawings. In the drawings for explaining each of the following embodiments, corresponding members having the same function are designated by the same reference numerals, and overlapping description will be omitted.

First, an actuator control system according to an embodiment of the present invention will be described with reference to FIGS.

FIG. 1 is an example of a hardware configuration diagram of an actuator control system according to the present invention. The actuator 110 has two PWM (Pulse Width Modulation)
It is controlled by the signals PWM_a and PWM_b. The control processing device 1 includes a counter unit 16 that counts up in a constant cycle, a comparison data unit 14 that stores data to be compared with a count value, a comparison unit 15 that compares the count value and comparison data, and output terminals 1 to 1. The output unit 8 includes an output terminal up to the output terminal 8 and an output value that can be set, an output buffer 10 that stores the output value of the output unit 8 and output terminal data, and a control unit 2 that controls these.

Next, the outline of the processing software executed by the control unit 2 will be described. The control unit 2 has a response unit such as an interrupt response or a response by searching a match flag when the count value matches the comparison data. As a result, the control unit 2 can detect the match between the count value and the comparison data. At this time, the control unit 2 performs an output process in accordance with the output buffer 10, and then performs a process of determining which terminal should be activated or deactivated at what time. Next, according to this result, the output value and the output terminal are set in the output buffer 10 at the time to be output to the comparison data unit 14.

FIG. 2 is a time chart. PWM_
The period of the a signal is Tp_a, the duty is Td_a, and P
The cycle of the WM_b signal is Tp_b and the duty is Td_b.
Suppose A pulse having a constant cycle is input to the counter unit 16 and the count value increases at a constant slope. Here, by changing the data to be written to the comparison data section 14 as shown in the figure, the rising and falling timings of the two PWM signals can be obtained. At this timing, an appropriate output value and output terminal to the output section 8 can be obtained. If you set up two PW
An M signal can be output.

Therefore, the control unit 2 first outputs the output buffer 10 at the timing when the count value and the comparison data match.
The output value and the command of the output terminal are given to the output unit 8
Next, it is determined whether PWM_a is rising, PWM_a is falling, PWM_b is rising, or PWM_b is falling, and the following processing is performed. For example, in the process a, the output terminal 2 is activated according to the output buffer 10. Next, the time when the PWM_b pulse rises and the time when it falls are calculated. After that, a pulse process to be performed next is searched for, and since this is the process of raising PWM_a, the rise time is stored in the comparison data unit 14, and the output setting for raising the output terminal 1 is stored in the output buffer 10. . Also,
In process b, the output terminal 1 is activated according to the output buffer 10. Next, the time at which the PWM_a pulse rises and the time at which it falls are calculated. After that, the pulse processing to be performed next is searched, and here, since it is the processing for lowering PWM_b,
The fall time is stored in the comparison data section 14, and the output setting that causes the output terminal 2 to fall is stored in the output buffer 10. In process c, the output terminal 2 is pulled down according to the output buffer 10. After that, search for the next pulse processing to be performed,
Since the processing here is the fall of PWM_a, the fall time is stored in the comparison data section 14, and the output setting that causes the output terminal 1 to fall is stored in the output buffer 10. In process d, the output terminal 1 is turned off according to the output buffer 10. After that, a pulse process to be performed next is searched for, and since this is the process of raising PWM_b, the rise time is stored in the comparison data section 14, and the output setting for raising the output terminal 2 is stored in the output buffer 10. .

However, it is conceivable that the processing may be delayed if the change timings of the respective PWM signals become close in time. In this case, for example, as shown in FIG. 3, when Terr occurs at the rising timing, Terr is added at the next fall time, and when Terr occurs at the falling timing, Terr is added at the next rise time. By doing so, the average duty can be corrected to be constant.

That is, in this case, the cycle of the PWM pulse signal changes randomly, but the average value of the n PWM pulses becomes equal to the command.

FIG. 4 is a flowchart. Processing 50
At 0, the data in the output buffer created in the processing 506 described later is transferred to the output unit 8. Here, the output unit 8 is assumed to be an output port unit of a general microcomputer, and the transferred data can be output to the terminal as it is. Therefore, next, in process 501, it is determined whether or not the current process is caused by the rise or fall of PWM_a. If PW
If it is caused by the rise or fall of M_a, the time (Ton_a) at which PWM_a is turned on next by process 502.
) And the time to turn off (Toff_a). Similarly, in process 504, it is determined whether or not the process this time is caused by the rise or fall of PWM_b. If it occurs due to the rise or fall of PWM_b, the next time PWM_b turns on (Ton_b) and the time it turns off (Toff_b) are calculated by processing 505. Next, in process 506, the calculated Ton_a, Toff_a, Ton_b, Toff_b that is closest to the current time is searched and stored in the comparison data unit 14. At this time, when Ton_a is selected, the bit corresponding to the PWM_a terminal (output terminal 1) is set in the output buffer bits, and when Toff_a is selected, the PWM_a terminal (output Clear the bit corresponding to pin 1). Similarly, Ton_b
If is selected, the PWM_
Set the bit corresponding to the b terminal (output terminal 2), and
If ff_b is selected, P among the bits of the output buffer
The bit corresponding to the WM_b terminal (output terminal 2) is cleared. However, bits that are not related to ON / OFF must retain the previous state. Next, in process 507,
Judge whether the difference between the comparison data and the current time is smaller than Tmin. If it is smaller, it is determined that the comparison data setting process is not in time, and the next process is performed. First, in process 508, it is determined whether the process of the time stored in the comparison data portion is a start-up or a fall. If it is startup, process 51
The start time (Ton_x) is delayed by 0 to the processable time (current time + Tmin), and the delay time (Terr) due to this
Is added to the fall time (Toff_x), the process returns to step 506 and the search is performed again. If it is a fall, processing 509
Delays the fall time (Toff_x) until it can be processed (current time + Tmin), and the delay time (Terr)
Is added to the startup time (Ton_x), the process returns to the processing 506 and the search is performed again.

However, in the above embodiment, the output section 8 has been described assuming output port means of a general microcomputer, but as a circuit of the more optimal output section 8, FIG. 5 can be cited. The latch circuit 38 receives a chip select (CS) signal obtained by decoding the address signal by the decoder 34 and a data strobe (D) indicating that the data is valid.
S) The data of the data bus is taken in at the timing of the signal processed by the AND gate 36. Similarly, in the latch circuit 39, the timing of the chip select (CS) signal obtained by decoding the address signal by the decoder 35 and the signal obtained by processing the data strobe (DS) signal indicating that the data is valid by the AND gate 37 Take in the data of the data bus with. Also, JK flip-flops 40 to 47
Operates at the timing when the comparison unit 15 detects a match. FIG. 6 is a truth table of the JK flip-flops 40 to 47. If the output Q is desired to be 1, the input J (data of the latch circuit 38) is set to 1 and the input K (data of the latch circuit 39) is set to 0, and the comparison unit 15 waits for a match. If the output Q is desired to be 0, the input J (data of the latch circuit 38) is set to 0 and the input K (data of the latch circuit 39) is set to 1, and the comparison unit 15 waits for a match. If it is not desired to change the output Q, the input J (data of the latch circuit 38) input K
(Data of the latch circuit 39) may be set to 0. Therefore, the process of holding the bit not related to ON / OFF in the previous state performed in the process 506 is as simple as setting both the input J (data of the latch circuit 38) and the input K (data of the latch circuit 39) to 0. Since it can be realized by processing, the processing load on the control unit 2 can be reduced.

FIG. 7 shows an example of a concrete circuit of the latch circuits 38 and 39. D type flip-flop 48-55
The input D appears at the output Q at the rising timing of the clock (CK) signal. The D flip-flop 48 is for determining ON / OFF of the output terminal 1.
The D flip-flop 49 determines ON / OFF of the output terminal 2. Similarly, the output terminal 8 of the D flip-flop 55 is also supported. Therefore, the designation of the output terminal can be determined by which D flip-flop is to store the data.

According to this embodiment, the virtual PWM shown in FIG.
By increasing the processing variables Ton_x and Toff_x and the processing related thereto by the required amount, it is possible to output the PWM output to the required number of terminals with the same hardware, and in high-mix low-volume production. Even in some cases, the hardware can be shared, so that the production cost can be reduced. Not only the PWM pulse, but also the drive pulse of the step motor, the fuel injection signal of the automobile engine,
The ignition signal and the like can be considered as a set of PWM signals having the same carrier frequency, and can be similarly realized. Especially, if these are divided into groups of startups or shutdowns,
The processing of each group can avoid the delay of the pulse output due to the processing time as in the other embodiments described below.

Next, as another more specific embodiment, 1
A control system for controlling an automobile engine and an automatic transmission using a chip microcomputer will be described with reference to FIGS.

FIG. 8 is a hardware block diagram of the engine and automatic transmission control system according to the present invention. First, a method of controlling the engine will be described. As an engine applied to the automobile engine control system of this illustrated example, 4
The cylinder 4-cycle engine 101 will be described below as an example.
As sensors, a TVO sensor 104 for detecting the throttle opening and an AFM sensor 105 for detecting the intake air amount.
An O ₂ sensor 108 for detecting the amount of oxygen contained in the exhaust gas, a REF sensor 103 for generating a pulse for every 180 ° crank angle of the engine 101, and a POS sensor 102 for generating a pulse for every 2 ° crank angle. Is provided. The pulse width of the pulse signal of the REF sensor 103 differs for each cylinder, and the cylinder discrimination can be performed using this pulse width information.

Further, as a mechanism for controlling the engine 101, there are an injector INJ 106 for injecting fuel and an ignition IGN 107 for igniting a mixture of air and fuel. Injector INJ and ignition IGN
Are provided for each of the other cylinders, but the same operation is performed, and therefore the description thereof is omitted here. The catalyst 109 purifies exhaust gas. A one-chip microcomputer 1 that controls the engine 101 includes a CPU 2 that performs control calculation processing, an interrupt controller 3, and an A / D conversion unit 4 that converts an analog signal into a digital signal.
A ROM 9 for storing a control program and a virtual OCR program for virtually expanding the timer output, a RAM 10 for temporarily storing data, a timer 6 for generating a constant cycle interrupt, and a free running for inputting / outputting a pulse signal. It comprises a timer 7 and port means 5 and 8 for inputting and outputting digital signals.

Next, the hardware related to the automatic transmission 110 will be described. The automatic transmission 110 has a speed ratio of 4
It has a lock-up function that can be switched to different types and that fastens the torque converter. From the vehicle speed sensor 111, a pulse signal having a frequency proportional to the vehicle speed is obtained. At the rising edge of this pulse signal, the free-run counter FRC_a
The value of 16 is input capture register ICR_b2
It is taken into 0 and the CPU 2 converts it into the vehicle speed based on this information. In addition, the shift signal is output from the digital port output means 8 to control the hydraulic pressure for shifting using the solenoid valve 112. The lockup control is performed by the PWM signal (L / Uduty). The PWM signal (PLduty) is also used to control the hydraulic pressure that controls the entire transmission.

FIG. 9 shows the free running counter 7
2 shows a detailed block diagram of FIG. The FRC_a16 is counted up by the internal clock CLK at a constant cycle of, for example, about 3.2 μs. Comparator_a15, Comparator_b1
7, comparator_c21, comparator_d23, comparator_e25
Are output compare registers OCR_a, respectively.
14, OCR_b18, OCR_c22, OCR_d2
4, when the data of OCR_e26 and the data of FRC_a16 become equal, the interrupt signals INT1, INT2, INT5, INT
6 and INT7 are generated. The input capture register ICR_a19 captures the value of FRC_a16 at the rising edge of the pulse signal from the REF sensor 103 and generates an interrupt signal INT3. The input capture register ICR_b20 is a vehicle speed sensor 111.
At the rising edge of the pulse signal by FRC_a16
Value is taken in and an interrupt signal INT4 is generated. The counter CNT_a 29 counts up at the rising edge of the pulse signal from the POS sensor 102. The comparator_f28, the comparator_g30, and the comparator_h32 are output compare registers OCR_f27 and OCR, respectively.
Data of CR_g31 and OCR_h33 and CNT_a2
When the data of 9 become equal, the interrupt signals INT8, IN
T9 and INT10 are generated.

The following processing is performed for each interrupt request. First, in INT1, the injector (INJ)
Pulse rise processing, injector (IN
J) Pulse fall processing, engine speed Ne measurement processing at INT3, vehicle speed measurement processing at INT4, INT
5, offset 1 processing, INT6 PWM pulse rising processing, INT7 PWM pulse falling processing,
The INT8 performs an ignition (IGN) pulse rising process, the INT9 performs an ignition (IGN) pulse falling process, and the INT10 performs an offset 2 process.
Since the configuration of the output compare register (OCR) for the rise and fall processes of the pulse signal is constant regardless of the number of output pulses, the number of cylinders of the engine is 8
Alternatively, even if the number is increased to 12, it can be realized by the same hardware.

With the above description of the hardware, the control method of the engine and the automatic transmission will be described.

FIG. 10 shows a control block diagram of the engine and the automatic transmission. First, the control block 2 of the automatic transmission
16 will be described. Block 200 is a vehicle speed sensor 9
The vehicle speed information is detected by measuring the pulse signal of the vehicle in a cycle or counting the number of pulses within a certain time.
Convert to. The throttle opening signal is converted into an angle signal by the block 201. From this information, block 202 determines the gear position. This is performed according to the shift schedule shown in FIG. That is, a fixed cycle (for example, 40 m
In s), the current vehicle speed VSP and the throttle opening TVO are applied to this shift schedule, and the gear position is shifted to the gear position indicated by the corresponding region. However, upshift and downshift have separate schedule lines to have hysteresis to prevent frequent shifts. Further, by reducing the engine output during gear shifting, gear shifting shock can be reduced. Therefore, in block 204, the gear position command changes during shifting, and this is detected, and an output torque down command is output to the engine control. Block 203 sets a value in the digital output port means 8 to output the obtained gear position. This is output based on the relationship between the gear position and the shift signal outputs SOLA and SOLB shown in FIG. Although not shown, the automatic transmission 110 has a structure that shifts to each gear position by this shift signal. Further, in block 212, the condition for locking up the torque converter is determined. This searches the map shown in FIG. 14 for the lockup degree (L / U_duty) from the vehicle speed VSP and the throttle opening TVO. Block 21
In 3, the processing for converting the retrieved LU_duty into a PWM signal is performed. Further, in block 214, the hydraulic pressure (line pressure) for controlling the automatic transmission is calculated. This searches the line pressure (PL_duty) from the throttle opening TVO using the map shown in FIG. In block 215, a process of converting the retrieved PL_duty into a PWM signal is performed.

Flowcharts of the above automatic transmission control are shown in FIGS. In the case of an automatic transmission, since the inertia of the entire vehicle is very large, the control response speed does not need to be particularly high. Therefore, the whole process is started at a relatively slow timing (40 ms). Therefore, the calculation load on the CPU is relatively small.

First, FIG. 15 is a flowchart of a background processing program which operates when the one-chip microcomputer 1 is reset. First, mask processing 300 for prohibiting interrupts is performed, and initialization processing 301 such as initial setting of the RAM 10 and peripheral function registers is performed. After that, the interrupt mask canceling process 302 for canceling the prohibition of the interrupt is performed.

Next, a task for generating a start request interrupt at various timings will be described in detail.

First, FIG. 16 shows a flowchart of vehicle speed detection. This process starts at the rising edge of the vehicle speed pulse signal VSP. First, in process 303, the value of the input capture register ICR_b20 is loaded into ICRNEW.
Next, in process 304, ICRNEW to ICROLD (ICRNE one cycle before
W) is subtracted to calculate the period PERIOD between the rising edges of the vehicle speed pulse signal. Process 305 stores the current ICRNEW in ICROLD for calculation of the next cycle. In process 306, the vehicle speed conversion count L is divided by the vehicle speed pulse period PERIOD to obtain the vehicle speed VSP.

FIG. 17 shows a process performed in a 40 ms cycle. First, in process 307, the throttle opening sensor 104
Is taken in by the A / D converter 4. Further, in process 308, the line pressure control map shown in FIG. 13 is searched to determine the line pressure (PL_duty). Similarly, in the process 309, the lock-up control map shown in FIG. 14 is searched to determine the lock-up degree (L / U_duty). In process 310, the shift schedule map shown in FIG. 11 is searched to determine the gear position. Process 31
In 1, the shift is detected and a torque reduction command is generated to the engine. In process 312, the shift signal shown in FIG. 12 is output to the port output means 8 so that the determined gear position is reached.

Next, the details of the generation processing of the PWM signal for controlling the line pressure (PL_duty) and the lockup pressure (L / U_duty) will be described.

FIG. 18 is a data table provided for processing so that the output compare registers OCR are virtually many. This is secured in the RAM 10. U Virtual OCR_n is the time to start the nth pulse, U output pattern_n is the terminal to be started, UVALID
In _n, a flag indicating whether or not the n-th time data to be started and the data of the output pattern are valid is stored. Similarly, the D virtual OCR_n is the time at which the nth pulse is desired to fall, the D output pattern_n is the terminal at which it is desired to be fallen, and the DVALID_n is the nth time data and output pattern data at which it is desired to be fallen. The flag indicating whether or not there is stored is stored. Since two PWM signals are output using this data table, OCR_d24 is used for rising the PWM signal and OCR_e is used for falling.
Process using interrupt by 26.

FIG. 19 shows a process for raising the PWM signal, which is started by the interrupt INT6 of the OCR_d24. First, in process 313, the logical sum of the output port 8 and the rising output pattern is calculated for each bit. As a result, 1 is set to the bit to be started. The next output pattern and time are set in the subsequent processing. In process 314, the output U virtual O
Clear the UVALID flag corresponding to CR to remove it from the search target. Next, in process 315, it is determined whether or not this interrupt process is generated for the rise of the line pressure PWM signal. If so, in process 316, U virtual O
The rising time of the PWM signal of the next line pressure is set in CR_1. Similarly, in process 317, D virtual OCR_1
Is set to the time when the next PWM signal of line pressure falls. Note that Tp_PL shown here is the period of the line pressure PWM signal, and Td_PL is the on-time of the line pressure PWM signal. Next, in process 318, a bit pattern in which the bit corresponding to the PWM signal of the line pressure of the U output pattern_1 is 1 and the other bits are 0 is set. Similarly, the D output pattern_1 sets a bit pattern in which the bit corresponding to the line pressure PWM signal is 0 and the other bits are 1. Next, h'FF is set to UVALID_1 and DVALID_1 so that the data set in the process 320 becomes valid. Regarding the processes 321 to 326, the same process is performed for the lockup PWM signal. Next, process 3
At 27, a startup schedule process is performed. This is UVALID
In the valid U virtual OCR_n where _n is h'FF, the value of the U virtual OCR_n closest to the current time is set to OCR_d24.
And the U output pattern_n selected in the startup output pattern buffer is stored. Next, processing 328
Then, preparation is made for detecting that the processing 329 has been activated multiple times. In the process 329, the same schedule process is performed for the shutdown. In process 330, it is detected that the shutdown schedule processes of process 329 have been activated in a multiple manner, and when they are activated in a multiple manner, the shutdown schedule process of process 329 is performed again.

FIG. 20 shows a process performed for falling the PWM signal, which is activated by the interrupt INT7 of the OCR_e26. First, in process 331, the logical product of the output port 8 and the rising output pattern is obtained for each bit. As a result, the bit to be lowered becomes 0. Next, the D virtual O output in processing 314
Clear the DVALID flag corresponding to CR to remove it from the search target. In process 329, a fall schedule process is performed to search for the next fall. In process 332, a flag indicating that this process 329 has been interrupted multiple times is set.

Next, details of the startup schedule process 327 will be described. Although this processing is performed by the CPU 2, it is assumed that the CPU 2 has 16 general-purpose registers R0 to R15. First, in process 333, initialization is performed to prepare the whole. In process 334, the current time is stored in the register R10. Next, in process 335, it is determined whether the UVALID flag is valid, and if it is valid,
In process 336, the difference between the current time and the U virtual OCR_n is calculated. In process 337, it is determined whether the difference generated in process 336 is smaller than the register R11. The content of the register R11 is determined in the process 341, and when the route is followed to the process 342, the U virtual OCR_n becomes closest to the current time. Therefore, in the process 342, the U virtual OCR_n is stored in the register R14, and the U output pattern_n is stored in the register R5 in the process 343 to prepare for output. When proceeding to processing 339, U virtual OCR_n
Is not close to or equal to the current time. Therefore, in the process 339, it is determined whether the U virtual OCR_n is equal to the closest one to the current time, and if they are equal, the U output pattern_n is merged into R5 in the process 340. In process 334, n is incremented and process 345
Determines whether n is 2. This is because there are two PWM signals, and increasing this value can cope with an increase in the number of PWM signal outputs. In process 346, the value of the register R5 prepared in process 343 is stored in the startup output pattern buffer. Similarly, process 34
In 7, the value of the register R14 prepared in the process 342 is stored in the OCR_d24, and the next startup preparation is completed.

FIG. 22 is a flowchart of the shutdown schedule processing 329. Since the processing contents are almost the same as those of the startup schedule processing 327, the description thereof will be omitted.

In this embodiment, the output timing delay compensation shown in FIG. 3 is omitted for the sake of clarity.

This completes the description of the control method for the automatic transmission 110. Next, the control method for the engine 101 will be described. First, the control block 217 of the engine shown in FIG. 10 will be described. An engine speed Ne is calculated by measuring a pulse cycle by a block 208 using a pulse signal synchronized with the engine rotation obtained by the REF sensor 103. Further, the signal from the air flow rate sensor 105 is subjected to coefficient conversion processing in block 205 to calculate the air inflow amount Qa.
Using these values, the basic fuel injection amount TI is calculated in block 206 according to the following equation (1).

[0041]

[Equation 1]

However, K: correction coefficient Ts: invalid pulse width, and the fuel injection timing TITM can be determined from the engine speed Ne, and is specifically obtained by a table search or the like. Further, when the throttle opening obtained by the block 201 is a certain value or more,
Correction such as increasing the amount of fuel may be performed. Further, the fuel injection amount TI may be controlled to detect whether or not the stoichiometric air-fuel ratio is the stoichiometric air-fuel ratio from the O ₂ sensor signal obtained from the block 209 and to perform feedback control such as proportional control and integral control. The basic fuel injection amount TI and the fuel injection timing TITM obtained in this way are output as an injection pulse by the block 207.

Next, the generation of the ignition signal will be described.
Intake air amount obtained in block 205 and block 208
The ignition signal pulse width DWELL and the ignition timing ADV are determined in block 210 from the engine speed Ne obtained from the above. This is obtained by searching a preset data table. The ignition signal pulse width DWELL and the ignition timing ADV are stored in the block 211.
Is output as an ignition pulse.

FIG. 23 shows a time chart of engine control. In order from the top, the signal waveform of the POS sensor 102, the signal waveform of the REF sensor 103, the value of the free running counter FRC_a16, and the counter CNT_a that counts up at the rising edge of the POS sensor signal.
29, the output waveform of the fuel injection signal INJ # 1 of the first cylinder, the output waveform of the fuel injection signal INJ # 2 of the second cylinder, the output waveform of the fuel injection signal INJ # 3 of the third cylinder, the output waveform of the fourth cylinder Output waveform of fuel injection signal INJ # 4, output waveform of ignition signal IGN # 1 of first cylinder, ignition signal IGN of second cylinder
# 2 output waveform, third cylinder ignition signal IGN # 3 output waveform, fourth cylinder ignition signal IGN # 4 output waveform, 180d
eg processing timing, OCR_a processing timing, O
The timing of CR_b processing, the timing of OCR_f processing, and the timing of OCR_g processing are shown.

The fuel injection signal INJ # 1 for the first cylinder
The rising timing of the fuel injection pulse signal from the fuel injection signal INJ # 4 to the fourth cylinder is generated in the REF signal cycle (engine rotation angle cycle of 180 degrees). Therefore, these start-up timings must be separated by a certain time interval (for example, 4
Engine speed 8000 rpm with a 4-cylinder cylinder engine
In the case of, it has about 3.75 ms). Therefore, if the OCR is updated at this time, the startup timing can be controlled by one OCR. Also, this condition is
The same applies to the falling timing of the fuel injection pulse, the rising timing of the ignition pulse signal from the ignition signal IGN # 1 of the first cylinder to the ignition signal IGN # 4 of the fourth cylinder, and the falling timing of the ignition pulse signal. . Therefore, by having one OCR for each startup group and each shutdown group, the startup or shutdown timing of each can be controlled. Since this is a condition that holds even if the number of cylinders of the engine changes, it is not necessary to change the number of OCRs even if the number of cylinders of the engine changes.

Next, the outline of each processing will be described. 18
In the 0 deg process (r1), the engine speed Ne is calculated, the basic fuel injection amount TI and the fuel injection timing TITM are calculated, the ignition timing ADV, the energization angle DWELL are calculated, and the time at which fuel injection is started (offset 1) O
In CR_c22, the angle (offset 2) at which ignition is started is set in OCR_h33. Offset 1 processing (o1)
Then, the output times (f1) and (f2) of the fuel injection pulse and the output pattern are generated, and the output time at which the rising occurs first is set to OCR_a14 and the rising output pattern is set to the rising output pattern buffer. Further, the output time at which the fall occurs first is set to OCR_b18, and the fall output pattern is set to the fall output pattern buffer. In the offset 2 process (s1), the ignition pulse output angle (c
1) and (c2) are generated, and the output angle at which the rising occurs first is set in OCR_f27, and the rising output pattern is set in the rising output pattern buffer. Also, the output angle at which the fall occurs first is OCR_g3.
The fall output pattern is set to 1 in the fall output pattern buffer.

These OCR_a14, OCR_b18,
The following operation is performed by setting the OCR_f27 and OCR_g31. First, in the OCR_a process (a1), the rise and fall times of the fuel injection signal are set. In the OCR_b process (b1), the fall of the fuel injection signal. In the OCR_f process (f1), the rise and fall angles of the ignition signal are set.
In the OCR_g process (g1), the ignition signal is lowered.
In the 180 deg processing (r2), (r3), (r4), the above 18
0 deg processing (r1) and offset 1 processing (o2), (o
3) and (o4), the offset 1 process (o1) and
In the offset 2 processing (s2), (s3), (s4), the offset 2 processing (s1) and the OCR_a processing (a
2), (a3), (a4), the OCR_a process (a
1) and OCR_b processes (b2), (b3), and (b4), the OCR_b process (b1) and the OCR_f processes (f2), (f3), and (f4) are the OCR_f processes.
In (f1) and OCR_g processing (g2), (g3), and (g4), the same processing as the OCR_g processing (g1) is performed.

Next, the engine control flowchart according to the present invention will be described with reference to FIGS.

FIG. 24 is a flow chart of a task for which an activation request is generated for each crank angle of 180 deg. Process 362
Then, the pulse cycle of the REF signal is obtained using the value of ICR_a19 in which the time of the rising timing of the REF signal is stored, and the engine speed is calculated. In process 363, the basic fuel injection amount TI and the fuel injection timing TITM are calculated from the engine speed, the intake air amount, and the like. In process 364, the ignition angle ADV and the energization angle DWELL are calculated from the engine speed and the intake air amount. Process 365
Then, one revolution of the crank angle is detected and a 1rev start request is generated. In process 366, the fuel injection time (offset 1)
Is set to OCR_c22, and the energization start angle (offset 2) is set to OCR_h33.

FIG. 25 shows 10 m generated by the timer 6.
It is a flowchart of the task which an activation request generate | occur | produces in s period. Here, the AFM sensor 10 is processed by the process 367.
The signal is taken in from 5 and intake air amount data is acquired.

FIG. 26 is a flow chart of a task for which an activation request is generated in a cycle of 1 rev. In process 368, O
₂ The signal of the sensor 108 is captured. Process 36
In No. 9, the fuel injection time is increased or decreased based on the captured O ₂ sensor signal, and the air-fuel ratio is controlled to be 14.7.

Next, a detailed description will be given of the flow chart of the portion related to the output compare register OCR processing in the fuel injection and ignition processing. In the present embodiment, in order to easily respond to changes in the number of cylinders, the virtualization timer data storage format shown in FIG. 18, the startup schedule process 327 shown in FIG. 21, and the shutdown schedule process shown in FIG. 329 is used to take countermeasures.

FIG. 27 is a flowchart of the offset 1 process. The process 370 sets the value of the current time + ΔT to the U virtual OCR_n. ΔT is a very small value, and after the ΔT time of this process, the injector IN of the n-cylinder IN
The purpose is to raise the J signal. In process 371, a bit pattern in which the bit corresponding to the injector n in the output pattern_n is 1 and the other bits are 0 is set. Further, in process 372, process 370 and process 371.
Set h'FF in UVALID_n so that the data set in step 3 becomes valid. After that, the startup schedule process of the process 327 is performed, and the OCR_a14 is set. In processing 373 to processing 377, processing similar to that at the time of startup is performed so that the injector n is turned off at the injection end time.

FIG. 28 is a flow chart of the processing generated by the interrupt of OCR_a14. In step 378, the logical sum of the output port 5 and the rising output pattern buffer is calculated for each bit. As a result, the bit to be activated becomes 1.
In steps 379 to 384, the UVALID flag corresponding to the output U virtual OCR is cleared to remove it from the search target.

FIG. 29 is a flow chart of the processing generated by the interruption of OCR_b18. In step 385, the logical product of the output port 5 and the falling output pattern buffer is calculated for each bit. As a result, the bit to be lowered becomes 0.
In steps 386 to 391, the DVALID flag corresponding to the output D virtual OCR is cleared to remove it from the search target. Next, the fall schedule process of process 329 is performed, and the flag notifying multiple interrupts is set in process 392.

30 to 32 are flowcharts for the ignition pulse generation, the description thereof is omitted because the processing is almost the same as the fuel injection.

By the above processing, the fuel injection signal and the ignition signal of the engine can be output by the pair of two OCRs for start-up and fall, and the hardware configuration of the one-chip microcomputer can be simplified. , And virtual OCR
By changing the program, it becomes possible to control with the same specification microcomputer regardless of the number of cylinders of the engine.

The virtual OCR update process and the OC
Since the input clock cycle of the free running counter 16 is 3.2 μs in the Rn update processing, the processing time is preferably 3.2 μs or less. For example, since the virtual OCR updating process requires about 64 processing steps, it is desirable to use a microcomputer having a clock frequency of 20 MHz or higher.

[0059]

As can be understood from the above description, according to the present invention, a large number of pulse output processes can be performed, and further, the pulse output peripheral functions can be freely and widely used, and the whole system can be used. It can have an inexpensive structure and can also be used as a control processing device suitable for vehicle integrated control and the like in which a lot of pulse signals are output.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a control device having flexible output functions and terminals.

FIG. 2 is a time chart of PWM output.

FIG. 3 Measures against output timing deviation.

FIG. 4 is a flowchart of virtual PWM processing.

FIG. 5 is a block diagram of an output circuit.

[6] truth Diagram Table.

FIG. 7 is a latch circuit.

FIG. 8 is a hardware configuration diagram of an engine and an automatic transmission control system.

FIG. 9 is a block diagram of a free running timer.

FIG. 10 is a control block diagram of an engine and an automatic transmission.

FIG. 11 is a shift schedule map.

FIG. 12 shows the relationship between gear position and shift signal output.

FIG. 13 is a line pressure control map.

FIG. 14 is a lockup control map.

FIG. 15 is a flowchart of background processing.

FIG. 16 is a flowchart of vehicle speed measurement processing.

FIG. 17 is a flowchart of 40 ms processing.

FIG. 18 is a virtual timer data storage format.

FIG. 19 is a flowchart of OCR_d interrupt processing.

FIG. 20 is a flowchart of OCR_e interrupt processing.

FIG. 21 is a flowchart of startup schedule processing.

FIG. 22 is a flowchart of a shutdown schedule process.

FIG. 23 is a time chart of engine control.

FIG. 24 is a flowchart of 180 deg processing.

FIG. 25 is a flowchart of 10 ms processing.

FIG. 26 is a flowchart of 1rev processing.

FIG. 27 is a flowchart of offset 1 processing.

FIG. 28 is a flowchart of OCR_a interrupt processing.

FIG. 29 is a flowchart of OCR_b interrupt processing.

FIG. 30 is a flowchart of offset 2 processing.

FIG. 31 is a flowchart of OCR_f interrupt processing.

FIG. 32 is a flowchart of OCR_g interrupt processing.

[Explanation of symbols]

1 ... 1-chip microcomputer, 2 ... control unit, 6 ...
Free-running timer means, 8 ... Output unit, 10 ... Output buffer, 14 ... Comparison data unit, 15 ... Comparison unit, 16 ...
Counter section, 38, 39 ... Latch circuit, 101 ... Engine, 110 ... Actuator, ICR ... Input capture register, FRC ... Free running counter, OCR ... Output compare register, CNT ...
Pulse counter, TVO ... Throttle opening, AFM ... Air flow sensor, INJ ... Fuel injection signal, IGN ... Ignition signal, REF ... 180 deg pulse signal, POS ... 2 deg pulse signal.

─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Mitsuru Watabe 2520 Takaba, Hitachinaka City, Ibaraki Prefecture Hitachi, Ltd. Automotive Equipment Division, Hitachi, Ltd. (72) Tetsuya Ichihashi 2477 Kashima Yatsu Kashima Yatsu, Hitachinaka City, Ibaraki Prefecture 3 Inside Hitachi Automotive Engineering Co., Ltd. (72) Inventor Shoji Sasaki 2520, Takaba, Hitachinaka City, Ibaraki Prefecture Hitachi, Ltd. Automotive Equipment Division (56) Reference JP 62-151969 (JP, A) Japanese Patent Laid-Open No. 5-53417 (JP, A) Japanese Patent Laid-Open No. 3-161883 (JP, A) Japanese Patent Laid-Open No. 5-101196 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) G05B 19 / 05 G06F 15/78 510

Claims (4)

(57) [Claims] 1. A counter section for counting pulses of a constant frequency, a comparison data section for storing comparison data for comparison with the counter section, a comparison section for comparing the counter section with comparison data, an output terminal and an output value. In the control processing device having an output unit capable of designating and a control unit for controlling them, the control unit, when the matching condition of the comparison unit is satisfied,
While setting the output terminal and output value of the output section ,
The difference between the comparison data and the current time is from a predetermined time
When it is small, the predetermined time is set to the current time.
And output value as new comparison data
Control device characterized by setting the operating time of
Place 2. The control processing device according to claim 1, wherein the output signal of the output unit is at least one PW.
A processing device for control, which is an M pulse signal. 3. The control processing apparatus according to claim 1, wherein the output signal of the output unit is a fuel injection pulse signal of at least one automobile engine. 4. The control processing device according to claim 1, wherein the output signal of the output section is an ignition pulse signal of at least one automobile engine.