JP3395206B2 - Automatic equalizer - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an automatic equalizer, and more particularly to an automatic equalizer in which a unit frame is constituted by a plurality of time slots assigned to different mobile stations. The present invention relates to an automatic equalizer suitable for use in a digital mobile communication system that performs transmission by adding a unique synchronization pattern signal for each time slot. 2. Description of the Related Art In the United States, Europe and Japan, digitization of a mobile telephone system, which is a kind of mobile communication system, is being promoted. In this digital car telephone system, a time division multiplexing process (TDMA: Time Division)
Multiple Access) method. In the United States, adoption of the TIA system, which is a type of the TDMA system, has been decided. In this TIA system, a communication channel from a base station to a mobile station (vehicle) has a frame configuration as shown in FIG. That is, a 1944-bit unit frame is formed by six time slots each consisting of 324 bits, which is 40 msec. As shown in FIG. 5, the content of one time slot is composed of 28-bit synchronization (SYNC) pattern data, 296-bit digital data and control data. [0004] In this car telephone system, a high-rise building or the like may be interposed between a mobile station moving at a high speed and a base station. easily influenced. The influence of the multipath causes intersymbol interference, interchannel interference, and the like, so that the transmission characteristics between the base station and the mobile station are significantly degraded, and it becomes difficult to receive with little transmission error.
In addition, the equivalent transmission characteristics change every moment. [0005] In such a mobile communication system, it is essential to use an equalizer in order to realize reception with less transmission errors. Further, it is necessary to determine the coefficients of the filter constituting the equalizer with high accuracy and high speed, and it is desired to realize the filter with the simplest possible hardware or with a small amount of calculation. The present invention has been made in view of the above points, and provides an automatic equalizer capable of accurately and quickly determining a filter coefficient of an equalizer with a small amount of calculation. The purpose is to: The automatic equalizer according to the present invention forms a unit frame by a plurality of time slots assigned to different mobile stations, and a unique synchronization is provided for each time slot. In a digital mobile communication system that performs transmission by adding a pattern signal, an automatic equalizer configured to determine a filter coefficient of an equalizer using the received synchronization pattern signal. synchronization pattern signal of a first time slot assigned Te and after one frame of the first time slot own
Synchronization pattern detection means for detecting a synchronization pattern signal of a second time slot allocated to the station; and a first pattern corresponding to the synchronization pattern signal of the first time slot.
Deciding means for deciding the filter coefficient of the second time slot and the second filter coefficient corresponding to the synchronization pattern signal of the second time slot, and the first time by the linear interpolation using the first filter coefficient and the second filter coefficient. And a coefficient interpolation means for setting a filter coefficient for data in the slot. The filter coefficient in the first time slot allocated to the own station and this first time slot
And the filter coefficient in the second time slot allocated to the own station one frame later than the first time slot, and the filter coefficient for the data in the first time slot is reduced to a small amount of calculation by linear interpolation of both filter coefficients. And at high speed with high accuracy, and further adaptively controls the filter coefficient for each symbol of data. Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of the automatic equalizer according to the present invention. 1, the PSK-modulated IF signal is supplied to a demodulation circuit 1 having a configuration as shown in FIG. 2 and demodulated. 2, the IF signal is supplied to first and second synchronous detectors 11 and 12, and a carrier reproducing unit 13, respectively. In the carrier reproducing unit 13,
A carrier for signal demodulation is generated. This carrier is directly supplied to the first synchronous detector 11 and is supplied to the second synchronous detector 12 via the π / 2 shifter 14. Thus, the first synchronous detector 11 functions as an I-axis synchronous detector, and the second synchronous detector 12 functions as a Q-axis synchronous detector. The demodulated output of the demodulation circuit 1 is supplied to the equalization filter 3 after being delayed in the memory 2 by a period corresponding to, for example, one time slot. As the equalizing filter 3, a filter composed of a transversal filter is generally used. FIG. 3 shows an example of the specific configuration. In FIG. 3, an equalizing filter 3 is constituted by four transversal filters 31 to 34 and two adders 35 and 36.
The I-axis detection output x _i of the first synchronous detector 11 is supplied to the transversal filters 31 and 32, and the Q-axis detection output y _i of the second synchronous detector 12 is supplied to the transversal filters 33 and 34, respectively. You. The outputs of the transversal filters 31 and 33 are added by an adder 35, and the outputs of the transversal filters 32 and 34 are added by an adder 36. As a result, the I-channel equalized output signal _Ii is obtained as the output of the adder 35, and the Q-channel equalized output signal Q
_i is obtained. Referring again to FIG. 1, the equalized output signals I _i , Q _{i of the} I and Q channels output from the equalizing filter 3.
Are supplied to _1/0 determiners 4 _I and 4 _Q , respectively, and it is determined whether the level is a logical level “1” or “0”. Then, the parallel data, which are the judgment outputs of the 1/0 judgment units 4 _I and 4 _Q , are converted into serial data by a parallel / serial conversion circuit (not shown) and output. As described in connection with the time slot configuration in FIG. 5, synchronous (SYNC) pattern data having a known pattern is added to the beginning of each time slot and transmitted. In the case of the TIA scheme, since the π / 4 shift DQPSK modulation scheme is adopted, 28 bits of the synchronization pattern data are received as data having a length of 14 symbols. In the DQPSK system,
Since the I-channel signal and the Q-channel signal are transmitted and received, interference between channels (crosstalk) in addition to intersymbol interference in each channel cannot be ignored. [0013] Therefore, in the present embodiment, in order to prevent crosstalk between intersymbol interference and channel definitive for each channel, as described above, constitutes a equalizing filter 3 in the transversal filter 31 to 34, It is assumed that the tap coefficients of the transversal filters 31 to 34, that is, the filter coefficients of the equalization filter 3, are set according to the reception status grasped based on the synchronization pattern data. That is, I-axis and Q-axis detection outputs x _i , y _i
Are supplied to the SYNC detection circuit 5 and the filter coefficient determination circuit 6, respectively. The SYNC detection circuit 5 detects the synchronization pattern data added to the preset time slot of the own station from among the synchronization pattern data added to the head of each time slot, and further detects, for example, the own station. The synchronization pattern data added to the time slot next to the time slot is detected. The respective detected synchronous pattern data of two consecutive time slots are supplied to the filter coefficient determination circuit 6 in the order of detection. The filter coefficient determination circuit 6 converts the tap coefficients of the transversal filters 31 to 34 into two time slots based on the supplied synchronization pattern data and the known synchronization pattern data stored in the SYNC pattern table 7. The two tap coefficients determined correspondingly and determined are stored in the coefficient memory 8 at the next stage. The coefficient interpolation circuit 9 sets tap coefficients of the transversal filters 31 to 34 by performing linear interpolation with tap coefficients corresponding to the two time slots stored in the coefficient memory 8. Thus, when decoding digital data and control data in a time slot of the own station, two bits determined based on each synchronization pattern data of two time slots sandwiching these data sections.
Tap coefficients linearly interpolated by one tap coefficient will be used. As a result, the filter coefficient of the equalization filter 3 can be accurately and quickly determined with a relatively small amount of calculation, and the filter coefficient can be adaptively controlled for each symbol. Next, the transversal filters 31 to 3
The operation for determining the tap coefficient of No. 4 will be described in detail. First, the duration of one symbol is T, and the demodulation output of the demodulation circuit 1, that is, the detection output of the first and second synchronous detectors 11 and 12 is checked at each time interval T to detect synchronous pattern data. . The tap delay time of each of the transversal filters 31 to 34 is set to be equal to the duration T of one symbol. Further, each of c _n the tap coefficients of the transversal filter _{31~34, e n, d n,} f n (n = -k, ..., 0, ..., -
k), the outputs I _i and Q _i of the equalization filter 3 are
Equations (1) and (2) are obtained. (Equation 1) (Equation 2) Here, x _i , y _i (i = − (k + m),..., 0,
.., + (K + m)) are detection outputs of the first and second synchronous detectors 11 and 12. Therefore, regarding the i-th symbol, the error ε _{i of the} I channel and the error δ _{i of the} Q channel are expressed by the equations (3) and (4). (Equation 3) (Equation 4) In equations (3) and (4), X _i , Y _i (i = −m,
.., 0,..., + M) are symbols determined from unique synchronization pattern data composed of a fixed pattern,
This is known data stored in the NC pattern table 7. From this, the sums of squares of the errors E _I and E _Q are
It is expressed by the equations (5) and (6). (Equation 5) (Equation 6) First, tap coefficients c _n and d _n are determined so as to minimize the error of the I channel. Applying the least squares method,
By partially differentiating equation (5) with respect to c _n and d _n , equations (7) and (8) are obtained. (Equation 7) (Equation 8) In equations (7) and (8), n = −k, −
By substituting (k-1),..., 0,..., + K, the simultaneous equations shown in equation (9) are obtained. (Equation 9) Since the coefficient matrix of this simultaneous equation (9) is a symmetric matrix, it is not necessary to perform calculations for each element. Further, in order to solve this simultaneous equation, it is general to first solve the coefficient matrix by L · U decomposition and then solve it. Similarly, the tap coefficients e _n and f _n are determined so as to minimize the error of the Q channel. By partially differentiating equation (6) with respect to e _n and f _n , equations (10) and (11) are obtained. (Equation 10) (Equation 11) In equations (10) and (11), n = −k, − (k−1),
By substituting..., 0,..., + K, the simultaneous equations shown in equation (12) are obtained. (Equation 12) The coefficient matrix of this simultaneous equation (12) is exactly the same as the coefficient matrix in equation (9). According to the above processing procedure, the tap coefficient G ₁ in the time slot assigned to the own station, for example, the time slot 1, can be obtained.
It can also be determined tap coefficients G ₂ of the next time slot 2. Then, the tap coefficient G _j corresponding to the j-th symbol of the data part in the time slot 1
Is determined by linear interpolation between the two obtained tap coefficients G ₁ and G ₂ , as shown in equation (13). (Equation 13) Here, J represents the total number of symbols transmitted in one time slot. In the case of the TIA system shown in FIG. 5, J = 1
62. In equation (13), linear interpolation is performed for each symbol, but the calculation amount can be further reduced by performing calculation for every several symbols. In the above embodiment, the tap coefficient in the time slot assigned to the own station is
The tap coefficients in the next time slot are obtained, and the tap coefficients of the transversal filters 31 to 34 are determined by linear interpolation of both tap coefficients. The tap coefficient is not limited to the coefficient, but may be a tap coefficient in a time slot several slots after the time slot allocated to the own station. According to this, it is possible to perform arithmetic processing with a margin in time as compared with the case where the tap coefficient in the next time slot is obtained. The tap coefficients of the transversal filters 31 to 34 may be determined by linear interpolation with the tap coefficients in the time slot assigned to the own station one frame later. In this case, in the memory 2 in FIG. 1, it is necessary to delay the data by a period corresponding to one frame, so this modification is useful when the delay time is not practically problematic. According to this, it is only necessary to always determine the tap coefficients in the time slot allocated to the own station, and therefore the amount of calculation in the filter coefficient determination circuit 6 can be reduced. Further, in the above embodiment, the case where the present invention is applied to a digital car telephone system has been described. However, the present invention is not limited to this case. What you get. As described above, according to the present invention,
The filter coefficient in the first time slot allocated to the own station and one frame of the first time slot
Determining a filter coefficient of the second time slot allocated to the own station after chromatography beam, you have to set the filter coefficients for the data in the first time slot by linear interpolation of the filter coefficients
The time slot assigned to your station.
It is only necessary to determine the tap coefficient
The filter coefficient can be set accurately and at high speed with a smaller amount of calculation, and the filter coefficient can be adaptively controlled for each symbol of data.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing one embodiment of the present invention. FIG. 2 is a block diagram illustrating an example of a configuration of a demodulation circuit in FIG. 1; FIG. 3 is a block diagram illustrating an example of a configuration of an equalization filter in FIG. 1; FIG. 4 is a configuration diagram of a frame in the TIA scheme. FIG. 5 is a configuration diagram of a time slot in the TIA scheme. [Description of Signs] 1 Demodulation circuit 3 Equalization filters 4 _I , 4 _Q 1/0 decision unit 5 SYNC detection circuit 6 Filter coefficient determination circuit 7 SYNC pattern table 9 Coefficient interpolation circuit 11 First synchronous detector 12 Second Synchronous detector 13 Carrier recovery units 31-34 Transversal filters 35, 36 Adders

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ identification symbol FI H04L 7/08 H04L 7/08 Z H04Q 7/38 H04B 7/26 109N (58) Fields surveyed (Int.Cl. ⁷ , DB Name) H04B 3/00-3/44 H04B 7/005-7/015

Claims (1)

(57) [Claim 1] A unit frame is composed of a plurality of time slots assigned to different mobile stations, and a unique synchronization pattern signal is added to each time slot and transmitted. In the digital mobile communication system for performing the above, an automatic equalizer adapted to determine the filter coefficient of the equalizer using the received synchronization pattern signal, wherein the first equalizer assigned to its own station Time slot synchronization pattern signal and one frame of the first time slot
A synchronization pattern detection means for detecting a synchronization pattern signal of a second time slot assigned to the own station after the first time slot; a first filter coefficient corresponding to the synchronization pattern signal of the first time slot; Coefficient determining means for determining a second filter coefficient corresponding to a synchronization pattern signal of a second time slot; and the first time slot by linear interpolation using the first filter coefficient and the second filter coefficient. And a coefficient interpolating means for setting a filter coefficient for data in the automatic equalizer.