JP3393765B2 - Array controller and data storage array - Google Patents

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION The present invention relates to a controller for controlling the transfer of data between a host system and a plurality of data storage devices, and also to a data processing system incorporating such a controller.

[0002]

BACKGROUND OF THE INVENTION Over the last few years, there has been increasing interest in disk drive arrays that store large amounts of data within computer systems. Disk array
It typically consists of a number of disk drives connectable to the system in use via one or more control elements that control the transfer of data to and from the disk drives. Disk arrays are designed for mass data storage, high reliability, and high speed data transfer to and from your system.

One widely used method for array architecture is RAID (Redundant A).
relays of Independent Disk
s). For more information on RAID, see the paper "A Case for Redundant Arr."
ays of Independent disks
(RAID) "(ACM SIGMOD confer
ence processes, Chicago,
IL. , June 1-3, 1988, pp. 109-1
It is described in a large number of documents including 16). This paper proposes five array levels (RAID 1-5) with different levels of data management. Each RAID
At the level, users can increase their data storage capacity by combining multiple inexpensive disk drives. RAID system stores two identical data in two drives (RAID1)
Or loss of data due to drive failure by spreading the data between two or more drives in an array, calculating the parity of the striped data, and storing that parity data on another drive. Protect against. If one of the drives holding the data fails, the parity data and the remaining data in the parity group can be used to reconstruct the data on the failed drive (RAID
2-5). An array is often referred to as "N + P" if it has N data disks and P parity disks. For example, in RAID 3, parity data stored on a single parity disk stripes the data between disks in bits or bytes. Therefore, for RAID 3, P equals 1. A parity group consists of groups of data on N disks and parity data on P disks.

When storing data to disk with RAID 3, parity is generated by performing an XOR operation on the stored data. The parity thus generated is stored on a separate disk. Logical data records are split and interleaved between disks, with parity stored on separate disks. All disks are accessed simultaneously for user application access. If the data stored in the array needs to be updated, the parity data of the parity group containing that data also needs to be updated. The parity generation can be implemented in software or in the form of XOR hardware. Hardware implementations can generally generate parity more quickly when writing data from the host system to the array. One example of such an embodiment is described in European Patent EP 508604.

[0005]

It is an object of the present invention to provide an improved storage array controller and an improved data array incorporating such an array controller.

[0006]

According to the present invention, an array controller is provided for controlling the transfer of data from a host system to an array of data storage devices. The array controller includes a processor connected to a data buffer for staging data during the transfer via a local bus, and includes a buffer controller for controlling the operation of the buffer, and further includes: Local used to transfer data
Includes channel hardware that presents multiple data channels selectable by bus address.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT Referring to FIG. 1, a host computer system 1 connected to a RAID controller 20 via a data bus or data link 12.
A data processing system including 0 is shown. RAID
The controller 20 uses the data links 40, 42, 4
Magnetic disk drives 50, 52 through 4, 46,
It is connected to a plurality of data storage devices in the form of 54,56. In FIG. 1, each disk drive is connected to the RAID controller 20 by a separate communication link, but in an alternative configuration, the disk array is a disk array.
It will be appreciated that the drives may be chained together and the two ends of the chain may also be configured as a coupled loop to communicate to the controller. It will be appreciated that the number of disk drives in the array will depend on the particular application to which the data processing system is attached. RA
In the ID3 configuration, the array consists of three, four or more data drives with one parity drive. The RAID controller 20 in the figure is
All R's in the host system that are separate from the host system, but in the form of, for example, an adapter card
It will likewise be appreciated that AID controller functionality may be included. The host system has its own RA
It can be connected to a second host system connected to the array of ID controllers and disk drives. This inter-host communication path provides some redundancy if one of the RAID controllers fails.

In the preferred embodiment, the host system is an IBM RISC System / 6000 computer running the IBM AIX operating system. Details of the RISC System / 6000 computer as well as the AIX operating system are readily available in the published literature. Host and RAI
The connectivity between the D controller and the disk drive is
Although it can be implemented in a number of different ways depending on the required bandwidth and usage, the preferred embodiment is described with reference to the serial storage architecture (SSA architecture). The SSA architecture is based on the American Specification Association (A
NSI) X3T10.1 is under development and is an interface designed for connecting external connection devices such as disk drives and tape devices to workstation servers (host systems) and storage subsystems. Information about SSA can be obtained from ANSI.

According to the SSA architecture, the host
The link between the system and the RAID controller is a serial link that provides a communication path for serialized data. Full-duplex communication over the link is provided by SSA, which allows rapid transmission of data between the various components of the system. Loop configurations use two communication paths to each drive (that is, communication from both ends of the chain) to double bandwidth for each drive in the loop, or to drive if communication fails. Other routes can be provided for. In SSA, two-signal connection (transmission and reception) that realizes full duplex communication is performed. Host system and RAI
The series connection between the D controllers consists of four wires used to communicate frames of information. The four lines consist of plus and minus output lines (transmit) and plus and minus input lines (receive). A port (called a "gateway") consists of hardware and firmware that supports one end of the link (one for the transmit path and one for the receive path). S
The SA's port can simultaneously maintain two 20 megabyte per second conversations, inbound and outbound, at the same time. Therefore, SSA dual port
A node can perform four simultaneous conversations for a total of 80 megabytes per second. The port of one node connects to the port of another node via a link. A gateway is established between the two nodes to achieve full duplex communication over the SSA network. Some nodes issue transactions to other nodes to perform functions such as accessing disks. 2 gateways
The task control block consists of two connections (one in each direction), the master (the connection issuing the transaction) constitutes the master control block, and the slave side of the gateway receives the transaction frame and calls the addressed service. Make up.

SSA uses logical aspects of the SCSI (Small Computer System Interface) specification to address disk drives connected in series. These SCSI specifications correspond to the physical specifications of SSA. That is, SSA is a transport layer for various upper layer protocols, especially SCSI-2 for storage devices.
Can be used as SSA-based SCSI-2, in the presence of initiators, targets, and logical units, maintains the same address appearance as specified in the SCSI-2 specification.

The main components of the RAID controller are shown in FIG. The controller is a RAM containing code and control blocks via a microprocessor bus 24.
25 connected to the ROM 26 and the ROM 26
Including 2. Microprocessor (MP) bridge 27
The microprocessor 2 via the local bus 28.
2 is connected to the DRAM controller 29. The DRAM controller is connected to the DRAM 30. The DRAM controller contains the hardware necessary to perform a flow-through XOR on the RAID3 array. host·
The bridge 32 provides a connection to the host system hardware via the PCI bus 45. In addition,
Connected to bus 28 are two SSA dual port chips 34 and 36 which provide a communication path to an array of disk storage devices.

Referring to FIG. 3, channel hardware 48 is provided between local bus 28 and DRAM control unit 49 for address information and data manipulation when data is continuously accessed in DRAM 30. There is. The DRAM controller operates in a conventional manner to access data in the DRAM, multiplex matrix addresses, and generate DRAM control signals. Use page mode cycles to maximize bandwidth during burst transfers. The channel hardware acts as a slave on the local bus, such as a normal DRAM controller, and the operation of the channel hardware is transparent to the master transferring data through the channel. It is advantageous to provide multiple channels to allow simultaneous data transfer. The specific channel is
Select by high-order bit of input address. For example,
For 16 channels, the local bus address contains a bit to select the channel function and 4 bits to address the particular channel. The local bus address used in this embodiment of the invention is shown in FIG. Each channel has a function field and associated parameters. The parameters are stored in the channel RAM in the channel hardware and initialized by the firmware before using the channel for data transfer. In the embodiment described herein, the channel hardware comprises 16 channels to manage the data transfer between the local bus and the DRAM. Channels include 0, 1. ． ． The number of 15 is attached. The channel is selected by bits 31:24 of the local bus address as follows. Bit 31:24 Function 0100xxxx Direct access to DRAM 0101cccc Access to DRAM via Channel 'cccc' For example, for channel 7, bits 27:24 are '0111'
It is selected in the case of b.

In an embodiment of the invention, any channel can be used for RAID 3 stripe and write operations, as described below.
However, only channel 15 can be used in the RAID3 reconfiguration operation. In addition, these channels are designed to operate simultaneously, causing collisions when using data and parity buffers within the controller hardware. An example is shown below.

All 16 channels can perform stripe and RAID3 write functions simultaneously. Up to eight channels are RAID3, provided channel "n" is not used at the same time as channel "n + 8" (both used for RAID3 writes).
The write function can be executed simultaneously. Channel 15 to RAI
Used for D3 reconstruction, any other channel can be used for stripes. The following RAM buffers are required in the controller (see Figure 5).

One data buffer composed of 32 word × 36 bit dual port RAM. This data buffer is used for RAID3 reconstruction and RAID3 writes.

Parity buffer 2 composed of 4 words × 36 bits dual port RAM each
Individual. Used only for RAID3 reconstruction.

The data and parity buffers are addressed by the BufPtr field in the selected channel.

These channels are used to perform defined array functions. The use of these features and channel hardware will now be described with reference to an array configured as RAID3. In such a configuration, the functions can be categorized as follows.

1. RAID 3 stripes: This operation includes both stripes of data from device to DRAM and stripes of data from DRAM to device. Use one channel for each device. 2. RAID3 write: This operation involves the transfer of data from the host to DRAM. In this embodiment, this operation produces parity data on the fly as the data is transferred into DRAM.
A single channel is used for this type of transfer. Note that this feature is used for all transfers from host to DRAM, even if the disk is destroyed. In that case, the data on that disk is completely unavailable. 3. RAID3 Reconfiguration: This operation is DRA
Includes the transfer of data from M to the host and takes effect if one of the data stores becomes inoperable.
In this embodiment, data lost when transferring data from DRAM is reconstructed on the fly. A single channel is used for this type of transfer.

First, the setup and operation of the system for executing the writing of data from the host memory to the device configured as the RAID3 array will be described.

When an application running on the host requests the writing of data to the storage device, first the controller / controller executes a RAID3 write to write the data to the controller DRAM buffer.
Set up hardware and firmware and also RA
In order to transfer data from the ID buffer to individual disk storage devices, the controller hardware and firmware must be set up to perform RAID 3 stripes. To simplify the following discussion, R
The two operations of AID3 write and RAID3 stripe are described as occurring at the same time. However,
RAID3 writes and RAIs are provided so that the pipeline of data between the host memory and the device is efficient.
The two operations of the D3 stripe are generally arranged to operate in parallel. A / B buffering is performed in the controller so that it can write to the disk drive upon receipt of a specified amount of data from the host, as described in detail below. RAID 3 write operations and RAID 3 stripe operations will now be described with reference to FIG.

RAID3 Writing RAID3 writing starts when the application 100 running on the host requests writing of data to the storage device. The application sends details of the data to be transferred, including the address of the data in host memory, to the file system 102 associated with the host system. The file system makes this request
Translate to a physical request containing the number of disks, the starting logical block address and the number of blocks of data to write. If the device driver 104 master process is presented with this request, a transaction occurs and is issued to the controller. This master process uses the master control block (MC
Call the host kernel with a pointer to B). M
The CB is addressed in the controller to the required service. In the case of the present invention, the required service is RAID
It is 3. The host kernel calls the gateway with a pointer to the MCB. The host side of the gateway uses the gateway transaction control block (GTC) for write operations in host memory.
B) is generated. GTCB, in the discussion of the present invention,
A number of parameters including (i) destination service (RAID3 service provided by controller firmware), (ii) pointer to write data in host memory, and (iii) pointer to details of actual operation parameters. specify.

The PCI gateway writes a pointer to the GTCB to a queue in memory. The host hardware issues an interrupt to the controller when the host writes the GTCB pointer. Gateway 10
The controller side of 6 fetches the GTCB by the DMA 109 using the host interface chip. The gateway then enters the transaction control block (TCB) in the controller address space.
To generate. Finally, the gateway calls the controller kernel 110 to request the TCB to execute. The controller kernel calls the RAID3 service 108 with a pointer to the TCB. Then RA
The ID3 service generates write transactions for each disk drive that makes up the RAID3 array and sends these transactions to the disk service 112 using the kernel. Disk Services issues the appropriate SSA-SCSI read command,
These are sent to the SSA driver 114 which includes the serial interface chip 116.

The SSA driver issues SCSI commands to the disk drive 120 using the SSA protocol and serial interface chip. For SCSI commands to each disk drive, start L
Specify the BA and the number of blocks to write.

At the controller, the memory allocation service allocates space in the DRAM buffer for write data. The memory allocation service allocates and initializes one channel in the channel hardware for RAID3 writes. In this initialization, the following parameters are written into the channel RAM (1 in the description of the invention).
Word equals 4 bytes).

(I) Contains the Addrl DRAM word address. (Ii) InP This is a bit for specifying whether the parity should be interleaved by data (InP = 1) or whether the parity should be written in another parity data area in the allocated buffer space (InP = 0). . (Iii) A 2-bit field coded to select the Fun channel function (for RAID3 writing, this field is set to 10b). (Iv) Addr2 Includes additional DRAM word address (specifies address in DRAM for parity if InP = 0). (V) Specifies the width of the ArrWid RAID3 array. ArrWid is defined to be equal to N-1. However, N is the number of data disks (ie, parity disks are not included).

Stripe size (ie, the size of the unit of data stored in DRAM for each disk,
For example, see FIG. 5) is an on-chip RA in the controller.
A tradeoff is made between minimizing the amount of M and maximizing DRAM bandwidth when accessing the parity stripe. In the discussion below, stripes
Set the size to 16 bytes.

Once the channels are allocated, the DMA engine 1 in the host interface chip 32
08 is loaded with the source address in the host (provided on the original I / O request), the destination address in DRAM, and the byte count. The DMA engine 108 then controls the transfer of data to DRAM by DMA. If a channel is specified, a RAID3 write uses one stripe of the data buffer to calculate the parity for each stripe. The data on the local bus goes straight to the address A of the DRAM.
It is stored in ddr1. Each stripe of data (ie 16 bytes) at the same time the data is stored in the DRAM
Perform the XOR operation above. The stripe of data on the first disk is the data buffer selected by bits 26:24 of the local bus address.
Stored in stripes. Data on the remaining disk
The stripes are XOR'd into the buffer. The contents of the stripe buffer (ie, parity), once generated, are linearly stored in separate areas of the DRAM using Addr2 if InP = 0, and In
If P = 1, it is stored as an additional data stripe.

RAID 3 Stripe As already mentioned, the RAI from DRAM to disk.
D3 stripe operations generally operate in parallel with RAID3 write operations between the host and DRAM. The RAID 3 stripe operation proceeds as follows.

In response to the SCSI command issued by the controller via the serial link, each disk drive returns a data request message when it is ready to receive data. Upon receiving the data request message from each drive, the SSA driver sets up the SIC to transfer the data by DMA to the DRAM over the local bus. For each disk drive, the SSA driver dynamically allocates a SIC DMA channel, details of the local bus address (provided within the original write transaction issued by the RAID3 service), and the total number of bytes to transfer. , And the operation is a write operation, the DMA channel is initialized. Bits 31:24 of the local bus address are
Specifies that controller channel identification and transfer should go through DRAM.

One controller channel is allocated and initialized for each disk drive in the array. The controller firmware loads the parameters InP, ArrWid and Addr1 into the channel RAM for the specified channel of each disk in the array (see above for definitions of these parameters). Striping is performed when reading and writing data over the local bus. For each disk, the channel hardware uses the word address Addr1
To access the requested data from the DRAM. Addr1 is typically incremented by 1 after each word is accessed. However, at the end of the first stripe of data (ie, 16 bytes) on each disk, Addr1 is 1 + 4 if InP = 0 (parity data stored in a separate area of DRAM during RAID3 writing). It is incremented by * ArrWid, and when InP = 1, it is incremented by 1 + 4 * (1 + ArrWid). In this way, data is transferred to each disk by the allocated controller channel.

Next, RAID the channel hardware.
The case of use as a part of the three reconstruction operation will be described. This operation is used to reconstruct read data from a corrupted data disk during an array read command. The data flow of the reconstruction operation is shown in FIG. During the reconstruction operation,
The data from the operational disk is striped into DRAM using any available channel in the manner described above (unless, of course, the data is transferred into DRAM rather than from DRAM). When non-interleaved parity is selected (InP = 0),
The stripes on the destroyed disk are emptied and the read data from the parity disk is stored linearly in a separate area of DRAM using Addr2. However, if the interleaved parity mode is selected (InP = 1), the parity will use stripes instead of corrupted disks (no Addr2). RAID 3 reconstruction uses A / B data and parity buffers and channel 15.
The firmware has parameters InP, ArrWid,
Initialize the channel RAM for channel 15 with Addr1, Addr2 and BufPtr. The identification of the destroyed disk is stored in the reconfiguration register that controls the RAID3 reconfiguration function.

The flow-through XOR processes one stripe from each disk as follows.

1. The data requested by the host bridge is typically local to the data buffer 80.
Transfer to the bus, increment the buffer pointer (BufPtr) after each word. However, if the buffer pointer addressed the stripe corresponding to the corrupted disk (identified in the reconstruction register), the data would instead replace the current parity buffer (8
2 or 84). 2. As each word is transferred over the local bus, the other data and parity buffers are filled from DRAM with the next set of stripes. Fetch valid data stripe in channel 15 using Addr1. Addr1 is incremented after each word. When you reach the stripe allocated to the destroyed disk,
If Addr1 keeps incrementing and InP = 0, Addr1
Fetch the parity stripe from the address pointed to by 2 (where Addr2 is incremented after each word of the parity stripe) and InP = 1
In the case of, the fetch is performed from the stripe position of the destroyed disk (Addr2 is unchanged in this case). Each word fetched is stored in the data buffer at BufPtr. The first stripe is also stored in the parity buffer. The next stripe is XOR'd into the parity buffer.

In summary, the following matters will be disclosed regarding the configuration of the present invention.

(1) In an array controller that controls the transfer of data from a host system to an array of data storage devices, a processor connected to a data buffer that stages the data during the transfer via a local bus. , A buffer that controls the behavior of the buffer
An array controller that includes a controller and channel hardware used to transfer data to and from a data buffer that presents multiple data channels selectable by a local bus address. (2) The array controller according to (1) above, wherein the channel hardware includes a channel storage device that stores parameters associated with each data channel. (3) Local bus address transfers data to data
The array according to (1) above, characterized in that it includes an identification bit specifying that it should be transferred by a buffer.
controller. (4) The array controller according to (3) above, wherein the local bus address includes a channel identification bit that identifies a data channel to be selected for data transfer. (5) The array controller described in (4) above, wherein the local bus address specifies an array controller service to be executed for the data to be transferred on the selected channel. (6) In the above (5), further comprising means for providing a RAID3 array controller service selectable by a local bus address, thereby storing data on a storage device according to RAID3. Array controller described. (7) One of the RAID 3 services transfers data from the host to a data buffer over a channel designated by a local bus address for later storage on a data storage device, and later The array controller of (6) above, which is a RAID3 write operation that generates parity associated with the data for storage on parity storage. (8) One of the RAID 3 services is a RAID 3 partition operation that transfers data between a data storage device, a parity storage device and a data buffer and selects one data channel for each storage device. The array controller according to (7) above, characterized in that: (9) The array controller according to (8) above, wherein one of the RAID3 services is a RAID3 reconstruction operation that reconstructs data on a failed drive. (10) The array controller according to (1) above, wherein the data buffer is a dynamic random access memory (DRAM). (11) A data storage array connected to a host computer system including a plurality of data storage devices configurable as an array and an array controller controlling transfer of data from the host system to the array of data storage devices. To transfer data between a processor connected to a data buffer that stages the data during the transfer via a local bus, a buffer controller that controls the operation of the buffer, and the data buffer And channel hardware presenting a plurality of data channels selectable by local bus address. (12) The array according to (11) above, wherein the channel hardware includes a channel storage device that stores parameters associated with each data channel. (13) The array described in (11) above, wherein the local bus address includes an identification bit that specifies that the data should be transferred by the data buffer. (14) The array described in (13) above, wherein the local bus address includes a channel identification bit that identifies a data channel to be selected for data transfer. (15) The array described in (14) above, wherein the local bus address specifies an array controller service to be performed on the data to be transferred on the selected channel. (16) In the above (15), further comprising means for providing a RAID3 array controller service selectable by a local bus address, thereby storing data on a storage device according to RAID3. The array described. (17) One of the RAID3 services has a local bus connection for later storage on a data storage device.
A RAID3 write operation that transfers data from a host to a data buffer over a channel specified by an address and generates parity associated with the data for later storage on parity storage. The array according to (16) above. (18) One of the RAID 3 services is a RAID 3 partition operation that transfers data between a data storage device, a parity storage device and a data buffer and selects one data channel for each storage device. The array according to (17) above, which is characterized in that (19) One of the RAID3 services is a RAID3 reconfiguration operation for reconfiguring data on a failed drive, (18).
The array described in. (20) The array described in (11) above, wherein the data buffer is a dynamic random access memory (DRAM).

[Brief description of drawings]

FIG. 1 is a block diagram of a data processing system that includes a host connected to an array of hard disk devices via a RAID controller.

2 is a block diagram showing the main logical components of the RAID controller of FIG. 1. FIG.

3 is a block diagram showing a relationship between channel hardware and DRAM controller hardware of the RAID controller of FIG.

FIG. 4 is a block diagram illustrating services provided by a data processing system that implements RAID operations according to the present invention.

FIG. 5 is a block diagram of RAID controller DRAM hardware and flow-through XOR hardware.

FIG. 6 is a diagram of a local bus address.

[Explanation of symbols]

10 Host computer system 12 data buses 20 RAID controller 40 data links 42 Data Link 44 data links 46 data links 50 disk drive 52 disk drive 54 disk drive 56 disk drive

─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Stephen G. Lunin United States 95120 San Jose Thorntree Drive, California 5966 (56) Reference JP-A-8-221326 (JP, A) JP-A-6-332626 ( JP, A) JP 59-98234 (JP, A) JP 49-112544 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) G06F 3/06-3/08 G06F 12/08 G06F 13/12-13/18

Claims (12)

(57) [Claims] 1. An array controller for controlling the transfer of data from a host system to an array of data storage devices, the processor connected to a data buffer for staging the data during said transfer via a local bus; A buffer controller that controls the operation of the buffer and channel hardware that presents multiple data channels selectable by local bus address used to transfer data to and from the data buffer. A selected channel that contains a local bus address that contains an identification bit that specifies that data should be transferred by the data buffer, and that contains a channel identification bit that identifies the data channel that should be selected for the data transfer. The array to perform on the data to be transferred Characterized by specifying a controller service, array controller. 2. The method of claim 1, further comprising means for providing a RAID3 array controller service selectable by a local bus address, thereby storing data on a RAID3 storage device. The array controller described in. 3. One of the RAID 3 services is
Transfers the data from the host to the data buffer via the channel specified by the local bus address for later storage on the data storage and the data for later storage on the parity storage. The array controller of claim 2, wherein the array controller is a RAID3 write operation that produces associated parity. 4. One of the RAID 3 services is
4. The RAID 3 partition operation of transferring data between a data storage device, a parity storage device, and a data buffer, and selecting one data channel for each storage device, as set forth in claim 3. Array controller. 5. One of the RAID 3 services is
5. A RAID3 reconstruction operation that reconstructs data on a failed drive.
The array controller described in. 6. The array controller according to claim 1, wherein the data buffer is a dynamic random access memory (DRAM). 7. Data for connection with a host computer system including a plurality of data storage devices configurable as an array and an array controller for controlling transfer of data from the host system to the array of data storage devices. In a storage array, to transfer data between a processor connected to a data buffer that stages the data at the time of the transfer through a local bus, a buffer controller that controls the operation of the buffer, and the data buffer Channel hardware that presents multiple data channels selectable by local bus address for use with the local bus address to specify that data should be transferred by the data buffer. Selection bit for data transfer. An array characterized by including a channel identification bit that identifies a data channel and specifying an array controller service to perform on the data to be transferred on the selected channel. 8. The method of claim 7, further comprising means for providing a RAID3 array controller service selectable by a local bus address, thereby storing data on a RAID3 storage device. The array described in. 9. One of the RAID 3 services is
Transfers the data from the host to the data buffer via the channel specified by the local bus address for later storage on the data storage and the data for later storage on the parity storage. 9. The array of claim 8, wherein the array is a RAID3 write operation that produces associated parity. 10. A RAID3 split operation in which one of the RAID3 services transfers data between a data store, a parity store and a data buffer and selects one data channel for each store. 10. The array according to claim 9, characterized in that 11. A RAID in which one of the RAID 3 services reconstructs data on a failed drive.
11. Array according to claim 10, characterized in that it is a 3 reconstruction operation. 12. The array according to claim 7, wherein the data buffer is a dynamic random access memory (DRAM).