JP3388086B2 - Sample and hold circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sample and hold circuit, and more particularly to a sample and hold circuit with improved feedthrough characteristics. 2. Description of the Related Art In a conventional sample and hold circuit, there is a phenomenon (hereinafter referred to as "feedthrough") in which an input leaks through a capacitance between electrodes of a switch circuit during holding. Was an important issue. FIGS. 4 and 5 are circuit diagrams showing an example of a conventional sample and hold circuit with improved feedthrough. In FIG. 4, 1 is an input buffer, 2a and 2b are switch circuits, 3a and 3b are hold capacitors,
Is an output buffer, 5a and 5b are compensation capacitors, 100 is a differential input, and 101 is a differential output. A differential input 100 is input to a differential input terminal of an input buffer 1, a non-inverted output of the input buffer 1 is connected to a switch circuit 2a and one end of a compensation capacitor 5a, and an inverted output of the input buffer 1 is connected to a switch circuit. 2b and one end of the compensation capacitor 5b. The other end of the switch circuit 2a is connected to a hold capacitor 3
a, one end of the output buffer 4 and the other end of the compensation capacitor 5b. The other end of the switch circuit 2b is connected to the hold capacitor 3b, the inverting input terminal of the output buffer 4, and the other end of the compensation capacitor 5a. Further, the other ends of the hold capacitors 3a and 3b are grounded, and a differential output terminal of the output buffer 4 outputs a differential output 101. Here, the operation of the conventional example shown in FIG. 4 will be described. At the time of sampling, the switch circuits 2a and 2b are turned on, and the differential input is input to the hold capacitors 3a and 3b via the input buffer 1 and the switch circuits 2a and 2b. At the same time, it is output as a differential output 101 via the output buffer 4. On the other hand, at the time of hold, the switch circuits 2a and 2b are in the "OFF" state, and the differential input 100
Is output as the differential output 101 via the output buffer 4 irrespective of the value of. However, even if the switch circuits 2a and 2b are actually in the "OFF" state, if the value of the differential input 100 changes, charges are injected through the capacitance between the electrodes,
The differential output that should have been held changes. For example, if the change of the differential input is ".DELTA.V", the capacitance values of the hold capacitors 3a and 3b are "CH", and the capacitance value of the inter-electrode capacitance is "C", the hold capacitor 3a has "
1 / 2ΔV · C ”is stored in the hold capacitor 3b as“ − ”.
Since a charge of 1 / 2.DELTA.V.C is injected, the differential output 100 changes by ".DELTA.V. (C / CH)." Here, the conventional example shown in FIG. Capacity 5
Since the capacitance values of the compensation capacitors 5a and 5b are set to “C”, the charge of “− ／ ΔV · C” is held in the hold capacitor 3a via the compensation capacitor 5b. The hold capacitor 3b receives “1 /” via the compensation capacitor 5a.
Since the charge of 2ΔV · C ”is respectively injected, the injected charge is offset and the feedthrough becomes zero. As a result, the compensation capacitance 5a has the same capacitance value as the capacitance between the electrodes of the switch circuit. 5a and 5b, the injected charge is offset and the feedthrough can be reduced.
b, 4 and 100 have the same reference numerals as in FIG.
And 6b are switch circuits, 8a and 8b are bootstrap buffers, and 101a is a differential output. In FIG. 5B, 9 is a transconductance amplifier, and 10a and 10b are load resistances. In FIG. 5A, the differential input 100 is input to the differential input terminal of the input buffer 1 and
Is connected to the input terminal of the switch circuit 6a, and the inverted output of the input buffer 1 is connected to the input terminal of the switch circuit 6b. One output terminal of the switch circuit 6a is connected to one end of the hold capacitor 3a and the non-inverting input terminal of the output buffer 4, and one output terminal of the switch circuit 6b is connected to the hold capacitor 3b and the inverting input terminal of the output buffer 4, respectively. And the other ends of the hold capacitors 3a and 3b are grounded. The non-inverted output and inverted output of the output buffer 4 are output as a differential output 101a and are connected to bootstrap buffers 8a and 8b. further,
The outputs of the bootstrap buffers 8a and 8b are connected to the other output terminals of the switch circuits 6a and 6b, respectively. FIG. 5B is a circuit diagram showing a more detailed structure of the input buffer 1. The differential input 100 is connected to the transconductance amplifier 9, and the output of the transconductance amplifier 9 is a load. Resistance 10
a and 10b are grounded and output. The operation of the conventional example shown in FIG. 5A will now be described with reference to FIG. The basic operation of the sample and hold is the same as that of the conventional example shown in FIG. At the time of sampling, the switch circuits 6a and 6b are connected to "A" and "B" in FIG. Therefore,
The gain of the transconductance amplifier 9 is "gm",
Assuming that the load resistance is “R”, the gain of the input buffer 1 at the time of sampling is “gm · R”. On the other hand, at the time of hold, the switch circuits 6a and 6b are connected to "c" and "d" in FIG. Therefore, the output resistances of the bootstrap buffers 8a and 8b are connected in parallel with the load resistances 10a and 10b, so that the bootstrap buffers 8a and 8b are connected.
Assuming that the output impedance of b is “ro”, the gain of the input buffer 1 at the time of holding is “gm · ro”. Here, since "ro <<R", the differential output of the input buffer 1 becomes "ro / R" and the hold capacitance 3
The charges injected into a and 3b are also reduced to “ro / R”. As a result, the differential output is switched to the bootstrap
By feeding back by the buffers 8a and 8b to reduce the gain of the input buffer 1 at the time of holding, the injected charge is reduced and the feedthrough can be reduced. However, in the conventional example shown in FIG. 4, the frequency band is limited by the compensation capacitance. In the conventional example shown in FIG. 5A, the output impedance of the bootstrap buffer is reduced. Due to the influence, there have been problems such as insufficient reduction of feedthrough and deterioration of settling characteristics. Therefore, an object of the present invention is to realize a sample and hold circuit capable of reducing feedthrough. In order to achieve the above object, according to the present invention, in a sample and hold circuit, a differential output type input buffer to which an input signal is input, and the input buffer An adder that adds the non-inverted output and the inverted output of the non-inverted output,
A first switch circuit for selecting the output of the adder at the time of hold, a second switch circuit to which the output of the first switch circuit is input and which is closed when sampling and open when hold; And a hold capacitor for holding the output of the second switch circuit, and an output buffer for outputting the voltage held in the hold capacitor. Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a circuit diagram showing one embodiment of a sample and hold circuit according to the present invention. In FIG. 1, 1 and 4 have the same reference numerals as in FIG. 4, 3c is a hold capacity, 11 is an adder, 12
And 13 are switch circuits, 102 is an input signal, and 103 is an output signal. The input signal 102 is input to the non-inverting input terminal of the input buffer 1, and the non-inverting output of the input buffer 1 is connected to one input terminal of the adder 11 and one input terminal of the switch circuit 12. The inverted output of the input buffer 1 is connected to the other input terminal of the adder 11. The output of the adder 11 is connected to the other input terminal of the switch circuit 12, and the output of the switch circuit 12 is connected to the input terminal of the switch circuit 13. The output of the switch circuit 13 is connected to one end of the hold capacitor 3c and the non-inverting input terminal of the output buffer 4. The non-inverted output of the output buffer 4 is the output signal 1
03, the inverted input terminals of the input buffer 1 and the output buffer 4 and the other end of the hold capacitor 3c are grounded. The operation of the embodiment shown in FIG. 1 will be described with reference to FIG. FIG. 2A is a circuit diagram showing a connection relationship at the time of sampling, and FIG. 2B is a circuit diagram showing a connection relationship at the time of hold. At the time of sampling, the switch circuit 12
2A, and the switch circuit 13 is in the “ON” state, so that the connection relationship is as shown in FIG. The gain of the input buffer 1 is set to “+ G” and “−G”.
G ", the input signal 102 is output multiplied by" + G ". This voltage is held in the hold capacitor 3c.
2 is connected to the “B” side, and the switch circuit 13 is connected to the “OF”
Since the state is “F”, the connection relationship is as shown in FIG. The non-inverted output and inverted output of the input buffer 1 are obtained by multiplying the input signal 102 by "+ G" times and "-G" times, and these outputs are added by the adder 11. Is "0". As a result, when the non-inverting input and the inverting input of the input buffer 1 are added during the hold and applied to the switch circuit 13, the switch circuit 1 in the "OFF" state is obtained.
No. 3 shows no change in the input signal 102, and the feedthrough becomes extremely small. FIG. 3 is a circuit diagram showing another embodiment of the sample and hold circuit according to the present invention. In FIG. 3, 1, 3c, 4, 11, 12 and 13 are denoted by the same reference numerals as in FIG. 1, 3d is a hold capacity, 11a is an adder,
12a and 13a are switch circuits, 100a is a differential input, and 101b is a differential output. The differential input 100a is input to the differential input terminal of the input buffer 1, and the non-inverted output of the input buffer is connected to one input terminal of the adders 11 and 11a and the switch circuit 1
2 is connected to one of the input terminals. The inverted output of the input buffer 1 is connected to the other input terminals of the switch circuits 11 and 11a and the switch circuit 12
a is connected to one input terminal. The output of the adder 11 is connected to the other input terminal of the switch circuit 12, and the output of the switch circuit 12 is connected to the input terminal of the switch circuit 13. The output of the adder 11a is a switch circuit 12a
And the output of the switch circuit 12a is connected to the input terminal of the switch circuit 13a. The output of the switch circuit 13 is the hold capacitance 3
c is connected to one end of the output buffer 4 and the non-inverting input terminal of the output buffer 4, and the output of the switch circuit 13 a is connected to one end of the hold capacitor 3 d and the inverting input terminal of the output buffer 4. Further, the output buffer 4 has a differential output 101.
b, and the other ends of the hold capacitors 3c and 3d are grounded. Here, the operation of the embodiment shown in FIG. 3 is the same as that of the embodiment shown in FIG. 1, and the portion "a" in FIG. "
Perform the above-described operation with respect to the inverted output of the input buffer 1. In the embodiment shown in FIG. 1 and the like, the voltage applied to the switch circuit 13 is always constant, and it becomes easier to keep the switch circuit 13 in the "OFF" state as compared with the conventional example. The power consumption of the switch circuit 13 can be reduced. Further, if the power consumption is the same as that of the conventional example, the band is high, and the circuit configuration is simpler than that of the conventional example, so that high-speed operation becomes possible. As is clear from the above description,
According to the present invention, the following effects can be obtained. By adding the non-inverting input and the inverting input of the input buffer at the time of holding and applying the result to the switch circuit, a sample-hold circuit capable of reducing feedthrough can be realized.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a circuit diagram showing one embodiment of a sample and hold circuit according to the present invention. FIG. 2 is a circuit diagram showing a connection relation at the time of sampling and a connection relation at the time of hold; FIG. 3 is a circuit diagram showing another embodiment of the sample and hold circuit according to the present invention. FIG. 4 is a circuit diagram showing an example of a conventional sample and hold circuit with improved feedthrough. FIG. 5 is a circuit diagram showing an example of a conventional sample and hold circuit with improved feedthrough. [Description of Signs] 1 Input buffers 2a, 2b, 6a, 6b, 12, 12a, 13, 13a
Switch circuit 3a, 3b, 3c, 3d Hold capacitance 4 Output buffer 5a, 5b Compensation capacitance 8a, 8b Bootstrap buffer 9 Transconductance amplifier 10a, 10b Load resistance 11 Adder 100, 100a Differential input 101, 101a, 101b Differential output 102 Input signal 103 Output signal

Claims (1)

(57) [Claim 1] In a sample and hold circuit, a differential output type input buffer to which an input signal is input, and an adder for adding a non-inverted output and an inverted output of the input buffer And a first switch circuit for selecting the non-inverted output at the time of sampling and selecting the output of the adder at the time of holding. The output of the first switch circuit is input and closed at the time of sampling and opened at the time of holding. A sample-and-hold circuit comprising: a second switch circuit that is in a state; a hold capacitor that holds an output of the second switch circuit; and an output buffer that outputs a voltage held by the hold capacitor. circuit.