JP3386503B2 - Binary decision graph input variable order determining apparatus and binary decision graph input variable order determining method - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a binary decision graph (BinaryDecisio) representing a logic function of a logic circuit.
n-diagram, BDD) and binary decision graph input variable order decision device and 2 used for verification of logic circuit design using
The present invention relates to a method for determining the order of input variables for a minute decision graph .

[0002]

2. Description of the Related Art One of methods for expressing a logical function of a logic circuit
The binary decision graph (BinaryDecisio)
n Diagram, BDD), and design verification of a logic circuit using this is performed. The binary decision graph is
When processing a logical function on a computer, there is a property that it can be expressed much more compactly than other expression methods and that the same logical function is always the same shape.In recent years, logical synthesis that handles logical functions, Logical collation (logical comparison),
It is becoming essential for various design support tools such as test generation. The binary decision graph is described in detail in the following documents. [1] R. E. Bryant: Graph-Based
Algorithmsfor Boolean Fun
actionManipulation, IEEE Tr
ans. Comput. , Vol. C-35, No.
8, pp. 677-691, 1986. [2] Fujita et al .: A variable order decision algorithm for binary decision graphs and its evaluation, IPSJ Journal, Vol.
31, No. 4, Apr. 1990. [3] S. MAl
ik et al. : Logic Vericat
ion using Binary Decision
Diagrams ina Logic Synthe
sis Environment, in Proc. I
nt. Conf. Computer-Aided De
sign, pp. 6-8, 1988. [4] K. S. B
race et al. : Efficient Imp
element of a BDD pack
age, in Proc. Design Automa
section Conf. , Pp. 40-45, 1990.
The binary decision graph expresses a logical function by a binary decision tree, and then (1) the order of input variables is fixed for all paths from the top node. (2) Share all subgraphs that can be shared. (3) Delete a node that has the same two child nodes. It is a contracted thing. This will be specifically described with reference to FIG. The binary decision graph shown in FIG. 4 represents the function of the output of the logic circuit of FIG. 3 as a function related to the input. When the logical function of the output of the logic circuit of FIG. 3 is expressed by an equation, Y = A · B + C · DZ = B ·
It becomes E + DF. In FIG. 4, the logical function Y is represented by four nodes. ○ represents a node,
Each node corresponds to one input variable, and
It is described in. The highest node pointed to by Y corresponds to the input variable A. From the node, 2
Two branches extend downward, the left side shows the case where the input variable is 1, and the right side shows the case where the input variable is 0.
Logical values are expressed as 1,0. Although there are a plurality of 1,0 for the sake of clarity, they are actually represented by one. In this binary graph,
The logical function of Y can be known by tracing the node downward from the node pointed to by Y. For example,
When A is 1 and B is 1, the value of Y is 1.
This can be seen by following the leftmost edge of the figure. Two
The minute decision graph is characterized in that the size, that is, the number of nodes, greatly differs depending on the order of fixed input variables. Therefore, even a complicated logical function may be represented with a small number of nodes if a good variable order is selected, and a simple logical function may have a large number of nodes if a bad variable order is selected. The larger the number of nodes required to express a logical function, the larger the memory amount and processing time required for processing. Therefore, a technique for determining the order of input variables that reduces the number of nodes is extremely important. The difference in the binary decision graph due to the difference in the input variable order will be described with reference to FIGS. 4 and 5. In FIG. 4, the input variable order is A, B, E,
C, D, and F, and the number of nodes in the binary decision graph is eight. On the other hand, FIG. 5 shows the same logical function expressed in different input variable order, and the number of nodes is 10. As you can see from Figure 4 and Figure 5,
Even when the same logical function is expressed, the number of nodes required to express the logical function in the binary decision graph differs depending on the order of the input variables. In the case of this example, this difference is not so large, but in a general circuit, this difference is large. Therefore, from the logic circuit diagram expressed by the gate connection such as AND / OR shown in FIG. 3, a technique for determining the order of input variables that reduces the number of nodes necessary for expressing the logic function is very important. Has become important. A conventional technique relating to an input variable determination method for a binary decision graph will be briefly described. For details, refer to the above-mentioned document [2],
It is described in [3]. It is known that the relationship between the logic circuit diagram and the binary decision graph expressing the logic function has the following tendency. -The input variables connected to the inputs of the same gate will have a smaller number of nodes if they are arranged in the closest order. As a heuristic method that satisfies this property, a method of using a search in the direction of the input side with priority from the depth of the output and using the order of the search as the order of the input variables when creating a binary decision graph is adopted. . In the methods of [2] and [3], improvements are made to this so that a better input variable order can be obtained.
In reference [2], the ordering of input fan-outs of 2 or more is adopted first. In the literature [3], when the input of a certain gate is searched, the one having a larger number of gate stages is preferentially searched. When the binary decision graph is used as a logic expression such as logic synthesis or test generation, all logic functions in the logic circuit must be expressed by one common input variable order. Further, in the logic matching, not all logic functions are necessarily represented by a common input variable order, but if they are represented by a common input variable order, there is an advantage that processing can be performed at high speed. Therefore, a technique of an input variable order determining method which is convenient for expressing all logical functions by a common input variable order becomes important. As described above, it is important to be able to represent all logic functions in the same input order, but in the conventional input variable determination method, a one-output logic circuit was targeted. When this is applied to a multi-output logic circuit, it is necessary to virtually treat it as a one-output logic circuit. In other words, a one-output gate for all outputs is virtually provided, and the output of the virtual gate is used as the output of the logic circuit to determine the order of input variables. The input variable order determination method of can be applied. A case of determining the order of input variables in the conventional technique for the logic circuit of FIG. 3 will be described. Since the logic circuit of FIG. 3 has two outputs, a virtual 2-input 1-output gate G that receives these outputs is used.
7 and its output is a virtual output X (Fig. 1
3). When the input side is searched from the virtual output X with depth priority, X → G7 → G3 → G1 → A → G1 → B → G1 → G3
→ G2 → C → G2 → D → G2 → G3 → G7 → G6 → G4
→ E → G4 → G6 → G5 → F → G5 → G6 → G7 → X Of these, if the inputs are ordered in the searched order, the resulting input variable order is A,
B, C, D, E, F. As can be seen from this result, in the conventional technique, regarding the output Y searched first among the gates (corresponding to the original outputs G3 and G6) virtually connected to the input of the gate G7, , The same result as when the output variables are ordered by the input alone is obtained, but for the gates (original output Z) searched after the second, the input (E , F), the input is to be ordered at the lowest rank at that time. This does not mean that the second and subsequent outputs are well ordered. On the other hand, design verification of a logic circuit using such a binary decision graph is performed by checking whether or not the two logic circuits are logically equivalent. For example, if you design a new type of carry-look-ahead adder and find that it is logically equivalent to a ripple-carry adder that you know to be correct, then the carry-look-ahead adder is correct as an adder. This means that the design has been verified. The determination as to whether they are logically equivalent is made by considering a logical function having an input as a variable for each output in two logical circuits. Two logic circuits can be determined to be logically equivalent if all corresponding output pairs in the two circuits have the same logic function. To determine if the logical functions of one output pair are the same, these logical functions are represented by a BDD. Since the binary decision graph has the property that it has the same shape if the expressed logical functions are the same, it is possible to judge the equivalence of the logical functions using this.
The binary decision graph also has a property that the number of required nodes greatly changes depending on the input variable order as described above. Due to this property, in the verification of the logical equivalence of the logic circuit having a plurality of outputs, the method of deciding the order of the input variables is 2
There is a street. (1) The input variable order of the binary decision graph expressing the output logical function is made common to all outputs. (2) The input variable order of the binary decision graph expressing the output logical function is determined for each output. These two methods include
Each has its strengths and weaknesses. Processing time can be shortened by making the input variable order common to all outputs. In order to calculate the logical function of the output, it is necessary to calculate the logical function for all of the gates needed to produce the output signal. In general, a gate required to calculate a logical function of one output is often required to calculate a logical function of another output. If the order of input variables is common, this gate can be processed once, but if it is different for each output, it will be necessary to calculate each time. For this reason, if the input variable order is common, each gate needs to be processed only once, and the calculation time can be shortened. On the other hand, from the viewpoint of the number of nodes, it is better to decide the order of input variables individually for each output than to make the order of input variables common to all outputs.
As the degree of freedom in selection increases, the number of nodes decreases. If the number of nodes becomes too large, it may not be possible to perform verification. Therefore, the range applicable to verification is wider when the input variable order is determined individually.

[0003]

As described above, the conventional input variable determination method is intended for a logic circuit having one output, and in the case of a circuit having two or more outputs, all outputs are output. This is dealt with by virtually thinking about the gate.
However, in this method, when actually applied to the circuit C7552 of the ISCAS85 benchmark circuit, the number of nodes can be represented by selecting a good input variable order. It was reported in Refs. [2] and [3] that all outputs could not be represented by a binary decision graph. Further, the two conventional methods for determining the order of input variables in the verification of logical equivalence of a logic circuit having a plurality of outputs have advantages and disadvantages, respectively. The method of using a common input variable order for all outputs has a short processing time but narrows the application range of the circuit. On the other hand, when the input variable order is individually determined, the application range of the circuit is wide, but the processing time is long. An object of the present invention is to provide a binary decision graph input variable order decision device for a multi-output logic circuit, which can represent a binary decision graph with a smaller number of nodes than the conventional input variable order decision method.
It is to provide a method for determining the order of input variables for a minute decision graph . A further object of the present invention is to provide a logic circuit design verification method in which the circuit application range is equivalent to the case of individually determining the input variable order, and the processing speed is faster than the case of individually determining the input variable order. It is in.

[0004]

In order to solve the problem] was to achieve the above purpose
Therefore, the first feature of the present invention is (a) a logic that outputs a plurality of signals.
The input variable order when the circuit is represented by a binary decision graph
A way for a computer to decide,
Output priority determining means determines priority of multiple outputs
And (b) for one-output logic function of computer
Input variable order determination means, each input for multiple outputs
The step of determining the variable order, and (c) the computer
The input variable order merging method corresponds to the first ordered set.
The second is the input variable order determined for each output.
Of merging the ordered set of to the first ordered set
And prioritize this merge process for all outputs
Repeated in order from the highest rank, and obtained the first ordered
The order of the input variables in the set for all outputs
With input variable order step and with second order
In the process of merging the sets into the first ordered set,
The first of the input variables included in the second ordered set
First input variable not included in ordered set and first order
The second input variable included in the attached set is the second ordered
The first ordered set when adjacent in
The first input variable and the second input variable are adjacent to each other.
And insert the first input variable into the first ordered set
Binary decision graph for ordering Input variable order determination method
That is the summary. The second feature of the present invention is (a) a plurality of
When expressing a logic circuit with an output in a binary decision graph
Is a way for the computer to determine the input variable order of
(B) The output priority determining means of the computer is
Prioritize multiple outputs and multiple selected internal signals
Step and (c) for one-output logic function of computer
Input variable order determination means
Steps that determine the order of each input variable
And (d) computer input variable order merging means
Each output and internal signal corresponding to the first ordered set
A second ordered collection that is the input variable order determined for
The merge is merged into the first ordered set.
Merge processing prioritized for all outputs and internal signals
Repeated in order from the highest rank, and obtained the first ordered
The input variables contained in the set for all outputs
With input variable order step and with second order
In the process of merging the sets into the first ordered set,
The first of the input variables included in the second ordered set
First input variable not included in ordered set and first order
The second input variable included in the attached set is the second ordered
The first ordered set when adjacent in
The first input variable and the second input variable are adjacent to each other.
And insert the first input variable into the first ordered set
Binary decision graph for ordering Input variable order determination method
That is the summary. Further, the first feature and the second feature of the present invention
Features are: (d) Determine the order of input variables for one-output logical functions
The input variables included in the second ordered set
Input variables that are not included in the first ordered set of
Or select them one by one in reverse order as the first input variable and
If the input variable of is the highest or the lowest, the first
The input variables of the top or bottom of the first ordered set
Position, otherwise the second ordered set
Immediately before or after this first input variable in
Use the variable as the second input variable and put it in the second ordered set.
First so that it is immediately after or just before the second input variable
Add the input variables of
May be. The third feature of the present invention is that (a) it has multiple outputs.
Input logic when expressing the logic circuit
A method of determining the numerical order by a computer,
The output priority determining means of the computer
And (b) computer input variables
The order deciding and merging means can output multiple outputs in order of priority.
In the input direction, the depth direction is prioritized and the logic circuit is traced.
Makes the gate the first ordered set when returning the route
Obtained after inserting and traversing all the multiple outputs
The order of the input variables contained in the first ordered set is
A step with the input variable order for all outputs
Prepared, when performing the process of tracing the route, the traced gate searches
If the gate was traced from the already output, the first
A game that has already traced the gate insertion position in an ordered set.
Immediately after, and otherwise in the first ordered collection
Immediately after the gate where the gate insertion position was previously inserted
Binary decision graph input variable order determination method
Is the gist. The fourth feature of the present invention is (a) multiple outputs
Input when expressing a logic circuit with
A method of determining the order of force variables by a computer,
(B) Multiple output priority order determination means for the computer
Power and a step for prioritizing multiple selected internal signals.
(C) Input variable order merge of computer
However, from multiple outputs and multiple selected internal signals,
In order of increasing order, priority is given to the depth direction in the input direction
When following a path and returning to the path that was followed
Insert into a set with all multiple outputs and multiple selections
The first ordered one obtained after the end of the internal signal
The order of the input variables contained in the set to all outputs
The input variable order with respect to
When performing the trace processing, the traced gate outputs the searched output and
And the gate traced from the selected internal signal
Already sets the gate insertion position in the first ordered set
Immediately after the traversed gate, otherwise, the first
The gate insertion position in the ordered set is
Immediately after a binary decision graph input variable order determination method
The main point is. The fifth feature of the present invention is that
(B) Display a logic circuit having multiple outputs in a binary decision graph
A device for determining the order of input variables when presenting,
An output priority determining means for determining the priority of the number output,
(B) Input variable order is determined for each output of multiple outputs
An input variable order determining means for a one-output logical function to be determined;
(C) to the output of each in correspondence to the set-out first with order
The second ordered set, which is the input variable order determined by
Perform the merge process on the first ordered set and merge
Processing for all outputs in descending order of priority.
Inputs included in the first ordered set obtained by returning
Make variable order the input variable order for all outputs
A second ordered set with input variable order merging means
In the process of merging into the first ordered set, the second order
The first ordered of the input variables included in the ordered set
The first input variable not included in the set and the first ordered collection
The second input variable contained in the
In the first ordered set when adjacent in
So that the first and second input variables are adjacent
Insert the first input variable into the first ordered set to order
It is a binary decision graph input variable order determination device.
Use as a summary. The sixth feature of the present invention is (a) a plurality of outputs
Input when expressing the logic circuit that it has with a binary decision graph
A device for determining the order of variables,
Output priority determination that determines the priority of the selected internal signal
Determining means, and (b) multiple outputs and multiple selected internal signals
, One-output logical function that determines the order of each input variable
Input variable order determining means for numbers and (c) first ordered collection
Corresponding to each output and internal signal.
The second ordered set, which is the input variable order, is
Perform the process of merging to the attached set,
Repeat for all outputs and internal signals in descending order of priority.
It is repeated and the entries included in the obtained first ordered set
Let the order of force variables be the input variable order for all outputs
A second ordered set, which comprises an input variable order merging means
In the process of merging
The first ordered variable among the input variables included in the ordered set
Input variable not included in the first set and first ordered
The second input variable contained in the set is the second ordered collection
In the first ordered set when adjacent in a match
So that the first and second input variables are adjacent
Insert the first input variable into the first ordered set
It is a binary decision graph input variable order decision device
And are the gist. The seventh feature of the present invention is (a) a plurality of outputs.
When expressing a logic circuit that has power in a binary decision graph
A device that determines the order of input variables and has priority over multiple outputs
Output priority determining means that determine the ranking, leaving a plurality (ii)
Force, the depth direction is superior to the input direction in descending order of priority.
When the logic circuit is traced first and the route that was traced back is returned,
To the first ordered set and all
Included in the first ordered set obtained after
The order of the input variables
And a means for determining and merging input variables in numerical order,
When the process of tracing is performed, the output of the traced gate has already been searched.
If the gate was traced from, the first ordered collection
Immediately after the gate that has already traced the gate insertion position in
, Otherwise, in the first ordered set
2 minutes with the gate insertion position immediately after the last inserted gate
Decision graph Input variable order determination device
It The eighth feature of the present invention is (b) a theory having a plurality of outputs
Input variable order when a logic circuit is represented by a binary decision graph
A device for determining a plurality of outputs and a plurality of selected
Output priority determining means for determining the priority of internal signals
And (b) from multiple outputs and multiple selected internal signals,
Priority is given to the depth direction in the input direction in descending order of priority.
When following a logic circuit and returning to the route that was followed, first place the gate
Insert into an ordered set of all multiple outputs and multiple
The first order obtained after finishing tracing from the selected internal signal
The order of the input variables contained in the ordered set is
Input variable order decision merge to be the input variable order for output
Means for tracing the route when performing the process of tracing the route.
Traced from the searched output and selected internal signals.
If it is a
Immediately after the gate that has already traced the gate insertion position, and other than
, Then the gate insertion position in the first ordered set
Enter the 2-minute decision graph immediately after the gate where the device was inserted
The gist is that it is a force variable order determination device.

[0005]

According to the present invention, the output priority is first determined by the output priority determining means. Also, for each output
The input variable order determining means for the one-output logical function determines each input variable order. The input variable order merging means determines the final input variable order for all the outputs based on the previously determined priority order of the outputs and the input variable order for each output. Further, the present invention first determines a common input variable order for all outputs. Attempts to generate a BDD for every output, in that input variable order. After the binary decision graph is generated, the two circuits compare the corresponding outputs. If a binary decision graph of all outputs can be generated, it can be executed in the same processing time as when the conventional input variable order is common to all outputs. When there are outputs for which the binary decision graph cannot be generated, a new common input variable order is determined for all or some of the signals at those outputs. Attempts to generate a binary decision graph for this order. If the binary decision graph cannot be generated at this time as well, the input variable order is determined for the set of outputs that could not be similarly generated,
Attempt to generate a binary decision graph. After that, the process is repeated until a binary decision graph can be generated for all outputs or no binary decision graph can be generated. When no new one can be generated, the order of input variables is determined for each output and an attempt is made to generate a binary decision graph. Output that cannot be generated even by this is not verifiable. Note that the fact that the binary decision graph cannot be generated here is determined due to factors such as the number of nodes exceeding the upper limit or the execution time exceeding the upper limit. If it is determined that the graph cannot be generated, the generation is interrupted. , So that we can move on to the generation of the next output.

[0006]

Embodiments of the present invention will be described with reference to the drawings. Book
The configuration of the binary decision graph input variable order determination device of the invention is
As shown in FIG. The present invention comprises an output priority order determining means 1, an output variable function input variable order determining means 2, and an input variable order merging means 3. The output priority determining means 1 determines the output priority when determining the input variable order. In general, in a multi-output logic function, a good input variable order for one output will not necessarily be a good input variable order for another output. Therefore, it is necessary to determine the output priority order for which output the good input variable order is set. The final input variable order for all outputs will be better for higher priority outputs. The output order determining means 1 of the present embodiment determines the output priority order such that the output having a larger number of gate stages from the input has a higher priority order. The one-output logical function input variable order determining means 2 determines an input variable order such that the number of nodes is reduced for one output among a plurality of outputs. This method utilizes the above-mentioned conventional technique or the like. The 1-output logic function input variable order determining means 2 of the present embodiment performs depth-first search from the output to the input, and orders the input variables in the searched order. The input variable order merging means 3 merges all the input variable orders for each output determined by the one-output logical function input variable order determining means 2 to determine a final input variable order for all outputs. The merging at that time is performed based on the priority order determined by the output priority order determining means 1. Ordering is performed in order from the output with the highest priority, based on the input variable order for the output. Input variables are merged as follows. First, the input variable order for the output with the highest priority is stored as it is as the final input variable order. The order being preserved here means that the relative order is preserved. For example, even if the order of A, B, C becomes A, P, B, Q, C, A, B, C
That order is preserved. Next, the input variable order for the output of the second priority is merged with the already determined input variable order. Inputs that were unordered in the first output (irrelevant to the first output) are reordered by merging. Ordering a newly ordered input variable at any position in the already ordered input variable order has no adverse effect on the input variable order determined for the higher priority output. The newly ordered input variables are irrelevant to the higher-priority output, and irrelevant input variables do not affect the binary decision graph for that output, no matter how they are ordered. is there. Therefore, the newly ordered input variables may be ordered so as to favor the output with the highest priority among the outputs affected by the input variable. Therefore, the newly ordered input variables are ordered so that they retain their order in the input variable order for the highest priority output that they affect. That is, the input variables are ordered so as to be adjacent to the input variable to be newly ordered. For example, let A, B, C, and D be the input variables that are already ordered in this order by the output with a high priority, and E be the input variable that is newly ordered. If the input variable order for the highest priority output that affects E is A, B, E, C, the overall input variable order is A, B, E, C, D.
To be merged. The same applies to the output of the third and subsequent priorities. First Embodiment FIG. 2 shows a detailed flow chart of the input variable order merging means 3 in the first embodiment. The flowchart of FIG. 2 will be described in detail using the logic circuit shown in FIG. Before the processing of FIG. 2 is started, the output priority determining means 1 sets Y, Z.
It is assumed that the priority order of is obtained. Further, with respect to Y by the input variable order determining means 2 for 1-output logical function,
It is assumed that the input variable order of A, B, C, D has been obtained, and the input variable order of B, E, D, F has been obtained for Z. When the flowchart of FIG. 2 is executed, the variable VL
The result is obtained as a set of ordered input variables. First, in step S101, VL = φ, OUT = {Y,
Z} is initialized. Next, step S102.
Then, Y is selected as o. Then, step S103
Then, the input variable order for o is put into VL1, and VL
1 = {A, B, C, D}. Next, step S10
In 4, A is selected as v. Next, since v is the highest in VL1 (S105), v is inserted at the beginning of VL. As a result, VL = {A}. Since there is a variable in VL1 that is not ordered (S108), S
Return to 104. In S104, the highest order variable B in VL1 which is not yet ordered is selected as v. Since v is not the highest level in VL1 (S105), S107
go to. The variable in the upper order immediately before v in VL1 is A, so w becomes A. W in VL
If v is inserted immediately after, VL = {A, B}. After that, S104 to S108 are also applied to the remaining variables of VL1.
Is applied, VL = {A, B, C, D}. Next, in S109, when the processed o is removed from OUT, OUT = {Z}. Since OUT is not an empty set (S110), the process returns to S102 again. O = in S102
In Y and S103, VL1 = {B, E, D, F}. Next, in S104, the highest variable not in VL is selected in VL1 and becomes E, which is v. Here B is not selected because it is already ordered in the VL. Since v is not the highest in VL1 (S105), the process proceeds to S107. The variable immediately before v in VL1 is B, so v
Order immediately after B in VL. As a result, VL =
It becomes {A, B, E, C, D}. Similarly, for the remaining variables of VL1, if S104 to S108 are processed, VL = {A, B, C, D, F}. In S109, OUT = φ, and in S110, it is determined to end. Thus, the input variable order is determined to be A, B, E, C, D, F. When the binary decision graph of the output of the logic circuit of FIG. 3 is created in the input order obtained in the flow chart of FIG. 2 explained above, it becomes as shown in FIG. 4, and there are a total of 8 nodes. On the other hand, in the prior art, the input variable order is A, B, C, D,
E and F are obtained. When the binary decision graph of the output of the logic circuit of FIG. 3 is created in this variable order, it becomes as shown in FIG. 5, and there are 10 nodes in total. As a result, it can be seen that the present invention can generate a binary decision graph with a smaller number of nodes than the conventional one. Second Embodiment Next, FIGS. 6 to 8 show flowcharts of the second embodiment. 6 to 8, the one-output logic function input variable order determining means 2 and the input variable order merging means 3 are combined so that the final overall order is determined while determining the input variable order for each output. The order of input variables is also decided at the same time. First, the outline of this flowchart will be described. In this flowchart, the input is treated as a 0-input 1-output gate and the output is treated as a 1-input 0-output gate. The final input variable order is obtained in the variable VL as an ordered set. After putting all the gates in the VL in order, not just the input gates,
Finally, the gates other than the input are deleted. This is done in order not to search the gate that has already been searched and to obtain a good input variable order. Since each gate is searched only once,
It can be executed more efficiently than the above-mentioned embodiment, and can be executed with the same efficiency as the prior art. The variable last indicates where in the VL the gates are ordered, and is inserted immediately after the gate pointed to by last. Also, each gate is
It has a variable from to indicate from which output it was searched. last usually points to the gate that was just inserted, but when it encounters a gate that was already searched during the search and was not searched from the output it is currently searching, it will point this gate to this gate. It is supposed to do. This searched gate is ordered after the input that can be reached from this gate, so
We will now order the inputs that we can reach after these previously searched inputs. By doing so, it is possible to determine a good input variable order for low-priority output without changing the input variable order decided from high-priority output. Also for this example,
This will be described in detail using the logic circuit of FIG.

First, in S201, each variable is initialized. Next, in steps S202 to S205, one by one is selected in order from the output with the highest priority, and it is set to o, and the procedure order
Call (o). Set last to nil before calling. In the circuit of FIG. 3, first, order (Y)
Is called. When the procedure order (g) is called, the argument g becomes Y (S301). Since Y has not been searched (S302), Y has been searched (S3).
03), Y from is set to Y (S304). The gate connected to Y is G3, so FANIN = {G
3} (S305). FA in S306 to S309
The procedure order is called for all gates in NIN. Here, order (G3) is called. In order (G3), order (Y)
As in the case of, the processing from S301 to S305 is performed, and in S306 to S309, order (G1) is called. Similarly, in the order (G1), ord
er (A) is called. A in order (A)
Since there is no input of, the process proceeds to S310. last is nil
Therefore, VL = {A}. or as last = A
Return from der (A), S of order (G1)
308 ends. Since the gate B connected to the input of G1 remains, order (B) is called. order
In (B), since B is not input, the process proceeds to S310. Since last is A, B is inserted immediately after A, and VL = {A, B}. As last = B,
Return from order (B), order (G1)
S308 ends. Since there is no gate left connected to the input, the process proceeds to S310. Since last is B, G1 is inserted immediately after B. As a result, VL = {A, B, G1}. After that, the same process is performed until the order (Y) in S203 of FIG. 6 is completed, and at that stage, VL = {A, B, G1,
The gates included in C, D, G2, G3, Y} and VL are all Y. In S204, OUT
From Y is removed, and OUT = {Z}. last is n
is set to il (S202a), procedure order
(Z) is called (S203). After that, in the same way as before, the order (G
6) is called, and at S308 of order (G6), o
rder (G4) is called, and in step S308 of order (G4), order (B) is called. Since B has already been searched (S302), the process proceeds to S314. Since B was previously searched from Y, the condition of S314 is not satisfied. Therefore, last is updated to B in S315 and the procedure order (B) to order (G4) in S308 is updated.
Return to. Here, by updating last to B,
Subsequent ordering will occur immediately after B. Order (E) is called for the remaining gate E connected to the input in order (G4) (S30).
8). In order (E), since E has not been searched and there is no input, the process proceeds to S310. Since last is B (S310), E is inserted immediately after B in VL. As a result, VL = {A, B, E, G1,
C, D, G2, G3, Y}. Update last to E and change from order (E) to order (G4) S30
Return to 8. Since there is no gate left to connect to the input, insert G4 right after E in VL and set order (G
It returns to S308 of 6). Similarly, order (G
5), order (D), order (F) are called and processed, and finally order (Z) ends, VL = {A, B, E, G4, G1, C, D, F ，
G5, G6, Z, G2, G3, Y}. order
The process returns from (Z) to S203. Since OUT = φ, (S
204, S205) and S206, if gates other than inputs are excluded from VL, the final input variable order is VL.
= {A, B, E, C, D, F} is obtained. This result is the same as the result obtained when the first embodiment of FIG. 2 is applied, but the result of applying the first embodiment and the result of applying the second embodiment are , Not always a match. In the above explanation, when there are multiple gates connected to the input of a certain gate, which gate to search from is not mentioned, but in reality, (1) the number of gate stages from the input to the gate Since there are many, I will search first. (2) The search is performed from the one having the largest maximum fan-out number of the input traced from the gate. (3) It searches first from the one having the largest number of inputs that can be traced from the gate. (4) If there is a gate that has already been searched, that gate is given priority. A method of deciding the search order such as
These are used alone or in combination. They are,
It can also be used to determine output priority. FIG. 9 shows a conventional technique for the ISCAS85 benchmark circuit.
The result (the number of nodes of the binary decision graph when the determined input variable order is used) when the first embodiment and the second embodiment are applied is shown. As can be seen from this, the number of nodes is generally smaller when the first embodiment or the second embodiment is applied than when the conventional technique is applied. Especially for C2670 and C7552,
In the prior art, the number of nodes was too large to create a binary decision graph, but when the first or second embodiment is applied, it can be expressed with a small number of nodes. Recognize. From this, in the conventional technology,
With the present invention, a circuit that cannot generate a binary decision graph can be represented, and thus the present invention expands the scope of application of the technique using the binary decision graph. The input variable order determining method for the multi-output logic circuit described above is also effective for determining the input variable order for the 1-output logic circuit. When the conventional technique is applied to the logic circuit of FIG. 10, A0, B0, A1, B1, C0, C
An input variable order of 1 is obtained, and the number of nodes required at that time is 14. On the other hand, if the present invention is applied with virtual outputs X and Y as shown in FIG. 11 and the output priority order is X, Y, and Z, A0, C0, B0, A1, C1,
An input variable order of B1 is obtained, and the required number of nodes at that time is 9. It can be seen that the number of nodes when using the input variable order obtained by applying the present invention is smaller than the number of nodes when using the input variable order obtained by the conventional technique. Third Embodiment Finally, FIG. 1 shows a flowchart of a third embodiment of the present invention.
2 shows. This embodiment is roughly divided into S401 to S4.
07, and S408 to S412. The part of S401 to S407 is a part that tries to generate and verify a binary decision graph by using a common input variable order for as many outputs as possible. S408 ~
The part of S412 is as a last resort when the binary decision graph is unlikely to be generated with the common input variable order.
The remaining output that cannot be generated by the binary decision graph is a part in which the order of input variables is individually determined and the binary decision graph is generated and verified. First, S401-
The part of S407 will be described in detail. The set S represents a set of outputs for which the binary decision graph has not yet been generated and has not been verified. At the very beginning, S is set as all outputs (S401). Next, in S402, a common input variable order for the outputs contained in S is determined. In S403,
Attempts to generate a BDD for the outputs contained in S using the input variable order determined in S402. At this time, if the number of nodes exceeds the upper limit, the process for the output is interrupted and an attempt is made to generate a binary decision graph for the next output. When the binary decision graph is successfully generated, it is determined whether the binary decision graphs for the corresponding outputs of the two circuits to be compared have the same shape, and if they are the same, it is determined that they are logically equivalent. Otherwise, it is determined that they are not equivalent. The set of outputs for which the binary decision graph has been generated in S404 to S406 is set as T, and the outputs contained in S to T are excluded. The output that has not yet been able to generate the binary decision graph remains in S.
Attempt to generate and verify a binary decision graph from 401. If T is an empty set, it means that the binary decision graph could not be made for any output in the input variable order for S. In this embodiment, S408 to S412
The input variable order is determined one by one for all the outputs included in (S409), and an attempt is made to generate and verify a binary decision graph (S410). By doing so, the range of application equivalent to the conventional method of individually deciding the order of input variables and processing is guaranteed. When the processing is completed for all the outputs of S, the processing of this flowchart is completed regardless of whether the binary decision graph is successfully generated.
This means that the output for which the binary decision graph could not be generated could not be verified. In the third embodiment,
It is designed to process a plurality of outputs as much as possible, and since it is not possible to process them collectively, the process shifts to using individual input variable order (S408 to S412). Alternatively, the processing may be shifted to the processing using the input variable order of.

[0008]

By using the present invention, the required number of nodes in the binary decision graph is significantly reduced as compared with the case of using the conventional method, and the storage capacity for processing the binary decision graph is reduced. Inputting a 2-minute decision graph that can reduce processing time
Number order determination device and binary decision graph input variable order determination method
Can provide the law . Further, according to the present invention, there is also a circuit that can generate a binary decision graph by using the variable order according to the present invention, while a circuit that could not generate the binary decision graph in the conventional method. Yes, the range of circuits to which the binary decision graph processing can be applied is expanded. Further, according to the present invention, in the logic circuit design verification using the binary decision graph, the processing can be performed at high speed without narrowing the range of applicable circuits.

[Brief description of drawings]

FIG. 1 shows the configuration of a 2 decision graph input variable order determination device.
It is a configuration diagram.

FIG. 2 is a flow chart of the first embodiment.

FIG. 3 is an example of a logic circuit.

FIG. 4 is a binary decision graph according to an input variable order according to the present invention.

FIG. 5 is a binary decision glass with input variable order according to the prior art.

FIG. 6 is a flowchart of the second embodiment.

FIG. 7 is a flowchart of a procedure order.

FIG. 8 is a flowchart following FIG.

FIG. 9 is a result applied to a benchmark circuit.

FIG. 10 is an example of a logic circuit.

FIG. 11 is a logic circuit to which a virtual output is added.

Flowchart der of the third embodiment of the present invention; FIG
It

FIG. 13 is a logic circuit to which a virtual gate is added.

[Explanation of symbols]

1 Output priority order determination means 21 Input variable order determining means for 1-output logical function 3 Input variable order merging means

Claims (14)

(57) [Claims] 1. A binary circuit for determining a logic circuit having a plurality of outputs.
The computer decides the order of the input variables when expressing it roughly.
A method of determining the output priority of the computer,
Determining the order of priority of input variables for computer one-output logic function
Determines the order of each input variable for the multiple outputs
And the input variable order merging means of the computer,
The second ordered with the input variable order determined for the force
Perform the process of merging the sets into the first ordered set.
The process of merging the
Iterate in ascending order to obtain the first ordered set
Change the order of the included input variables to the input variables for all outputs.
The step of providing a numerical order, the second ordered collection
In the process of merging a combination into the first ordered set,
Of the input variables included in the second ordered set , the first
The first input variable not included in the ordered set and the first order
The second input variable included in the ordered set is the second order
The first ordered set when adjacent in the attached set
The first and second input variables are adjacent in
Insert the first input variable into the first ordered set, like
Decision graph input variable characterized by sequential ordering
Order determination method. 2. A binary circuit for determining a logic circuit having a plurality of outputs.
The computer decides the order of the input variables when expressing it roughly.
Method, The output priority determining means of the computer outputs the plurality of outputs.
And a step for prioritizing a plurality of selected internal signals.
And Input variable order determining means for one-output logic function of computer
For the multiple outputs and the selected internal signals
And determining the order of each input variable, The input variable order merging means of the computer outputs the output and
For each of the internal signals The input variable order determined for
Merges the second ordered set into the first ordered set
And perform this merging process on all the output and
And the internal signals are repeated in the order of higher priority.
Input variable included in the obtained first ordered set
A sequence whose order of numbers is the order of input variables for all outputs.
And the second ordered set to the first
In the process of merging into an ordered set, the second ordered
Of the input variables included in the set, the first ordered set
The first input variable that is not included and the first
And the second input variable is in the second ordered set
When they are adjacent to each other in the first ordered set
So that the input variable and the second input variable are adjacent,
Insert and order the input variables in the first ordered set.
A binary decision graph input variable order determining method characterized by: 3. The second ordered set is converted into the first ordered set.
The process of merging into an ordered set is the second ordered set.
Of the input variables included in the first ordered set
Select input variables that cannot be filled one by one in forward or reverse order
As the first input variable, the first input variable is the highest
If it is the lowest, set the first input variable to the first
Insert at the top or bottom of the ordered set of
Otherwise, this first in the second ordered set
Input the variable immediately before or after the input variable of
A second input variable in the first ordered set as a variable
Set the first input variable to be immediately after or just before
To insert into the ordered set of
The binary decision graph according to claim 1 or 2, characterized in that
Input variable order determination method. 4. A step for determining the order of each of the input variables.
Traces the logic circuit, giving priority to the depth in the input direction.
Order the input variables in the order in which
The method according to any one of claims 1 to 3, characterized in that
Minute decision graph Input variable order determination method. 5. A step for determining the order of each of the input variables.
Input processing for each input variable order, and the input
The step of merging variable orders is the step of input variable order
Claim that is characterized by performing the process of merging
The binary decision graph input variable described in any one of 1 to 4.
Number order determination method. 6. A binary circuit for determining a logic circuit having a plurality of outputs.
The computer decides the order of the input variables when expressing it roughly.
Method, The output priority determining means of the computer outputs the plurality of outputs.
Determining the priority of The input variable order determining and merging means of the computer is the plurality of
From the output, in the order of the above-mentioned priority, depth direction
Trace the logic circuit, giving priority to the direction, and return to the traced path.
When inserting the gate into the first ordered set,
The first ordering obtained after finishing tracing from the plurality of outputs
The order of the input variables contained in the
The order of input variables for
When performing the process of tracing a route, the gate that was traced has already been searched.
If the gate was traced from force, the first ordered
The gate insertion position in the set of the gates already traced
Immediately after, otherwise in the first ordered set
The gate insertion position in the
Binary decision graph input variable order determination method characterized by
Law. 7. A binary circuit for determining a logic circuit having a plurality of outputs.
The computer decides the order of the input variables when expressing it roughly.
Method, The output priority determining means of the computer outputs the plurality of outputs.
And a step for prioritizing a plurality of selected internal signals.
And The input variable order determining and merging means of the computer is the plurality of
From the output and the plurality of selected internal signals, the priority order
In the order of increasing
When following the circuit and returning to the route that was followed, the gates are in the first order.
Insert into an ordered set and select all the outputs and the selected
The first ordered collection obtained after finishing the internal signal
The order of the input variables contained in the
The step of setting the input variable order to
When performing a process that
If the gate was traced from the selected internal signal,
The gate insertion position in the first ordered set has already been
Immediately after the traversed gate, otherwise, the first
The gate insertion position in the ordered set is
Input of a binary decision graph characterized by being immediately after
Variable order determination method. 8. An apparatus for determining an input variable order when a logic circuit having a plurality of outputs is represented by a binary decision graph, and an output priority order determining unit for determining a priority order of the plurality of outputs.
Stage and the input variable order is determined for each output of the multiple outputs
Input variable order determining means for 1-output logical function, and an input variable order determining means for each output
A process that merges the second ordered set into the first ordered set.
And merge this merge process for all outputs.
Repeated in descending order of priority, the first order obtained
The order of input variables in the ordered set to all outputs
Equipped with input variable order merging means to be the input variable order for the
The second ordered set to the first ordered set
In the process of merging into
Input variables that are not included in the first ordered set
One input variable and the second in the first ordered set
If the input variables and are adjacent in the second ordered set
First input variable and the first input variable in the first ordered set.
Set the first input variable to the second so that the two input variables are adjacent.
Characterized by inserting and ordering in one ordered set
A binary decision graph input variable order determination device. 9. A binary circuit for determining a logic circuit having a plurality of outputs.
It is a device that determines the order of input variables when expressed roughly.
I mean Priority of the plurality of outputs and the plurality of selected internal signals
Output priority determining means for determining, For the plurality of outputs and the plurality of selected internal signals,
Input variables for one-output logic functions that determine the order of each input variable
A numerical order determining means, Input determined for each of the output and the internal signal
The second ordered set, which is a variable order, is
Perform the process of merging to the set, and perform all this merging process.
The priority of the output and the internal signal of
In the first ordered set obtained.
Input variable order for all outputs
And an input variable order merging means for setting the order,
The process of merging an ordered set into the first ordered set
, The input variables in the second ordered set
The first input variable that is not included in the first ordered set
And a second input variable contained in the first ordered set
But in the second ordered set smell First when they are adjacent
The first input variable and the second input variable in the ordered set of
Order the first input variable in the first order so that the numbers and
Dichotomy characterized by inserting into a set and ordering
Graph input variable order determination device. 10. The input variable order merging means comprises:
The first of the input variables included in the second ordered set
Forward or reverse input variables that are not included in the ordered set
One by one as the first input variable, and the first input variable
If the force variable is highest or lowest, then the first
The input variables of the top or bottom of the first ordered set
Position, otherwise the second ordered set
Immediately before or after this first input variable in
Use the variable as the second input variable and put it in the first ordered set.
First so that it is immediately after or just before the second input variable
Insert the input variables of into the first ordered set and order
According to claim 8 or claim 9, characterized in that
The binary decision graph input variable order determination device described above. 11. Order determination of input variables for the one-output logic function
The determining means prioritizes the depth in the input direction to configure the logic circuit.
The input variables can be ordered in the order that they are followed and the paths that are followed are returned.
11. The method according to any one of claims 8 to 10, characterized in that
Binary decision graph input variable order determining device. 12. The input variable order merging means is an input variable
The process of determining the numerical order and the input variable order merging means are
A process of merging input variable orders for the plurality of outputs,
12. The method according to any one of claims 8 to 11, characterized in that
The binary decision graph input variable order decision device according to item 1
Place 13. A logic circuit having a plurality of outputs is divided into two.
A device that determines the order of input variables when expressed in a graph
There Output priority determining means for determining the priority of the plurality of outputs
Dan, From the multiple outputs, the input direction is in the descending order of priority.
To the depth direction, tracing the logic circuit,
Insert the gate into the first ordered set on the way back,
First obtained after all the multiple outputs have been traced
The order of the input variables contained in the ordered set of
Input variable order, which is the input variable order for all outputs
When the processing for tracing the route is provided, the constant merging means is provided.
The gate that was traced was the gate traced from the searched output
If in the first ordered set Gate insertion position
Is immediately after the gate already traced, and in other cases
Is the gate insertion position in the first ordered set.
Two minute decision, characterized by being immediately after the inserted gate
Graph input variable order determination device. 14. A logic circuit having a plurality of outputs is divided into two.
A device that determines the order of input variables when expressed in a graph
There Priority of the plurality of outputs and the plurality of selected internal signals
Output priority determining means for determining, From the plurality of outputs and the plurality of selected internal signals, the
Priority is given to the depth direction in the input direction in descending order of priority.
When following the logic circuit and returning to the route that was followed,
Insert into the first ordered set, with all the multiple outputs
Obtained after finishing tracing from the plurality of selected internal signals
The order of the input variables contained in the first ordered set
Input variables where is the input variable order for all outputs
An order determining and merging unit, and performs processing for tracing the route.
In this case, the output traced by the traced gate and the selected internal
If the gate was traced from the signal, the first ordering
The gate that has already been traced the gate insertion position in the set
Immediately after, otherwise the first ordered set
Immediately after the gate where the gate was inserted in
Binary decision graph input variable order determination characterized by
apparatus.