JP3379765B2 - Control device and method for nonvolatile memory - Google Patents

Description

Detailed Description of the Invention

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a control device and method for a non-volatile memory, such as a flash EEPROM, in which erasing and writing are completed by repeating erasing and writing operations a plurality of times in the same memory area.

[0002]

2. Description of the Related Art A flash EEPROM (for example, M5M28F101P manufactured by Mitsubishi Electric Corporation) is a non-volatile memory that can be electrically written and collectively erased.
Compared with M, it has excellent advantages such as lower bit cost and faster program operation. Therefore, its application to electronic computers and various electronic devices is being studied.

By the way, in the case of writing data in the flash EEPROM, due to the characteristics of the element, accurate data writing is realized by performing the writing process a plurality of times on the same memory area.

14 to 16 show a flash EEPR.
FIG. 14 shows a conventional procedure for writing target data in the OM. First, in FIG. 14, data “1” is written in the entire memory area, then erase is performed in FIG. 15, and finally the target data is written in FIG. I am doing it. In this way, the data "1" is written in all the memory areas before the erasing because in the flash EEPROM, if an extra erasing pulse is applied to the already erased "0" area due to the characteristics of the chip, This is because a problem (over-erasure) that causes deterioration of the chip occurs.

As shown in FIG. 14, "1" is written to all bits of the first 1 address (1 byte) of the flash EEPROM by a write command (step S1), and the write execution time required by the characteristics of the device is obtained. After WRc (10 μs) has passed (step S2), it is confirmed by the verify command whether or not the one address has been correctly written.
(Step S3). Then, after the confirmation execution time WVc (6 μs) required for the characteristics of the element has elapsed (step S4), it is determined whether or not a mistake has occurred (step S5). If a mistake has occurred, step S1 Return to and repeat the write operation. If no mistake has occurred, it is judged whether or not it is the last address (step S6), and the process proceeds to the next address.
(Step S7), the above series of procedures are repeated until the final address is reached.

Next, as shown in FIG. 15, flash EEPRO
An erase command (erase command) is issued to M (step S8), and the erase execution time ERc required due to the characteristics of the device.
After the elapse of (9.5 ms) (step S9), it is confirmed whether or not the first one address has been erased (step S10). After the confirmation execution time WVc (6 μs) has elapsed (step S1
1) It is determined whether or not a mistake has occurred (step S12). If a mistake has occurred, the procedure returns to step S8 and the erase operation is repeated. If no error has occurred, it is judged whether or not it is the last address (step S13), the process proceeds to the next address (step S14), and the above series of procedures is repeated until the last address is reached.

Then, as shown in FIG. 16, a flash EEP is performed.
The target data is written to the first 1 address (1 byte) of the ROM by the write command (step S15), and after the write execution time WRc (10 μs) has passed (step S16), the 1 address is correctly verified by the verify command. It is confirmed whether the data has been written (step S17). And
After the confirmation execution time WVc (6 μs) has elapsed (step S18), it is determined whether or not a mistake has occurred (step S19). If a mistake has occurred, the process returns to step S15 to repeat the write operation. If no error has occurred, it is judged whether or not it is the last address (step S20), the process proceeds to the next address (step S21), and the above series of procedures is repeated until the last address is reached.

[0008]

However, the conventional erasure /
In the writing method, in each of the writing in FIG. 14, the erasing in FIG. 15 and the writing in FIG. 16, a confirmation is made every time an erasing or writing operation is performed, and the next erasing or writing operation must be performed after the confirmation execution time has elapsed. Therefore, there is a problem that it takes a long time before the target data is accurately written in the flash EEPROM.

For example, a software overhead time WRo = 10 at the time of writing
μs Write operation execution time WRc = 10 μs Number of repetitions required to complete writing (actual value) Nw =
10 Software overhead time WV at confirmation after writing
o = 10 μs Confirmation operation execution time after programming WVc = 6 μs Software overhead time E Ro = 10 μs erase operation execution time ERc = 9500 μs Number of repeats required to complete erase Ne = 1
0 Software overhead time EVo at confirmation after erasure
= 10 μs Execution time of confirmation operation after erasing EVc = 6 μs If chip size CS = 128 × 1024 bytes, time T1 required for writing in FIG. 14, time T2 required for erasing in FIG. 15, and time required for writing in FIG. T3 is represented by Equations 1, 2, and 3, respectively. The number of mistakes in step S19 of FIG. 16 corresponds to the writing ability value Nw, and the number of mistakes in step S12 of FIG. 15 corresponds to the erasing ability value Ne.

[0010]

[Equation 1] T1 = (WRo + WRc + WVo + WVc) × CS × Nw = 47.2 sec

[Equation 2] T2 = {ERo + ERc + (EVo + EVc) × 1/2 × C
S} × Ne = 10.6 sec

[Equation 3] T3 = (WRo + WRc + WVo + WVc) × CS × Nw = 47.2 sec

Therefore, the total time required to write the target data to the flash EEPROM is 105 in total.
Seconds and longer. The object of the present invention is to perform confirmation operation more than before.
It is to realize effective erasing and writing of a nonvolatile memory by reducing the effective time and overhead time associated with repetition .

[0012]

A non-volatile memory control device according to the present invention is a non-volatile memory in which erasing or writing is completed by repeating erasing or writing operations a plurality of times in the same memory area. In the control device, the erasing ability value, which is the number of repetitions of the batch erasing operation until the erasing of all memory areas is completed, and the write operation until the writing of one address into the memory area is completed, in the nonvolatile memory. And a means for storing the erase ability value and the write ability value in the non-volatile memory, and the erase ability value and the write ability value from the non-volatile memory. and reading <br/> be means leaving viewed in the erasure of the entire memory area of the nonvolatile memory, at least the erasing ability values times without confirmation operation And a means for repeatedly performing the batch erasing operation, and a means for repeatedly writing the target data to the nonvolatile memory at least the number of times of the write capability value without performing a confirming operation. Is characterized by. Further, the nonvolatile memory control device according to the present invention is configured such that, in the above device, the write capability value is the maximum value of the number of repetitions of the write operation until the writing to the memory area of one address is completed among all the addresses. It is what Furthermore, the nonvolatile memory control device according to the present invention, in the above-mentioned device, performs a batch erase operation on all memory areas after performing a write operation on all memory areas, and whether an erase error occurs in order from the first address. If the erase error occurs, the erase ability value is determined by returning to the batch erase operation again until it is determined that the erase error has not occurred at the last address. The writing ability value is determined by sequentially repeating the writing operation in the memory area for each address until it is determined that the writing error has not occurred.

The non-volatile memory control method according to the present invention is a non-volatile memory control method in which erasing or writing is completed by repeating erasing or writing operations a plurality of times in the same memory area. , An erasing ability value which is the number of repetitions of the batch erasing operation until the erasing of all the memory areas of the nonvolatile memory is completed, and 1
And a procedure for predetermining a write ability value, which is the number of times the write operation is repeated until writing of one address to the memory area is completed, and a procedure for storing the erase ability value and the write ability value in the nonvolatile memory. includes procedures <br/> way back to be read out of the erasing ability value and writing ability value from the nonvolatile memory in the erasing of the entire memory area of the nonvolatile memory, at least the without confirmation operation The procedure of performing the batch erasing operation by repeating the erasing ability value number of times is repeated at least the number of times of the writing ability value without writing the confirmation operation in writing the target data to the nonvolatile memory. It is characterized by performing procedures. Furthermore, in the method for controlling a nonvolatile memory according to the present invention, in the above method, the write capability value is the maximum value of the number of times of repeating the write operation until the writing to the memory area of one address is completed among all the addresses. It is what

[0014]

In the above control device and method, since the erasing ability value of the non-volatile memory is recorded and the entire memory area is erased, the batch erasing operation for all the memory area is performed at least the number of times of the erasing ability value without the confirmation operation. Only after that, confirmation of erasure can be performed. Since the erasing ability value is the number of times the batch erasing operation is repeated until the erasing of all memory areas is completed, this procedure achieves erasing of all memory areas with an extremely high probability. Therefore, the checking operation can be omitted as compared with the conventional method. further,
Since the writing ability value of the nonvolatile memory is recorded and written to each address, the writing operation can be repeated at least the number of writing ability values without the confirmation operation, and then the writing confirmation can be performed. Since the write ability value is the number of times the write operation is repeated until the writing of the memory area of one address is completed, the writing to each address is achieved with a high probability by this procedure. Therefore, the checking operation can be omitted as compared with the conventional method. It should be noted that when an erasing error or writing error occurs, it is necessary to perform the necessary procedure to complete the erasing or writing, but such a procedure is extremely unlikely.
In the above control device and method, the determined erasing ability value and writing ability value are stored in the non-volatile memory. Therefore, even if the power is turned off after the determination of these ability values and before the batch erasing operation and further the target data writing operation, these ability values are still stored in the nonvolatile memory. When the power is turned on again, the batch erase operation and the data write operation can be executed. Also, since to read <br/> out viewed from the non-volatile memory erasing ability value and writing ability value, by performing this treatment prior to batch erase operation of the non-volatile memory, which also performs batch erase operation ability The values can be saved without disappearing, and the batch erasing operation and the data writing operation based on these ability values can be performed. Furthermore, if the writing ability value is set to the maximum value of the number of repetitions of the writing operation until the writing of one address to the memory area is completed among all the addresses, the writing of all the addresses is achieved with an extremely high probability. It

[0015]

In the non-volatile memory control apparatus and method according to the present invention, the erase confirmation operation can be made smaller when the entire memory area is erased, and the write confirmation operation can be made smaller when writing to each address than in the conventional method. it can. That is, by shortening the execution time and overhead time required for the confirmation operation, erasing and writing can be performed faster than in the conventional method. Furthermore, since the erasing ability value and the writing ability value are given to each memory chip, it is possible to correspond to the characteristics of each memory chip.

Hereinafter, control of the non-volatile memory according to the present invention
An example of implementing the apparatus and method in a flash EEPROM will be described in detail.

The flash EEPROM (5) is, as shown in FIG.
The M (2), the RAM (3) and the I / O (4) are connected to the CPU (1), and the erasing / writing operation is controlled by the CPU (1).

FIG. 13 shows a CPU (1) and a flash EEPR.
More specifically, the connection state of the OM (5) is shown. The flash EEPROM (5) has a capacity of 128 Kbytes, and the CPU through the data lines D0 to D7 and the address lines A0 to A16. It is connected to (1). Also, CP
The address lines A17 to A19 of U (1) are connected to the various memories and the flash EEPROM (5) through the decoder (6) and select one memory to be written or read.

1 to 4 show the erasing ability in the present invention.
A series of procedures to determine the value and writing ability value (hereinafter,
This is called the "first step". ) , In which FIG. 1 shows a procedure of writing “1” to each bit of the entire memory area, and FIG. 2 shows a procedure of collectively erasing the entire memory area to determine the erase performance value Ne. 3 and 4 show a procedure for writing "1" in each bit of the entire memory area to determine the write capability value.

Further, FIGS. 5 to 5 show the target data of the present invention.
A series of procedures for writing data (hereinafter referred to as "second step")
Say. ), In which FIG. 5 and FIG.
14 shows a procedure for writing each bit "1" of the entire memory area, corresponding to FIG. 14 of the related art, and FIGS. 7 and 8 show a procedure for collectively erasing the entire memory area, corresponding to FIG. 9 and 10 show a procedure for writing desired data, corresponding to FIG. 16 of the related art.

Since the flash EEPROM has a limited number of times of writing, when writing the data, for example, the RAM is used as a buffer memory, and the data in the middle of editing is first written in the buffer memory to finally complete the data. Read the data at the step of flash EE
It is supposed to be written in PROM.

Further, in this embodiment, as shown in FIG. 12, one word of the final address of the flash EEPROM (5) is used as a storage area for the write ability value Nw, and one word of the address immediately before the last address is erased. It is used as a storage area for the value Ne. When executing the second step, first, the writing ability value Nw and the erasing ability value Ne are read from the flash EEPROM (5) and, for example, the RAM is used.
Shall be written in a predetermined area. Therefore, even if the power is turned off after the execution of the first step and before the execution of the second step, the erasing ability value Ne and the writing ability value Nw are the same as those of the flash E.
Since it remains stored in the EPROM (5), it is possible to turn on the power again to execute the second step.

First Step (FIGS . 1 to 4) As shown in FIG. 1, a flash EE is issued by a write command.
"1" is written in each bit of the first 1 address of the PROM (step S1), and a constant write execution time W
After Rc (10 μs) has elapsed (step S2), it is confirmed by the verify command whether or not the one address has been correctly written (step S3). Then, after a certain confirmation execution time WVc (6 μs) has elapsed (step S4), it is determined whether or not a mistake has occurred (step S5). If a mistake has occurred, the process returns to step S1 to perform the write operation. repeat. If no error has occurred, it is judged whether or not it is the last address (step S6), the process proceeds to the next address (step S7), and the above series of procedures is repeated until the last address is reached.

Next, as shown in FIG. 2, after the variable Ne for counting the erasing ability value is initialized (step S8), an erasing command (erase command) is issued to the flash EEPROM (step S9), and a constant value is given. Erase execution time ERc
After the elapse of (9.5 ms) (step S10), it is confirmed whether or not the first one address has been erased by the verify command (step S11). The confirmation execution time WVc (6
μs) (step S12), it is determined whether or not a mistake has occurred (step S13), and if a mistake has occurred, the variable Ne is counted up (step S14) and then the process returns to step S9. , Erase operation is repeated. If no error has occurred, it is judged whether or not it is the last address (step S15), the process proceeds to the next address (step S16), and the above series of procedures is repeated until the last address is reached. As a result, the final value of the variable Ne becomes the erasing ability value.

Thereafter, as shown in FIG. 3, a variable FDATA (1 byte) for temporarily registering the actual value provided in the buffer memory.
"1" is set to all bits of (step S17). Next, after initializing the writing ability value Nw and the writing ability value counting variable Nwt (steps S18 and S19), write the data of the variable FDATA to the first one address (1 byte) of the flash EEPROM by a write command.
(Step S20), after the write execution time WRc (10 μs) has elapsed
(Step S21), it is confirmed by the verify command whether or not the one address has been correctly written (Step S22). Then, after the confirmation execution time WVc (6 μs) has elapsed (step S23), it is determined whether or not a mistake has occurred (step S24), and if a mistake has occurred, the variable Nwt is counted up (step S25). ), And returns to step S20 to repeat the write operation.

If there is no mistake in the above judgment,
As shown in FIG. 4, the magnitudes of Nwt and Nw are compared (step S26). If Nwt> Nw, Nwt is set to Nwt (step S27). Incidentally, step S26 and step S27
Is a procedure for setting the maximum value of the ability value different for each address to the writing ability value Nw of the memory chip.

Next, it is judged whether or not it is the last address (step S28). If NO, the process proceeds to the next address (step S29), and the address where the data writing was performed immediately before is the last address. After judging whether it is two bytes before (step S30) and judging whether it is one byte before (step S31), the process returns to step S19 in FIG.
The TA data is written while advancing addresses one after another.

When YES is determined in step S30 of FIG. 4, after the erasing ability value Ne obtained by the procedure of FIG. 2 is registered in the variable FDATA (step S33),
Returning to step S19 of FIG. 3, the content of the variable FDATA is written to the corresponding address of the flash EEPROM, that is, the address one byte before the final address. If YES is determined in step S31 of FIG. 4, after the writing ability value Nw obtained by the procedure from step S19 of FIG. 3 to step S27 of FIG. 4 is registered in the variable FDATA.
(Step S32) Then, returning to step S19 in FIG. 3, the content of the variable FDATA is written to the corresponding address of the flash EEPROM, that is, the final address.

As a result, in the flash EEPROM,
As shown in FIG. 12, the erasing ability value Ne and the writing ability value Nw are registered.

Second step (FIGS. 5 to 10) As shown in FIG. 5, a flash EEPR is issued by a write command.
Write "1" to each bit of the first 1 address of OM (step S1), and write execution time WRc (10 μs)
After elapse of (step S2), it is judged whether or not it is the last address (step S3), the process proceeds to the next address (step S4), and the above series of procedures are repeated until the last address is reached. Then, when it is determined in step S3 that the address is the last address, it is determined whether or not the data writing to all the memory areas has been repeated the number of times of the write capability value Nw (step S5). Returning to step S1, the writing of data is repeated.

After the data writing is repeated the number of times of the writing ability value Nw, one address of the written data is confirmed by the verify command as shown in FIG. 6 (step S6). Then, the confirmation execution time WVc (6 μ
After elapse of (s) (step S7), it is judged whether or not a mistake has occurred (step S8), and if NO, it is judged whether or not the address is the last address (step S9), and the process proceeds to the next address (step S9). Step 10), proceed with confirmation of the data.

When it is determined in step S8 that a mistake has occurred, "1" is written again for that one address (step S11), and the write execution time WRc (10 μm).
After elapse of (step S12), it is judged whether it is the last address or not.
After (step S13), the process proceeds to the next address (step S14), and "1" is written until the last address is reached. The probability that a mistake is found in step S8 is extremely low, and the number of times that the procedures of steps S11 to S14 are actually executed is extremely small.

When it is determined in step S9 that "1" has been written up to the last address, an erase command is issued to the flash EEPROM as shown in FIG. 7 (step S15), and the erase execution time ERc (9 After the lapse of 0.5 ms (step S16), it is judged whether or not the erasing operation has been repeated by the erasing ability value Ne (step S17). If NO, the process returns to step S15 and the erasing operation is repeated.

After the erase operation is repeated by the number of erase ability values Ne, it is confirmed whether or not the first one address has been erased by the verify command as shown in FIG. 8 (step S18). After the confirmation execution time EVc (6 μs) has elapsed
(Step S19), it is judged whether or not a mistake has occurred (Step S20), and if NO, it is judged whether or not it is the last address.
After (step S21), the process proceeds to the next address (step S22) to confirm the erase operation.

When it is determined in step S20 that an error has occurred, "0" is written to that one address (step S23), and after the write execution time WRc (10 μm) has elapsed (step S24), After determining whether it is the last address (step S25), the process proceeds to the next address (step S2).
6), write "0" until the last address is reached. The probability that a mistake is found in step S20 is extremely low, and the number of times the procedures of steps S23 to S26 are actually executed is extremely small.

When it is confirmed in step S21 that erasing has been completed up to the last address, as shown in FIG. 9, the first one address of the flash EEPROM is issued by a write command.
The target data is written in (1 byte) (step S27), and after the write execution time WRc (10 μs) has elapsed (step S28), it is judged whether it is the last address (step S27).
29), proceed to the next address (step S30), and repeat the above series of procedures until the final address is reached. When it is determined in step S29 that the address is the last address, the writing of data to the entire memory area is
It is determined whether or not the writing ability value Nw has been repeated (step S31). If NO, the process returns to step S27 and the writing of data is repeated.

After the data writing is repeated the number of times of the writing ability value Nw, one address of the written data is confirmed by the verify command as shown in FIG. 10 (step S32). Then, the confirmation execution time WVc (6 μ
After the elapse of (s) (step S33), it is judged whether or not a mistake has occurred (step S34), and if NO, it is judged whether or not it is the last address (step S35), and the process proceeds to the next address.
(Step S36), the data read confirmation is advanced.

When it is determined in step S34 that a mistake has occurred, the target data is written again for that one address (step S37), and after the write execution time WRc (10 μm) has elapsed (step S37). In step S38, it is judged whether or not it is the last address (step S39), the process proceeds to the next address (step S40), and data is written until the last address is reached. The probability that a mistake is found in step S34 is extremely low, and the number of times the procedure of steps S37 to S40 is actually executed is extremely small.

In the above series of erasing and writing operations,
In most cases, step S1 of FIG. 5 to step S of FIG.
By executing step 10, data "1" is correctly written to all addresses in the memory area, and then step S in FIG.
11 through step S14, without passing through step S of FIG.
15 to step S22 of FIG. 8 are executed to complete the memory erase. Further, thereafter, without going through steps S23 to S26 of FIG. 8, steps S27 to FIG.
The step S36 of 0 is executed to complete the writing of data.

In this case, as in the above-mentioned conventional example, WRo
= 10 μs, WRc = 10 μs, Nw = 10, WVo = 10
μs, WVc = 6 μs, ERo = 10 μs, ERc = 9500
μs, Ne = 10, EVo = 10 μs, EVc = 6 μs, CS
= 128 × 1024 bytes, the time T1 required for writing shown in FIGS. 5 and 6, the time T2 required for erasing shown in FIGS. 7 and 8 and the time T3 required for writing shown in FIGS. 9 and 10 are as follows. It is calculated by the equations 4, 5, and 6, respectively.

[0041]

## EQU00004 ## T1 = (WRo + WRc) * CS * Nw + (WVo + WVc) * CS = 28.2 sec

[Equation 5] T2 = (ERo + ERc) × Ne + (EVo + EVc) × CS = 2.19 sec

## EQU6 ## T3 = (WRo + WRc) × CS × Nw + (WVo + WVc) × CS = 28.2 sec

[0042] Therefore, ultimately the time required to write the desired data to the flash EEPROM total 5 8.
The time is 59 seconds, which is about half that of the conventional method.

According to the above non-volatile memory control device and method , erasing and writing can be performed more accurately and quickly than in the past.
The target data can be written accurately and quickly.
it can. Furthermore, the writing ability value N for each memory chip
Since w and the erasing ability value Ne are actually measured and stored, it is possible to absorb variations in characteristics between the memory chips.

The above description of the embodiments is for explaining the present invention, and should not be construed as limiting the invention described in the claims or reducing the scope. The configuration of each part of the present invention is not limited to the above-mentioned embodiment, and it goes without saying that various modifications can be made within the technical scope described in the claims.

For example, in the above embodiment, the writing ability value Nw
The number of repetitions until the completion of the writing and erasing operations is adopted as the erasing ability value Ne. It is possible to adopt various values that reflect the actual value, such as the number of times calculated by such a function. Further, the writing ability value Nw is 1 for the entire area of the memory chip.
Although one value is set, it is also possible to divide the memory area into a plurality and set the writing ability value Nw for each memory area.

[Brief description of drawings]

FIG. 1 is a flowchart showing a first part of a first step in a method for controlling a nonvolatile memory according to the present invention.

FIG. 2 is a flowchart showing a second part of the above.

FIG. 3 is a flowchart showing a third part of the above.

FIG. 4 is a flowchart showing a fourth portion of the above.

FIG. 5 is a flowchart showing a first part of a second step in the method for controlling the nonvolatile memory according to the present invention.

FIG. 6 is a flowchart showing a second part of the above.

FIG. 7 is a flowchart showing a third part of the above.

FIG. 8 is a flowchart showing a fourth portion of the above.

FIG. 9 is a flowchart showing a fifth part of the above.

FIG. 10 is a flowchart showing a sixth portion of the above.

FIG. 11 is a block diagram showing a configuration of a microcomputer equipped with a flash EEPROM.

FIG. 12 is a diagram showing storage addresses of an erasing ability value and a writing ability value in a flash EEPROM.

FIG. 13 is a block diagram showing a connection state between a CPU and a flash EEPROM.

FIG. 14 is a flowchart showing a first part of a read / write procedure of a conventional flash EEPROM.

FIG. 15 is a flowchart showing a second part of the above.

FIG. 16 is a flowchart showing a third part of the above.

[Explanation of symbols]

(5) Flash EEPROM Ne erasing ability value Nw writing ability value

   ─────────────────────────────────────────────────── ─── Continued front page       (56) References JP-A-1-263998 (JP, A)                 JP 62-298096 (JP, A)                 JP-A-2-289997 (JP, A)                 JP-A-2-218098 (JP, A)

Claims (5)

(57) [Claims] 1. A non-volatile memory control device in which erasing or writing is completed by repeating erasing or writing operation a plurality of times in the same memory area. In the non-volatile memory, erasing of all memory areas is performed. Means for predetermining an erase ability value, which is the number of repetitions of the batch erase operation until the completion of the write operation, and a write ability value, which is the number of repetitions of the write operation until the writing of one address to the memory area are completed, means for storing the erase actual value and writing ability value on the nonvolatile memory, from the non-volatile memory means to read out the erasing ability value and writing ability value, the entire memory area of the nonvolatile memory In erasing,
A means for performing a batch erase operation by repeating the erase ability value at least the number of times of the erase ability value without performing a confirming operation, and in writing target data to the nonvolatile memory, at least the write ability value of the nonvolatile memory does not require a confirming operation. A non-volatile memory control device comprising: means for repeatedly performing a write operation. 2. The non-volatile memory control device according to claim 1, wherein the write capability value is the maximum value of the number of repetitions of the write operation until the writing of one address to the memory area is completed in all the addresses. 3. A method for controlling a non-volatile memory in which the erasing or writing is completed by repeating the erasing or writing operation a plurality of times in the same memory area, wherein the erasing of all the memory areas in the non-volatile memory A procedure for predetermining an erase ability value that is the number of repetitions of the batch erase operation until completion of the write operation, and a write ability value that is the number of repetitions of the write operation until completion of writing one address into the memory area, the includes a procedure for storing in the nonvolatile memory the erasing ability value and writing ability value, and a procedure to read out the erasing ability value and writing ability value from the nonvolatile memory, the entire memory of the nonvolatile memory When deleting an area,
In order to write the target data to the non-volatile memory, the procedure of performing the batch erase operation at least the number of times of the erase ability value without the confirmation operation is performed. A method for controlling a non-volatile memory, characterized in that a procedure for performing a write operation is repeated a number of times. 4. The method for controlling a non-volatile memory according to claim 3, wherein the write ability value is a maximum value of the number of repetitions of the write operation until the writing of one address to the memory area is completed, among all the addresses. 5. A write operation is performed on all memory areas, and then a batch erase operation is performed on all the memory areas to determine whether or not an erase error has occurred in order from the first address. When an erase error occurs, Determines the erase capability value by returning to the batch erase operation again until it is determined that no erase error has occurred at the last address, and it is determined that no write error has occurred in order from the first address. The non-volatile memory control device according to claim 1 or 2, wherein the write capability value is determined by repeating the write operation in the memory area for each address until it reaches the limit.