JP3378386B2 - Semiconductor storage device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device for storing multivalued data.

[0002]

2. Description of the Related Art In recent years, semiconductor memory devices have been highly integrated, and research on fine semiconductor memory devices has been actively conducted. For example, among various semiconductor memory devices, an electrically rewritable nonvolatile semiconductor memory device (EEPROM) is expected as a substitute for a hard disk device, and further higher integration is desired.

The memory cell used in this EEPROM is
It has a special structure that uses a floating gate (charge storage layer), which is not found in other semiconductor memory devices, and the threshold value of a cell transistor is changed by holding charges in the floating gate. Although the threshold value takes a value corresponding to the “0” state and the “1” state, in this case, since only one information can be stored in one memory cell, when a large capacity storage element is formed, the element is There is no choice but to enlarge the formation area. Further, even if trying to miniaturize the element in order to avoid this, there are various problems to be solved in miniaturization,
It costs a lot of money.

On the other hand, the threshold value of the cell transistor can be varied by controlling the amount of charge injected into the floating gate, and it is theoretically possible to store multivalued data by utilizing this. is there. However, it is difficult to control the charge injection amount by the applied voltage, and it is extremely difficult to stably maintain the threshold value within a certain range of a plurality of levels. By changing the threshold value in two steps depending on the presence or absence of injected charges,
Considering the present situation where it is difficult to control the threshold value even when discriminating binary data of “0” and “1”, multi-valued data (three values or more) is stored according to the amount of injected charges in the conventional structure. Is practically difficult to do.

[0005]

As described above, in a conventional nonvolatile semiconductor memory device using a memory cell having a charge storage layer, only one data can be stored in one memory cell, so that the storage capacity is increased. However, there is a problem in that it is necessary to enlarge the element region and miniaturize the element, and accordingly, the manufacturing cost increases. Moreover, even if the threshold value is changed stepwise by controlling the amount of carriers injected into the charge storage layer, it is difficult to stably control the threshold value in a narrow range, and multi-valued data is stored in the conventional structure. Was practically difficult.

The present invention has been made in consideration of the above circumstances. An object of the present invention is to enable the threshold value of a cell transistor to be stably controlled in stages and to store multi-valued data. Another object of the present invention is to provide a semiconductor memory device capable of increasing the storage capacity without increasing the element region or miniaturizing the element.

[0007]

In order to solve the above problems, the present invention employs the following configurations. That is, the present invention provides a semiconductor memory device in which memory cells each having a first insulating film, a charge storage layer, a second insulating film, and a control gate stacked on a semiconductor substrate are arranged in a matrix. , A substance with unique and multiple charge trapping levels
And a level corresponding to the substance when a predetermined voltage is applied.
Is formed by stacking at least two conductive films that selectively capture carriers on both sides of the insulating film, and stores multi-valued data by selectively giving and receiving charges to and from each stacked conductive film. It is characterized by doing.

Here, the following are preferred embodiments of the present invention. (1) Use metal-doped polysilicon, silicon nitride, or tantalum oxide as the conductive film forming the charge storage layer. (2) A plurality of memory cells are connected in series to form a NAND cell. (3) The charge storage layer is composed of n layers of conductive films 1 to n, and the threshold voltage Vth (i) of the memory cell is changed to another threshold value by holding charges in the i-th conductive film. , And the memory cell has an n-value distinguishable threshold value. (4) When storing data in a memory cell, charges are injected into an arbitrary number of a plurality of conductive films by carrier injection from the surface of a semiconductor substrate. (5) When data is stored in a memory cell, charges are injected into an arbitrary number of a plurality of conductive films by carrier injection from the control gate. (6) The conductive film forming the charge storage layer is a substance having a plurality of unique charge trap levels, and by applying a predetermined voltage, carriers are selectively transferred to the corresponding levels of the conductive film. To be captured.

[0009]

According to the present invention, by stacking a plurality of conductive films as a charge storage layer and selectively injecting / releasing carriers into / from each conductive film, at least two or more ( It is possible to have three or more threshold values.

Here, the difference between the present invention and the conventional example is that
Instead of changing the amount of carriers injected into one conductive film, the carriers are selectively injected into a plurality of conductive films. The injection of carriers is determined by the voltage applied between the semiconductor substrate and the control gate. In the present invention, however, carriers are not injected into any conductive film up to a certain voltage V1, and when V1 is exceeded, the conductivity of the first layer is increased. The carriers are injected into the film, and when the voltage V2 is higher than the predetermined voltage by a predetermined level, the carriers are also injected into the second conductive film.

In this case, the amount of carriers accumulated in the charge accumulation layer does not continuously increase with an increase in the applied voltage but increases stepwise. Then, the threshold value of the cell transistor also changes stepwise. Therefore, the threshold value can be stably held at a certain value in a plurality of steps, and by utilizing this, it becomes possible to easily store multivalued data. As a result, without increasing the element area or miniaturizing the element,
It is possible to increase the storage capacity.

The amount of data that can be stored in one memory cell is determined by the number of conductive film layers stacked as the charge storage layer. Further, depending on the thickness of the insulating film between the conductive films and the type thereof, the threshold value Vth of the cell transistor and its width Δ
Vth can be controlled. Furthermore, the charge retention characteristic can be changed by changing the thickness of the insulating film between the conductive films.

[0013]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows an NA according to the first embodiment of the present invention.
FIG. 3 is a plan view showing a memory cell structure of an ND type EEPROM. Further, FIG. 2 and FIG. 3 are respectively views A- of FIG.
It is an A'sectional view and a BB 'sectional view.

As shown in FIGS. 1 and 2, this NAND type E
In an EPROM, a plurality of control gates 8 and a plurality of active layers 1
1 are orthogonally arranged, and a tunnel oxide film 4 (first insulating film) and an ONO film (second insulating film) 3 are provided at the intersections of the two.
Multiple floating gates (5, 6, 7) are provided so as to be sandwiched via the gates, and each intersection forms a storage node. That is, although the basic structure is the same as the conventional one, the charge storage layer is not a single layer but has a laminated structure in which two conductive films 6 and 7 are laminated with the insulating film 5 sandwiched therebetween.

Further, in this embodiment, as shown in FIGS. 1 and 3, the element isolation region has a groove 12 formed on the surface of the semiconductor substrate 1.
Are buried in the insulating film 2 up to the upper end surface, and multiple floating gates (5, 6, 7) are formed in a self-aligned manner between adjacent element isolation regions. In addition,
Reference numeral 26 in FIG. 1 denotes a bit line contact.

In the present embodiment, since the charge storage layer has a laminated structure, by changing the place where the injected electrons are held, the threshold value at the time of writing is not limited to the conventional one state but a plurality of threshold values. Can take a value.

Next, the manufacturing process of the device of this embodiment will be described. First, as shown in FIG. 4A, a p-type well is formed on an n-type silicon substrate 1 having a plane orientation (100) and a specific resistance of 5 to 50 Ω · cm, for example, a tunnel thermal oxide film having a thickness of 10 nm. A (first insulating film) 4 is formed in an HCl atmosphere, and further, for example, P-doped poly-Si is formed to a thickness of about 100 nm to form a first floating gate (conductive film) 6. The first floating gate 6 may be, for example, a silicon nitride film.
Then, the SiO ₂ film 5 is formed to a thickness of
Deposit about m. Instead of depositing this film 5, polysilicon may be thermally oxidized. Further, as the second floating gate 7, for example, the above-mentioned P-doped poly-Si film, or
For example, a silicon nitride film is deposited to about 100 nm. Then, the resist 21 is formed into a desired pattern by the PEP process.

Next, as shown in FIG. 4B, the above-mentioned multiple floating gate structures (5, 6, 7) and the tunnel oxide film 4 are etched by, for example, RIE using the resist 21 as a mask, and silicon is further added. The surface of the substrate 1 is etched in, for example, an HBr / SiF ₄ / O ₂ atmosphere to form a groove 12 having a depth of 0.5 μm and a width of 0.4 μm.

Next, as shown in FIG. 4C, field implantation is performed to remove the resist 21 and then the groove 1 is formed.
As the element isolation insulating film 2 with which 2 is embedded, for example, a TEOS film formed by CVD is formed. At this time, it is desirable to embed so that voids do not occur.

Next, as shown in FIG. 5D, this film 2 is etched back by, for example, RIE, and is left only in the groove 12. Next, as shown in FIG. 5E, an ONO film 3 is formed as an interpoly film to a thickness of, for example, about 16 nm, and as shown in FIG. 5F, a polysilicon film is deposited as a control gate 8. Then, an interlayer insulating film (not shown) is deposited on it to complete the element formation.

The floating gates 6 and 7 stacked as the charge storage layer may be made of P-doped poly or S, for example.
A film having an inherent trap level such as i ₃ N ₄ may be used. In the case of P-doped poly, by varying the P concentration, the total number of electrons held in each layer is different, so that it is possible to further provide a plurality of threshold values. In the case of a film having an intrinsic trap level such as Si ₃ N ₄ , a plurality of threshold values can be provided by trapping electrons at different trap levels in different electric fields.

In both cases, the amount of charges held in each film can be changed by changing the film thickness of the multiple floating gates, and thereby a plurality of threshold values can be provided with good controllability. be able to. Further, in the present embodiment, as the element isolation, a step of digging a trench (trench) on the silicon substrate and filling the trench is mentioned. However, for example, element isolation by a thick oxide film (LOCOS) is the same as that of the present embodiment. You can think about the process.

Next, the principle of operation in which multivalued data can be stored in the device of this embodiment will be described. FIG. 6 shows an energy band diagram of a cross section of the memory cell in this example. A charge storage layer is formed on a semiconductor substrate 1 via a tunnel oxide film 4, and a control gate 8 is formed thereon via an interpoly insulating film 3. And
As the charge storage layer, for example, two layers of silicon nitride films 6 and 7 are deposited via the insulating film 5.

There are traps in the silicon nitride film due to dangling bonds of silicon, and the traps can take three states as shown in FIG. One state is a state in which no electrons are contained in the trap, and is called an electrically positively charged D ⁺ state. The latter two are states in which one and two electrons are captured, which are called electrically neutral D ⁰ and electrically negatively charged D ⁻ state, respectively.

The energy level of each state is shown in the band diagram of the silicon nitride film as shown in FIG. There are three states D ⁺ , D ⁰ , D ^{− in} this trap, but only one state can be seen at a certain time. In the trap in the silicon nitride film, when 0, 1, and 2 electrons are trapped, that is, the energy levels of the D ⁺ , D ⁰ , and D ⁻ states are significantly different.

The electrons are trapped in the D ⁺ state and the trap state becomes the D ⁰ state. At this time, from the law of conservation of energy, D
Unless the electron has an energy higher than the energy level corresponding to ^0, it is trapped in the D ⁺ state and the trap state becomes D.
Cannot be ⁰ . The electrons are captured in the D ^O state,
The same applies when changing to the D ^- state.

Therefore, the electrons can be selectively trapped in the D ⁰ state or the D ⁻ state by adjusting the voltage applied to the floating gate. Further, for example, in the case of a silicon nitride film, since the number of trap levels per unit volume is determined, the amount of charges trapped in the film can be easily estimated by the film thickness. Therefore, when used in a multi-valued memory cell, the amount of change in threshold value can be easily predicted. Further, since the trap level concentration is caused by the bonding state of silicon and nitrogen, there is little variation between chips and between wafers. Therefore, it is possible to easily form a multi-valued memory device in which the variation in the threshold change amount is small.

D⁰ State and D^- Selectively capture electrons in the state
The electric field for catching can be determined as shown in FIG.
It The voltage applied between the silicon substrate and the control gate is V
Then, the electric field applied to the floating gate is The first floating gate D⁰ Let the state selectively trap
The electric field for this is expressed under the following conditions.

Φ ₀ − (φ _n + E ⁻ + E ⁰ + ε _flot · x ₀ )> 0 The electric field is expressed as follows. {Φ ₀ − (φ _n + E ⁻ + E ⁰ )} / x ₀ <ε _flot (2) Further, since electrons are not simultaneously captured in the D ⁰ state and the D ⁻ state, {φ ₀ − (φ _n + E ^- )} / X ₀ > ε _flot (3) Therefore, the electric field for capturing in the D ⁰ state is expressed as follows.

{Φ ₀ − (φ _n + E ⁻ + E ⁰ )} / x ₀ <ε _flot <{φ ₀ − (φ _n + E ⁻ )} / x ₀ (4) Electrons selectively in the D ⁻ state In order to capture, an electric field represented by the equation (3) may be applied. However, if a stronger electric field is applied than necessary, the electrons trapped in the floating gate will be emitted to the control gate, as shown in FIG. Therefore, in order to capture electrons in the D ^- state, it is necessary that {φ ₀ − (φ _n + E ⁻ )} / x ₀ = ε _flot (5).

[0031] Therefore, grounding the substrate, by applying a positive low voltage to the control gate, D ⁰ or D ^- by selectively applying a charge to the state, D ⁰ or D ^- selective state Can be made to capture the charge.

In FIG. 6, for example, the tunnel oxide film 4 has a film thickness of 8 nm and the silicon nitride films 6 and 7 have a film thickness of 100 n.
m, the insulating film 5 is 20 nm, and the control gate 8 is 200 to 30
0 nm. First, VU cure is applied to remove excess charges from the silicon nitride film, so that the film becomes electrically neutral. This state is set to "0". At this time, as shown in FIG. 11, most of the traps in the film are in the D ⁰ state (14), but the other traps are in the D ⁺ (13) and D ⁻ (15) states.

Next, when 0V is applied to the silicon substrate 1 and a low voltage (4 to 8V) is applied to the control gate 8, the traps in the D ⁺ state are selectively trapped to change the trap state to the D ⁰ state. It is possible. Due to the trapped charges, when the first and second floating gates 6 and 7 each have a thickness of 100 nm, the threshold change Δ of the cell transistor Δ
It is considered that Vth1 becomes about 0.4 to 0.8V. This state is named "1" state.

Next, 0V is similarly applied to the silicon substrate 1.
When 15 V is applied to the control gate 8, electrons are injected from the substrate 1 and all traps in the first floating gate 6 are in the D ⁻ state, as shown in FIG. Since the D ⁻ state has a small work function difference from the insulating film, the electrons in the D ⁻ (15) state tunnel into the second floating gate 7, as shown in FIG. This tunnel, as shown in Figure 14,
It ends when all the traps in the second floating gate 7 are in the D ⁻ (15) state. This state is named "2" state.
The threshold change of the cell transistor at this time is ΔVth
It is considered that 2 = 0.8V or so.

In erasing, the electrons in the D ⁻ state of the first and second floating gates 6 and 7 are tunneled in the tunnel oxide film 2 in the reverse order.
Then, a high negative electric field is applied to the control gate 8 to emit electrons in the D ⁰ state through the tunnel oxide film 2.

As described above, in this embodiment, the state where no charge is injected into the first and second floating gates 6 and 7 stacked as the charge storage layer is “0”, and the first floating gate. The state where the charges are injected into only 6 is “1”, the first,
Assuming that the state where charges are injected into both the second floating gates 6 and 7 is “2”, as shown in FIG. 15, “0”, “1”,
The threshold value of the cell transistor can be changed according to the state of "2". Therefore, a memory cell capable of storing three-valued data can be realized, and the storage capacity can be remarkably improved.

The present invention is not limited to the above embodiment. In the embodiment, the conductive film forming the charge storage layer has two layers. However, the number of conductive films may be three or more. Further, the conditions such as the film thickness of the conductive film and the insulating film between them can be appropriately changed according to the specifications. Further, the conductive film forming the charge storage layer is not limited to silicon nitride, and may be any substance having a charge trap level, such as metal (eg, gold) -doped polysilicon or tantalum oxide (Ta ₂ O ₅ ). Etc. can be used.

The carriers may be injected into the charge storage layer not from the substrate side but from the control gate side.
Further, in the embodiment, the NA in which a plurality of memory cells are connected in series is used.
Although the ND type example is shown, the present invention is not limited to this, and a normal NOR type non-volatile memory in which each memory cell is connected to a bit line and a memory cell unit in which a plurality of memory cells are connected in parallel are used as a memory cell unit. A connected to the bit line
It can also be applied to the ND type and DINOR type. In addition, various modifications can be made without departing from the scope of the present invention.

[0039]

As described above in detail, according to the present invention, since the charge storage layer has a structure in which a plurality of conductive films are laminated, it is possible to selectively inject and release carriers into each conductive film. One memory cell can have at least two (preferably three or more) threshold values. Therefore, the threshold value of the memory cell transistor can be stably controlled in stages, multi-valued data can be stored, and the storage capacity can be increased without increasing the element region or miniaturizing the element. It becomes possible to realize a semiconductor memory device.

[Brief description of drawings]

FIG. 1 is a NAND type EEPR according to an embodiment of the present invention.
The top view which shows the memory cell structure of OM.

FIG. 2 is a sectional view taken along the line AA ′ of FIG.

FIG. 3 is a sectional view taken along the line BB ′ of FIG.

FIG. 4 is a cross-sectional view showing the first half of the manufacturing process of the memory cell in the example.

FIG. 5 is a cross-sectional view showing the latter half of the manufacturing process of the memory cell in the example.

FIG. 6 is a diagram showing an energy band diagram of a memory cell section in an example.

FIG. 7 is a view showing a state of a trap due to a dangling bond of silicon.

FIG. 8 is a diagram showing energy levels of traps in a silicon nitride film.

FIG. 9 is a diagram showing an electric field for selectively capturing electrons in a D ⁰ state and a D ⁻ state.

FIG. 10 is a diagram showing a state in which electrons trapped in a floating gate are emitted to a control gate.

FIG. 11 is a view showing that traps in the D ⁺ state are selectively trapped to change the trap state to the D ⁰ state.

FIG. 12 is a view showing that all traps in the first floating gate are in a D ⁻ state.

FIG. 13 is a diagram showing a state in which electrons in the D ⁻ state tunnel into the second floating gate.

FIG. 14 is a view showing that all traps in the second floating gate are in the D ⁻ state.

FIG. 15 is a diagram showing a state distribution of threshold values corresponding to states “0”, “1”, and “2”.

[Explanation of symbols]

1 ... Semiconductor substrate 2 ... Element isolation insulating film 3 ... ONO film (second insulating film) 4 ... Tunnel oxide film (first insulating film) 5 ... SiO ₂ film 6 ... First floating gate (conductive film) 7 Second floating gate (conductive film) 8 Control gate 11 Active layer 12 Groove

─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Seiichi Aridome 1 Komukai Toshiba-cho, Sachi-ku, Kawasaki-shi, Kanagawa Toshiba Research & Development Center Co., Ltd. (72) Inventor Tetsuro Endo Komukai-Toshiba, Kawasaki-shi, Kanagawa No. 1 in Machi Toshiba Research & Development Center Co., Ltd. (56) References JP-A-7-273227 (JP, A) JP-A-8-83855 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) H01L 29/788

Claims (4)

(57) [Claims] 1. A semiconductor memory device in which memory cells each having a first insulating film, a charge storage layer, a second insulating film, and a control gate stacked on a semiconductor substrate are arranged in a matrix. , Has unique and multiple charge trapping levels
It consists of a substance and responds to the substance by applying a predetermined voltage.
Is formed by stacking at least two conductive films that selectively capture carriers at different levels through an insulating film, and by selectively giving and receiving electric charges to and from each stacked conductive film, a multi-valued A semiconductor memory device characterized by storing data. 2. The charge storage layer is composed of n layers of conductive films 1 to n, and the charges are held in the i-th conductive film so that the threshold value Vth (i) of the memory cell is different from that of other conductive films. 2. The semiconductor memory device according to claim 1, wherein the memory cell is distinguishable from a threshold value and the memory cell has an n-value distinguishable threshold value. 3. When storing data in the memory cell,
3. The semiconductor memory device according to claim 1, wherein charges are injected into an arbitrary number of the plurality of conductive films by carrier injection from the surface of the semiconductor substrate. 4. When storing data in the memory cell,
3. The semiconductor memory device according to claim 1, wherein charges are injected into an arbitrary number of the plurality of conductive films by carrier injection from the control gate.