JP3372468B2 - Electro-optic sampling oscilloscope - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electro-optic sampling oscilloscope.

[0002]

2. Description of the Related Art Recently, for example, an electro-optic sampling oscilloscope capable of measuring without disturbing a circuit under test is used for signal measurement of a circuit under test that handles a signal having an ultra-high bit rate of 2.4 Gbps. Has been.
Here, the electro-optic sampling oscilloscope uses an electro-optic probe that detects the signal under measurement by utilizing the electro-optic effect.

Further, the above-mentioned electro-optical sampling oscilloscope (1) is easy to measure because it does not require a ground line when measuring a signal. (2) The metal pin at the tip of the electro-optical probe is removed from the circuit system. Since they are isolated from each other, a high input impedance can be realized, and as a result, the state of the measured point is hardly disturbed. (3) Since the optical pulse is used, wideband measurement up to GHz order is possible. , It is especially used for the measurement of communication information systems, which are becoming faster.

FIG. 4 is a block diagram showing the configuration of a conventional electro-optic sampling oscilloscope using the above-mentioned measurement principle. The electro-optic sampling oscilloscope shown in this figure comprises a main body 1 and an electro-optic probe 2. The main body 1 is composed of a trigger circuit 3, a timing generation circuit 4, an optical pulse generation circuit 5, an A / D (analog / digital) converter 6, a processing circuit 7, and a setting section 8.

The trigger circuit 3 generates a trigger signal having a frequency set by the setting section 8 based on a trigger signal input from the outside. The timing generation circuit 4 generates the timing of generating the optical pulse and A / D in the A / D converter 6.
A timing signal for timing the D conversion is generated. This timing signal is generated from the desired sample rate, the trigger signal input from the trigger circuit 3, and the clock signal from the internal clock. Here, the sample rate means a rate determined by the processing circuit 7 based on the x-axis scale which is the enlargement factor of the measurement signal in the time direction set by the setting unit 8.

The optical pulse generation circuit 5 generates an optical pulse based on the timing signal generated by the timing generation circuit 4 and supplies it to the electro-optic probe 2.
Then, the optical pulse that has undergone the polarization change is detected by a polarization detection optical system (not shown) in the electro-optic probe 2, and the detection signal as the detection result is amplified and A / D converted by the A / D converter 6. Then, it is input to the processing circuit 7.
Then, the processing circuit 7 performs processing such as displaying the signal under measurement.

[0007]

By the way, in the conventional electro-optic sampling oscilloscope, if the trigger signal is unstable or random, a measurement error occurs that the waveform of the measured signal as the measurement result is disturbed. To do. However, in the conventional electro-optic sampling oscilloscope, from the viewpoint of the measurer, the trigger signal may be unstable or random, causing a measurement error, or the measured signal itself may not be correct. There is a drawback that it is not possible to distinguish whether it is stable and is being measured normally. The present invention has been made under such a background, and an object thereof is to provide an electro-optical sampling oscilloscope capable of notifying a measurement person of a measurement error resulting from an unstable trigger signal. To do.

[0008]

According to a first aspect of the present invention, an electro-optical sampling oscilloscope that measures a signal under measurement by using an optical pulse generated based on a trigger signal is provided at regular intervals. Conversion means for converting each bit in the trigger signal into parallel data, and comparison means for comparing the two parallel data,
It is characterized by comprising a judging means for judging whether or not the trigger signal is stable based on a comparison result of the comparing means, and a display means for displaying a judgment result of the judging means. The invention described in claim 2 is the electro-optical sampling oscilloscope according to claim 1,
While the determination means determines that the trigger signal is stable when the comparison result of the comparison means is in agreement,
When the comparison result of the comparison means does not match, it is determined that the trigger signal is unstable. According to a third aspect of the present invention, in the electro-optical sampling oscilloscope according to the first or second aspect, the first latch means for latching the parallel data at regular intervals and the first latch means for latching the parallel data are latched. Second parallel latching means for latching the parallel data that has been stored at regular intervals, and the comparing means includes the first and second latching means.
It is characterized in that the two parallel data latched by the respective latch means are compared.

[0009]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a configuration of a main part of an electro-optical sampling oscilloscope according to an embodiment of the present invention. In this figure, 10 is a control unit for generating the synchronization signal Ss shown in FIG. 2A from the above-mentioned internal clock Sck. The cycle of the synchronization signal Ss corresponds to the cycle of a digital signal of 8 bits. The period of the synchronization signal Ss is not limited to 8 bits, and may be any number of bits such as 16 or 32 bits.

Reference numeral 11 denotes one cycle of the synchronizing signal Ss,
S / P (serial / parallel) for converting the serial trigger signal St (see FIG. 2B) into parallel data Dp
It is a conversion unit. Here, the synchronization signal Ss and the trigger signal St
And are asynchronous. A latch circuit 12 latches the parallel data Dp for one cycle in synchronization with the synchronization signal Ss, and outputs the latched parallel data Dp as parallel data Dn + 1. Reference numeral 13 is a latch circuit that latches one cycle of parallel data Dp latched in the latch circuit 12 in synchronization with the synchronization signal Ss, and outputs the latched parallel data Dp as parallel data Dn.

Reference numeral 14 denotes a comparison section for comparing the parallel data Dn + 1 and the parallel data Dn, which are sequentially input from the latch circuit 12 and the latch circuit 13 in synchronization with the synchronization signal Ss. Output as Sc. A display unit 15 displays the comparison result of the comparison unit 14, and is, for example, a lamp, a light emitting diode, a liquid crystal display, or the like.

Next, the operation of the electro-optic sampling oscilloscope according to the above-described embodiment will be described.
At time t0 shown in FIG. 2A, the internal clock Sck
2 is input to the control unit 10, the control unit 10 generates the synchronization signal Ss shown in FIG. 2A from the internal clock Sck and outputs it to the S / P conversion unit 11, the latch circuit 12, and the latch circuit 13. Output to each.

As a result, the S / P converter 11 converts the sequentially input trigger signal St into parallel data Dp. Then, at time t1 shown in FIG. 2A,
The latch circuit 12 has a period T from time t0 to time t1.
The parallel data Dp obtained by parallel-converting the trigger signal St at 0 is latched. In the example shown in FIG. 2B, the parallel data Dp in the period T0 is “1100.
It is 0000 ".

Also, at time t1, the S / P converter 1
1 is the trigger signal St shown in FIG.
To parallel data Dp. And now, Figure 2
At time t2 shown in (a), the latch circuit 12
In the period T1 from the time t1 to the time t2, the parallel data Dp obtained by converting the trigger signal St into parallel is latched.

In the example shown in FIG. 2B, the parallel data Dp in the period T1 is "11000" which is the same as that in the period T0.
000 ″. Further, at time t2, the parallel data Dp latched by the latch circuit 12 is latched by the latch circuit 13. As a result, the latch circuit 12
From, the parallel data of "11000000" Dn + 1
Is output to the comparison unit 14, and the latch circuit 13 outputs “11000000” parallel data Dn to the comparison unit 14.

As a result, the comparison unit 14 causes the parallel data Dn ("11000000") and the parallel data Dn + 1.
("11000000") is compared. In this case, the arrangements of "1" and "0" and the number of consecutive "1" s of the both completely match, and therefore the comparison unit 14 outputs the comparison result signal Sc indicating that they match. To do. As a result,
The display unit 15 displays that the trigger signal St is stable, or neither of them is displayed.

Further, at time t2, the S / P converter 1
1 is the trigger signal St shown in FIG.
To parallel data Dp. And now, Figure 2
At time t3 shown in (a), the latch circuit 12
In the period T2 from time t2 to time t3, the parallel data Dp, which is the parallel conversion of the trigger signal St, is latched.

In the example shown in FIG. 2B, the parallel data Dp in the period T2 is "11001100". Further, at time t3, the parallel data D of "11000000" latched by the latch circuit 12 is generated.
p is latched by the latch circuit 13. As a result, the latch circuit 12 outputs the parallel data Dn + 1 of “11001100” to the comparison unit 14, and the latch circuit 13 outputs the parallel data Dn of “11000000” to the comparison unit 14.

As a result, the comparison unit 14 causes the parallel data Dn ("11000000") and the parallel data Dn + 1.
(“11001100”) is compared. In this case, since the arrays of "1" and "0" and the number of consecutive "1" s of both do not match, the comparison unit 14 outputs the comparison result signal Sc indicating that they do not match. As a result, the display unit 15 displays that the trigger signal St is unstable and that a measurement error has occurred.

As described above, the electro-optic sampling oscilloscope according to the embodiment of the present invention is configured to display on the display unit 15 whether or not the trigger signal St is stable. It is possible to notify the measurer of a measurement error caused by St becoming unstable.

Although one embodiment of the present invention has been described in detail above with reference to the drawings, the specific configuration is not limited to this embodiment, and design changes within the scope not departing from the gist of the present invention. Even so, it is included in the present invention. For example, in the electro-optic sampling oscilloscope according to the above-described embodiment, a case where the trigger signal is determined to be stable when the parallel data Dn and the parallel data Dn + 1 shown in FIG. I explained,
The criterion is not limited to this example, and the criteria listed below may be used. (A) If the trigger signal St obtained from the parallel data Dn shown in FIG. 3A and the trigger signal St obtained from the parallel data Dn + 1 shown in FIG. It is determined that the signal St is stable. (B) The rising and falling positions of the trigger signal St obtained from the parallel data Dn shown in FIG. 3A and the rising and falling positions of the trigger signal St obtained from the parallel data Dn + 1 shown in FIG. 3C. When each trailing edge position differs by -1 bit, it is determined that the trigger signal St is stable. This is in consideration of the error amount due to the shift of the conversion timing of the S / P conversion unit 11, which is caused by the non-synchronization of the trigger signal St and the synchronization signal Ss as described above. (C) The rising and falling positions of the trigger signal St obtained from the parallel data Dn shown in FIG. 3A and the rising and falling positions of the trigger signal St obtained from the parallel data Dn + 1 shown in FIG. 3D. When the position of each trailing edge differs by one bit, it is determined that the trigger signal St is stable. This is in consideration of the error amount due to the shift of the conversion timing of the S / P conversion unit 11, similarly to the above item (B). (D) If two or three of the criteria of (a), (b), and (c) above are simultaneously satisfied, it is determined that the trigger signal St is stable.

[0022]

As described above, according to the present invention, whether or not the trigger signal is stable is judged based on the comparison result of the comparison means, and the judgment result is displayed on the display means. With this configuration, it is possible to obtain the effect of being able to notify the measurer of a measurement error caused by the instability of the trigger signal.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a main part of an electro-optical sampling oscilloscope according to an embodiment of the present invention.

FIG. 2 is a signal waveform diagram illustrating an operation of the electro-optical sampling oscilloscope according to the same embodiment.

FIG. 3 is a diagram illustrating a stable condition of a trigger signal in the electro-optical sampling oscilloscope according to the same embodiment.

FIG. 4 is a block diagram showing a configuration of a conventional electro-optical sampling oscilloscope.

[Explanation of symbols]

10 Control unit 11 S / P converter 12 Latch circuit 13 Latch circuit 14 Comparison section 15 Display

─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Jun Kikuchi 4-19-7 Kamata, Ota-ku, Tokyo Ando Electric Co., Ltd. (72) Nobuichi Banjo 4-19-7 Kamata, Ota-ku, Tokyo Ando Electric Co., Ltd. (72) Inventor Yoshio Endo 4-19-7 Kamata, Ota-ku, Tokyo Ando Electric Co., Ltd. (72) Inventor Mitsuru Shinagawa 3-19-2 Nishishinjuku, Shinjuku-ku, Tokyo Nihon Telegraph Telephone Company (72) Inventor Tadao Nagatsuma 3-19-2 Nishishinjuku, Shinjuku-ku, Tokyo Japan Telegraph and Telephone Corporation (72) Inventor Junzo Yamada 3-19-3 Nishishinjuku, Shinjuku-ku, Tokyo Nihon Telegraph and Telephone Corporation (56) Reference JP-A-9-178780 (JP, A) JP-A-6-201803 (JP, A) JP-A-7-43393 (JP, A) JP-A-6- 242152 (JP, A) (58) The field (Int.Cl. ^7, DB name) G01R 13/00 - 13/42

Claims (3)

(57) [Claims] 1. An electro-optical sampling oscilloscope for measuring a signal under measurement by using an optical pulse generated based on a trigger signal, and converting each bit in the trigger signal into parallel data at regular intervals. A conversion means; a comparison means for comparing the two parallel data; a judgment means for judging whether the trigger signal is stable based on a comparison result of the comparison means; and a judgment result of the judgment means. An electro-optical sampling oscilloscope, comprising: display means for displaying. 2. The determination means determines that the trigger signal is stable when the comparison result of the comparison means is in agreement, while the trigger signal is determined when the comparison result of the comparison means is inconsistent. The electro-optic sampling oscilloscope according to claim 1, wherein the electro-optical sampling oscilloscope is determined to be unstable. 3. A first latch means for latching the parallel data at regular intervals, and a second latch means for latching the parallel data latched by the first latch means at regular intervals. The electro-optic sampling oscilloscope according to claim 1 or 2, wherein the comparison means compares the two parallel data latched in the first and second latch means, respectively.