JP3371404B2 - Switching power supply - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is configured so that a plurality of inverters are connected in parallel and a DC output voltage is supplied between output terminals common to the respective inverters. The present invention relates to a switching power supply. 2. Description of the Related Art In general, a switching power supply of this type intermittently supplies a DC input voltage to a primary winding of a transformer by switching a switching element constituting an inverter, and performs a switching operation of the transformer. The voltage induced in the next winding is rectified and smoothed by a rectifier diode or an output smoothing choke coil connected to the output side of the inverter, and a stable DC output voltage is supplied between output terminals. It is conventionally known to connect a plurality of inverters in parallel to supply a DC output voltage between output terminals common to each inverter in order to extract more output power. In the case of a power supply having such a structure, the total output current or total output power from each inverter is detected,
An overcurrent protection circuit is provided that narrows the pulse width to each switching element when an excessive current flows to the load side to prevent damage to the power supply device due to overload or output short circuit. [0003] The overcurrent protection circuit in the above prior art does not individually monitor the output from each inverter, so that one of the inverters fails and the remaining normal inverters fail. Even in the situation where output power exceeding the capacity is supplied, there is a possibility that it is not determined that an overload condition exists. In this case, the temperature of the transformer rises abnormally, Secondary disasters such as deterioration of withstand voltage between sides and electric shock accidents due to rare short circuits occur in normal inverters. In order to avoid such a situation, it is conceivable to attach a temperature detector such as a thermal guard to or near the heat-generating component that constitutes the power supply unit, and forcibly shut off the output from each inverter when abnormal temperature rises. This method not only has a large error in the temperature detector itself (for example, ± 5 ° C. in the case of a thermal guard), but also has a certain margin for the worst value of operating conditions such as temperature change. May not be detected by the temperature detector even in abnormal condition.
There is a possibility of a secondary disaster due to the operation in the unexpected overload mode as described above. [0004] The present invention has been made in view of the above problems, unnecessary
To prevent an unexpected shutdown function from operating.
Moni, secondary disasters due to the operation of the overload mode for each inverter, to provide a Switching power supply to anti <br/> stopped more securely, yet easy single circuit configuration Oh Ru. According to the present invention, a plurality of inverters each having a switching element and a transformer are connected in parallel, and an output smoothing choke coil is individually connected to the output side of each inverter. In a switching power supply device configured to supply a DC output voltage between output terminals common to the respective inverters, a voltage monitoring circuit for monitoring a voltage between the respective choke coils, and each monitoring from the voltage monitoring circuit. A failure detection circuit for detecting a failure of each of the inverters based on a signal , wherein the failure detection circuit
Are the respective monitoring signals from the voltage monitoring circuit and the first reference voltage.
And one of the monitor signals is the first reference voltage.
Outputs a failure detection signal when the voltage level falls below
A first comparator and each monitor from the voltage monitoring circuit
Comparing the signal with the second reference voltage, and if one of the monitoring signals is
When the voltage reaches the voltage level of the second reference voltage or more,
Permits output of the failure detection signal from the first comparator
Ru der that a second comparator that. With the above arrangement, the choke voltage between the choke coils generated when the switching element is switched is monitored by the power supply monitoring circuit, and based on the monitoring signal, the failure detection circuit determines the operation status of each inverter. Judge properly. Also, simply having a first comparator
In this case, the failure detection circuit detects the difference between each monitoring signal and the first reference voltage.
Outputs a failure detection signal for each inverter based on the comparison result
can do. In addition, one of the monitoring signals is
Only when the voltage level of the reference voltage or higher is reached,
The output of the fault detection signal from the comparator is permitted.
To prevent accidental activation of the shutdown function
Together with the operation of each inverter in the overload mode.
Secondary disasters can be more reliably prevented. Embodiments of the present invention will be described below with reference to the accompanying drawings. FIG. 1 shows a first embodiment of the present invention applied to a forward converter. In FIG. 1, reference numeral 2 denotes a transformer for insulating a primary side from a secondary side, and reference numeral 1 denotes a primary winding of the transformer 2. The transformer 2 is a transistor, and the transformer 2 and the transistor 1 constitute an inverter 3 to which a DC input voltage Vi is applied.
Reference numeral 3A denotes an inverter having the same configuration as the inverter 3 having the transformer 2A and the transistor 1A as a switching element. A plurality of these inverters 3 and 3A are connected in parallel in the device. In the present embodiment, the transistors 1 and 1A are used as switching elements, but a MOS-type FET having a high switching speed may be used. Also, three or more inverters 3 and 3A may be connected in parallel according to the output power. On the output side of each inverter 3, 3A, a rectifier diode 4, 4A connected to one end of the secondary winding of the transformer 2, 2A, and the other end of the secondary winding of the transformer 2, 2A and the rectifier diode 4, 4A
, And output choke coils 6 and 6A connected to the other ends of the secondary windings of the transformers 2 and 2A, respectively. A smoothing capacitor 7 is connected between output terminals + V and -V provided commonly to 3A. The voltage induced in each of the transformers 2 and 2A by the on and off operations of the transistors 1 and 1A is:
Rectified and smoothed through each of these elements, the output terminals + V,
A predetermined DC output voltage Vo is supplied between −V. Reference numeral 8 denotes a control circuit that forms a feedback loop provided commonly to each of the inverters 3 and 3A. The control circuit 8 compares the detection signal CV of the output voltage Vo obtained by the output voltage detection circuit (not shown) with a built-in reference voltage, and based on the comparison result, makes the output voltage Vo constant. In addition, the pulse conduction width of the drive signal to the transistors 1 and 1A is controlled. The control circuit 8 includes:
An overcurrent protection circuit (not shown) for protecting the inverters 3 and 3A from overload is provided. The total output current Io from each of the inverters 3 and 3A is output to the control circuit 8 as a current detection signal OCP by a current detector (not shown), and the overcurrent protection circuit causes the current detection signal OCP to exceed a predetermined voltage level. When each transistor 1,1
Control is performed so as to narrow the pulse width to A. On the output side of each of the inverters 3 and 3A, a choke voltage between the choke coils 6 and between the choke coils 6A is monitored.
, VSENS2 are provided. The voltage monitoring circuit 9 includes a diode 10 having an anode connected to one end of the choke coil 6 for rectifying a choke voltage, a current limiting resistor 11 having one end connected to the cathode of the diode, and another end of the choke coil 6. And a capacitor 12 connected between the other end of the resistor 11 for charging a rectified choke voltage and a discharging resistor 13 of the capacitor 12 connected in parallel with the capacitor 12. The other voltage monitoring circuit 9A also
Identical diode 10A, resistor 11A, capacitor 12A
And a peak rectifier circuit including a resistor 13A. 14 is a monitoring signal VSENS from each voltage monitoring circuit 9, 9A.
1, a failure detection circuit for detecting a failure in each of the inverters 3 and 3A based on VSENS2. This failure detection circuit 14 has a failure in any one of the inverters 3 and 3A, and
When the normal inverter 3 or 3A supplies an output exceeding the maximum output current of the inverter 3 or 3A alone, a shutdown signal SD as a failure detection signal is supplied to the control circuit 8. When the shutdown signal SD is output, the control circuit 8 controls all the inverters 3 and 3A.
The transistors 1 and 1A are controlled so as to forcibly shut off the output. FIG. 2 shows a circuit configuration of the failure detection circuit 14. As shown in FIG. In the figure, a monitoring signal VSENS1 output from one voltage monitoring circuit 9 is applied between an inverting input terminal and an output terminal-V of a comparator 21 constituting a first comparator, and the other voltage monitoring circuit 9A Is applied between the inverting input terminal and the output terminal -V of the comparator 22 which also constitutes the first comparator. Reference numeral 23 denotes a reference power supply that outputs a second reference voltage VREF2 of, for example, DC 2.5 V, and the reference voltage VREF2 is a comparator directly serving as a second comparator.
24 Inverting input terminals and a resistor for voltage division
A first reference voltage VREF1 of, for example, 0.5 V DC is applied to the non-inverting input terminals of the comparators 21 and 22 via 25 and 26. Each of the comparators 21, 22, and 24 is preferably formed of the same IC. In this case, the supply of the power supply voltage can be made common and the circuit can be simplified. In FIG. 2, the operating voltage Vcc is supplied to the comparator 21 for convenience.
The operating voltage Vcc is also supplied to 24, and the ground of not only the comparator 24 but also the comparators 21 and 22 is connected to the output terminal -V. The non-inverting input terminal of the comparator 24 is connected to a pair of diodes 27 and 28 as an OR circuit for selectively applying the monitoring signals VSENS1 and VSENS2, and is connected between the non-inverting input terminal and the output terminal-V of the comparator 24. Is connected to a parallel circuit of a capacitor 29 and a resistor 30. Operating voltage Vcc line and shutdown signal S
A series circuit of a resistor 31 and a diode 32 and a series circuit of a resistor 33 and a diode 34 are connected in parallel between the D lines.
Output terminal is connected, resistor 33 and diode
The output terminal of the comparator 22 is connected to the connection point with 34. The output terminal of the comparator 24 is connected to the shutdown signal SD line, and the diode 32 is connected only when the output terminal of the comparator 24 is at the H level.
The shutdown signal SD is output via the diode 34. In this embodiment, 2
The monitoring signals VSENS1 and VSENS2 for the choke coils 6 and 6A of the three inverters 3 and 3A are output from the respective voltage monitoring circuits 9 and 9A. However, the device is constituted by three or more inverters 3 and 3A. , The voltage monitoring circuits 9, 9A,
Are preferably provided. Failure detection circuit 14 in this case
Are the first comparators 21, 22,... And the diodes 27, 2
,... Are preferably provided in accordance with the number of monitoring signals VSENS1, VSENS2,. As shown in the graph of FIG. 3, the relationship between the monitoring signals VSENS1 and VSENS2 and the output current Io is such that the smaller the output current Io, the lower the choke voltage between the choke coils 6 and between the choke coils 6A. Signal VSE
The voltage levels of NS1 and VSENS2 also decrease. On the other hand, the reference voltage VREF1 of the failure detection circuit 14 is at least the monitoring signal VSENS at the time of no load where the output current Io does not flow.
1 and VSENS2 are set to values lower than the voltage level of each of the monitoring signals VSENS1 and VSENS2, and the reference voltage VREF2 is set to a half of the maximum value Iomax of the output current Io, that is, Io = It is set to a value lower than the voltage levels of the monitoring signals VSENS1 and VSENS2 at Iomax / 2. When there are n or more inverters 3 and 3A, the reference voltage VREF2 is set to a value lower than the voltage level of each monitoring signal VSENS1, VSENS2,... At Io = Iomax / n. Next, the operation of the above configuration will be described. In FIG. 1, when the inverters 3 and 3A are operating normally, the input voltage Vin is intermittently applied to the primary windings of the transformers 2 and 2A by turning on and off the transistors 1 and 1A. , A voltage proportional to the primary winding is induced in the secondary winding. At this time, transistors 1,
If 1A is on, the voltage induced in the secondary windings of transformers 2 and 2A is rectified by rectifier diodes 4 and 4A, and if transistor 1 and 1A are off, they are stored in choke coils 6 and 6A. The obtained energy is supplied to choke coils 6, 6 via flywheel diodes 5, 5A.
A and the output terminal + V,
An output voltage Vo is generated between −V. The control circuit 8 controls the pulse conduction width of the drive signal to each of the transistors 1 and 1A based on the detection signal CV of the output voltage Vo so that the output voltage Vo maintains a constant value. When the total output current Io from each of the inverters 3 and 3A increases due to an overload state and the current detection signal OCP exceeds a predetermined voltage level, the control circuit 8 immediately switches the transistors 1 and 3A.
The pulse width to 1A is narrowed to protect the inverters 3 and 3A and the load (not shown) connected between the output terminals + V and -V. During normal operation of the inverters 3 and 3A, when the transistors 1 and 1A are turned off, the output voltage -Vo is applied between the choke coils 6 and 6A.
And a forward voltage drop VF of the flywheel diodes 5, 5A is added to the voltage of -Vo + VF. The choke voltage generated between the choke coils 6 and between the choke coils 6A is equal to the voltage of the diodes 10 and 9 of the voltage monitoring circuits 9 and 9A.
The current is rectified at 10A, and the capacitors 12, 12A are charged to the peak voltage. Then, the peak-rectified choke voltage is output to the failure detection circuit 14 as monitoring signals VSENS1 and VSENS2, respectively. Monitoring signals VSENS1, VSENS2
Is higher than the reference voltage VREF1, and the output terminals of the comparators 21 and 22 are both at the L level. In this case, the shutdown signal SD is at the L level, and the operation of the inverters 3 and 3A continues. Become. On the other hand, when one inverter 3 fails, the output current of the other normally operating inverter 3A is the maximum output current of the inverter 3A alone, that is, in this case, Iomax / 2 Is exceeded, no choke voltage is generated between the choke coils 6 on the faulty inverter 3 side, and the voltage level of the monitor signal VSENS1 is 0 V
And the monitoring signal VSENS2 of the normally operating inverter 3A becomes higher than the reference voltage VREF2. Therefore, the voltage level of the monitor signal VSENS1 is changed to the reference voltage VRE.
F1; the output terminal of one comparator 21 of the failure detection circuit 14 goes to H level;
22 is at the L level. On the other hand, the monitor signal VSENS2 having a high voltage level is applied to the inverting input terminal of the comparator 24 via the diode 28,
The output terminal of the comparator 24 is H
Become a level. Therefore, in this case, the H-level shutdown signal SD is output from the comparator 21 via the diode 32, and the operation of the inverters 3 and 3A is forcibly stopped. Also, monitor signals VSENS1, VSENS2
If the voltage level of the comparator 24 does not reach the reference voltage VREF2, the output terminal of the comparator 24 is at the L level even if the output terminal of one of the comparators 21 and 22 is at the H level. When a current flows into the terminal, the shutdown signal SD does not go to the H level. That is, one of the monitor signals VSENS1 and VSENS
2 exceeds the reference voltage VREF2 and the comparator
Only when the output terminal 24 has reached the H level, the H-level shutdown signal SD is output from the comparators 21 and 22 via the diodes 32 and 34. As described above, according to the above embodiment, focusing on the choke voltage generated between the choke coils 6 and between the choke coils 6A, the voltage monitoring circuits 9 and 9A for monitoring the choke voltage are connected to the inverters 3 and 9 respectively. 3A and each monitoring signal VSE from the voltage monitoring circuits 9 and 9A.
By providing a failure detection circuit 14 for detecting a failure of each of the inverters 3 and 3A based on NS1 and VSENS2, one of the inverters 3 and 3A fails and the remaining normal inverters 3 and 3A output more than their capacity. The state in which power is supplied is determined between the choke coils 6 and the choke coils 6A.
It is possible to accurately know the change in the choke voltage between the inverters 3 and 3A, and it is possible to reliably prevent the secondary disaster caused by the operation in the overload mode for each of the inverters 3 and 3A. [0016] In this embodiment, the comparator 21 to a single,
The fault detection circuit 14 is provided with only each of the monitoring signals VSENS
1, a shutdown signal SD as a failure detection signal can be output for each of the inverters 3 and 3A based on a comparison result between the first reference voltage VREF1 and VSENS2. The next disaster,
This can be prevented by a circuit configuration using simple comparators 21 and 22. Further, in this embodiment , the first comparator
In addition to the shut-down signals SD from the comparators 21 and 22, only when one of the monitor signals VSENS1 and VSENS2 reaches or exceeds the voltage level of the second reference voltage VREF2.
Since the first and second comparators 21, 22, and 24 detect a failure of each of the inverters 3 and 3A, a second comparator 24 is provided. With 24, it is possible to prevent the shutdown function from being carelessly operated, and to more reliably prevent the secondary disaster caused by the operation in the overload mode for each of the inverters 3 and 3A. Next, a second embodiment of the present invention will be described with reference to FIGS. In this embodiment,
The same parts as those in the first embodiment are denoted by the same reference numerals, and the description of the common parts is omitted. This embodiment is applied to a push-pull converter including a pair of switching elements, transistors 41 and 42 and transistors 41A and 42A, and the difference from the first embodiment is as follows. First, the present embodiment has a center tap type rectifier circuit, which is composed of rectifier diodes 43, 44, 43A and 44A connected to respective ends of secondary windings of transformers 2 and 2A. Each of the choke coils 6, 6A is connected to a transformer 2,
It is inserted and connected between the secondary winding center tap of 2A and the output terminal -V. Further, the voltage monitoring circuits 9 and 9A include resistors 45, 45A, 46 and 46A for voltage division, and capacitors 47 and 47A, respectively.
It has. These resistors 45, 46 and 45A, 46A
Is used when the output voltage Vo is a relatively high value, for example, DC 24 V. When the output voltage Vo is a low value, the voltage monitoring circuits 9 and 9 in the first embodiment are used.
A circuit having the same configuration as A can be applied. On the other hand, the other configuration, for example, the configuration of the failure detection circuit 14 is exactly the same as that shown in FIG. The configuration of the control circuit 8 and the like is the same as that of the first embodiment. In this embodiment, the push-pull type converter circuit is shown in FIG. 4. However, if at least the secondary winding side of the transformers 2 and 2A is a center tap type, the present invention can be applied to a half bridge type or full bridge type converter. It is possible to obtain exactly the same operation and effect. In this embodiment, when one of the transistors 41, 41A or the transistors 42, 42A is turned on, the rectifier diode 4 is connected to the secondary winding of the transformer 2, 2A.
Power is supplied to the output terminals + V and -V via the rectifier diodes 45 and 45A.
When the switches 41, 42, 41A and 42A are turned off, power is supplied from the choke coils 6 and 6A to the output terminals + V and -V via the rectifier diodes 44 and 44A or the rectifier diodes 45 and 45A. . Voltage monitoring circuit 9, 9A
Divides the choke voltage generated when both of the transistors 41, 42, 41A and 42A are off after peak rectification and outputs the same to the failure detection circuit 14 as the same monitoring signals VSENS1 and VSENS2 as in the first embodiment. The failure detection circuit 14 determines whether one of the monitor signals VSENS1 and VSENS2 is
When the voltage reaches or falls below the voltage level of REF1, or when one of the monitoring signals VSENS1 and VSENS2 becomes the reference voltage VREF2
And the output terminal of the comparator 24 reaches the H level, the H level shutdown signal S
D is output to forcibly stop the operations of the inverters 3 and 3A. As described above, also in the above-described embodiment, the situation in which a certain inverter 3, 3A fails and the remaining normal inverters 3, 3A are supplied with output power exceeding the capability is determined by the choke coil 6. The change in the choke voltage between the inverters and the choke coil 6A can be accurately known, and the secondary disaster caused by the operation in the overload mode for each of the inverters 3 and 3A can be reliably prevented. As an effect of the embodiment, the output voltage V
Even when the voltage values of o differ, the voltage monitoring circuit 9,
By simply connecting the voltage dividing resistors 45, 45A, 46, 46A to 9A, the common fault detection circuit 14 allows the inverters 3, 3
Since failure detection can be performed for each A, it is possible to easily achieve commonization of circuits. The present invention is not limited to the above embodiment, and various modifications can be made within the scope of the present invention. According to the first aspect of the present invention, in the switching power supply device, a plurality of inverters each having a switching element and a transformer are connected in parallel, and an output smoothing choke coil is provided on the output side of each of the inverters. In a switching power supply device that is individually connected and configured to supply a DC output voltage between output terminals common to the respective inverters, a voltage monitoring circuit that monitors a voltage between the respective choke coils; and And a failure detection circuit for detecting a failure of each of the inverters based on each of the monitoring signals of the voltage monitoring circuit.
The visual signal is compared with the first reference voltage, and one of the monitoring signals is
If the voltage has reached the voltage level of the first reference voltage or less,
A first comparator for outputting a fault detection signal;
Comparison of each monitoring signal from the monitoring circuit with the second reference voltage
And one of the monitor signals is a voltage level of the second reference voltage.
When the above is reached, a failure from the first comparator
A second comparator for permitting output of the detection signal.
Are those was, inadvertent shutdown feature to work
Overload mode for each inverter.
Is a simple circuit configuration for secondary disasters caused by operation in
However, it is possible to prevent it more reliably .

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a circuit diagram showing a first embodiment of the present invention. FIG. 2 is a circuit configuration diagram of a failure detection circuit. FIG. 3 is a graph showing a relationship between an output current and a monitoring signal. FIG. 4 is a circuit diagram showing a second embodiment of the present invention. [Description of Signs] 1, 1A transistor (switching element) 2, 2A transformer 3, 3A inverter 6, 6A choke coil 9, 9A voltage monitoring circuit 14, failure detection circuit 21, 22, first comparator 24, second comparator 41, 41A, 42, 42A Transistor (switching element)

──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H02M 3/28 H02M 7/48

Claims (1)

(57) Claims 1. A plurality of inverters each having a switching element and a transformer are connected in parallel, and an output smoothing choke coil is individually connected to the output side of each of the inverters. In a switching power supply configured to supply a DC output voltage between output terminals common to the inverters, a voltage monitoring circuit that monitors a voltage between the choke coils, and a monitoring signal from the voltage monitoring circuit. A failure detection circuit for detecting a failure of each of the inverters based on the voltage monitoring circuit.
Is compared with the first reference voltage, and the monitoring signal
One of them has reached the voltage level of the first reference voltage or less.
A first comparator for outputting a failure detection signal;
Each monitoring signal from the voltage monitoring circuit and the second reference voltage
And comparing one of the monitor signals with the voltage level of the second reference voltage.
From the first comparator when
A second comparator for permitting output of the failure detection signal;
Switching power supply apparatus characterized by comprising.