JP3365495B2 - Semiconductor device and manufacturing method thereof - Google Patents

Semiconductor device and manufacturing method thereof

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Publication number
JP3365495B2
JP3365495B2 JP18657499A JP18657499A JP3365495B2 JP 3365495 B2 JP3365495 B2 JP 3365495B2 JP 18657499 A JP18657499 A JP 18657499A JP 18657499 A JP18657499 A JP 18657499A JP 3365495 B2 JP3365495 B2 JP 3365495B2
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JP
Japan
Prior art keywords
film
copper
semiconductor device
electrode pad
insulating film
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Expired - Fee Related
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JP18657499A
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Japanese (ja)
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JP2001015549A (en
Inventor
政由 田上
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NEC Corp
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NEC Corp
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Publication of JP2001015549A publication Critical patent/JP2001015549A/en
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Publication of JP3365495B2 publication Critical patent/JP3365495B2/en
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  • Engineering & Computer Science (AREA)
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  • Microelectronics & Electronic Packaging (AREA)
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  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【発明の属する技術分野】本発明は、銅や銅系合金を配
線材料として用いた半導体装置に関するもので、特に銅
や銅系合金を電極パッドに用いた半導体装置に関するも
のである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device using copper or a copper alloy as a wiring material, and more particularly to a semiconductor device using copper or a copper alloy for an electrode pad.

【０００２】[0002]

【従来の技術】従来より半導体装置の配線材料には、低
抵抗性、加工性などの観点から、アルミニウム（Ａｌ）
やＡｌ系合金が用いられてきた。しかし、半導体装置の
高集積化が進むにつれて、Ａｌ系配線には様々な問題が
生じてきている。たとえば、Ａｌの比抵抗は比較的小さ
いものの、微細化が進むにつれて、Ａｌ配線全体の抵抗
が上昇し、半導体装置が動作中に発熱するため、誤作動
を引き起こしている。また、Ａｌは融点が低いために、
容易にマイグレーションするため、配線の信頼性を確保
することが困難となってきている。2. Description of the Related Art Conventionally, aluminum (Al) has been used as a wiring material for semiconductor devices from the viewpoint of low resistance and workability.
Al alloys have been used. However, as the degree of integration of semiconductor devices has increased, various problems have arisen in Al-based wiring. For example, although the specific resistance of Al is relatively small, as the miniaturization progresses, the resistance of the entire Al wiring increases, and the semiconductor device generates heat during operation, causing malfunction. Also, since Al has a low melting point,
Since the migration is easy, it is becoming difficult to secure the reliability of the wiring.

【０００３】最近では、これらのＡｌの弱点を克服する
ために、Ａｌよりも約４０％比抵抗が低く、また約４０
０℃融点が高い銅、または銅系合金を半導体装置の配線
に用いる試みがなされている。Recently, in order to overcome these weak points of Al, the specific resistance thereof is lower than that of Al by about 40% and about 40%.
Attempts have been made to use copper or a copper-based alloy having a high melting point of 0 ° C. for wiring of a semiconductor device.

【０００４】図２５に、ボンディングワイヤ結線用の電
極パッドに、銅を用いた半導体装置の断面図の公知例を
示す（特開平７−２０１９０９）。この例の場合、半導
体基板１上に、絶縁膜（シリコン酸化膜）２を介して、
Ｔａ、ＴａＮなどの保護膜（密着膜）３により被覆され
た、電極パッドを構成する銅膜４が形成され、さらにそ
の上にパッシベーション膜５を堆積後、電極パッド上の
パッシベーション膜５及び密着膜３が開口されて、銅膜
が露出した構造となっている。そして、その銅膜の露出
部にボンディングワイヤ６が結線されている。このと
き、ボンディングワイヤ６の材料としては金（Ａｕ）や
Ａｌが用いられ、超音波や加熱によりボンディングワイ
ヤ６と電極パッドを構成する銅膜４が圧着されるように
なっている。超音波印加の場合には約２００℃、加熱の
際には約４００℃でワイヤボンディングが行われる。FIG. 25 shows a known example of a sectional view of a semiconductor device in which copper is used for an electrode pad for connecting a bonding wire (Japanese Patent Laid-Open No. 7-201109). In the case of this example, on the semiconductor substrate 1, an insulating film (silicon oxide film) 2 is interposed,
A copper film 4 constituting an electrode pad, which is covered with a protective film (adhesion film) 3 such as Ta or TaN, is formed, and a passivation film 5 is further deposited on the copper film 4, and then the passivation film 5 and the adhesion film on the electrode pad. 3 is opened so that the copper film is exposed. The bonding wire 6 is connected to the exposed portion of the copper film. At this time, gold (Au) or Al is used as the material of the bonding wire 6, and the bonding wire 6 and the copper film 4 forming the electrode pad are pressure bonded by ultrasonic waves or heating. Wire bonding is performed at about 200 ° C. when applying ultrasonic waves, and at about 400 ° C. when heating.

【０００５】ところが、銅は大気雰囲気中で約１７０℃
以上に加熱すると表面が酸化され、さらにＡｌと異なり
酸化が膜の内部まで非常に早く進行するために銅膜全体
が銅酸化膜になってしまう。その場合、電極パッドの抵
抗の上昇による導通不良や、ボンディングワイヤとの圧
着不良による断線等が発生し、半導体装置の信頼性や歩
留まりが低下する。However, copper is about 170 ° C. in the atmosphere.
When heated above, the surface is oxidized, and further, unlike Al, the oxidation progresses very quickly to the inside of the film, so that the entire copper film becomes a copper oxide film. In that case, a conduction failure due to an increase in the resistance of the electrode pad, a disconnection due to a crimping failure with the bonding wire, and the like occur, and the reliability and the yield of the semiconductor device are reduced.

【０００６】この問題点を解決するために、電極パッド
の銅膜を酸化防止金属膜で皮膜し、ワイヤボンディング
中に銅膜が酸化されることを防ごうとする試みがなされ
ている。図２６は、特開平８−７８４１０にて開示され
た、酸化防止金属膜を含む多層構造を有する銅製電極パ
ッドの断面図である。半導体基板１１上に、絶縁膜１
２、電極パッドを構成する銅膜１６、および表面保護膜
１９が堆積されており、表面保護膜１９の一部がボンデ
ィング用開口部２０として開口されている。そして、こ
のボンディング用開口部２０に存在する、電極パッドを
構成する銅膜１６上には、拡散防止膜１７および酸化防
止金属膜１８が堆積されており、銅膜は露出していない
構造となっている。そしてボンディングワイヤ２１は、
拡散防止膜１７および酸化防止金属膜１８を介して、電
極パッドを構成する銅膜１６に結線された構造となって
いる。In order to solve this problem, an attempt has been made to coat the copper film of the electrode pad with an antioxidant metal film to prevent the copper film from being oxidized during wire bonding. FIG. 26 is a cross-sectional view of a copper electrode pad having a multilayer structure including an anti-oxidation metal film, which is disclosed in JP-A-8-78410. The insulating film 1 is formed on the semiconductor substrate 11.
2, the copper film 16 forming the electrode pad, and the surface protection film 19 are deposited, and a part of the surface protection film 19 is opened as a bonding opening 20. Then, the diffusion prevention film 17 and the oxidation preventing metal film 18 are deposited on the copper film 16 forming the electrode pad existing in the bonding opening 20, so that the copper film is not exposed. ing. And the bonding wire 21 is
The structure is such that it is connected to the copper film 16 forming the electrode pad via the diffusion prevention film 17 and the oxidation preventing metal film 18.

【０００７】[0007]

【発明が解決しようとする課題】ところが従来の酸化防
止金属膜を含む多層膜構造を有する銅製電極パッドには
以下の課題があり、銅の容易に酸化されやすいという欠
点を克服し、銅の高集積化に適する性質を生かした、銅
製電極パッドの本格的実用には至っていない。However, conventional copper electrode pads having a multilayer film structure including an anti-oxidation metal film have the following problems, and overcome the drawback that copper is easily oxidized, and the high copper Copper electrode pads, which take advantage of the properties suitable for integration, have not yet been put into full-scale practical use.

【０００８】第１の課題として、多層構造を有する従来
の銅製電極パッドは、ボンディングワイヤ圧着時に印加
される超音波の振動により、圧着中に絶縁膜より容易に
剥離することが挙げられる。これは、従来の電極パッド
においては、銅膜は酸化防止金属膜により被覆されてお
り表面には露出していないものの、電極パッドの全体は
絶縁膜の表面に突出した構造となっており、振動などの
機械的ストレスにより容易に剥離しやすいという構造上
の問題に起因する。さらに、表面保護膜を備える従来の
電極パッドの場合、図２６に例示したように、銅膜上の
酸化防止金属膜を含む多層膜の一部が該表面保護膜上に
露出した形態となっており、さらに剥離しやすい構造と
なってる。A first problem is that the conventional copper electrode pad having a multi-layer structure is easily separated from the insulating film during pressure bonding due to vibration of ultrasonic waves applied during pressure bonding of the bonding wire. In the conventional electrode pad, the copper film is covered with the anti-oxidation metal film and is not exposed on the surface, but the entire electrode pad has a structure protruding onto the surface of the insulating film. It is caused by a structural problem that it is easily peeled off due to mechanical stress such as. Further, in the case of the conventional electrode pad including the surface protective film, as shown in FIG. 26, a part of the multilayer film including the antioxidant metal film on the copper film is exposed on the surface protective film. And has a structure that is easier to peel off.

【０００９】上記課題は、絶縁膜として低誘電率の膜を
用いた場合に一層顕著となる。半導体装置内の配線相互
の絶縁を行うために用いられる絶縁膜は、現状において
はシリコン酸化膜が用いられているが、配線遅延減少に
伴う性能向上の観点からは、シリコン酸化膜よりも比誘
電率が低い材料を用いる方が有利であり、現在、ＨＳＱ
（Ｈｙｄｒｏｇｅｎ Ｓｉｌｉｓｅｓｑｕｉｏｘａｎ
ｅ）膜等の膜の利用が盛んに検討されている。ところ
が、このような膜を用いた場合、銅膜と絶縁膜、あるい
は、拡散防止膜と絶縁膜との間の密着性が低下し、ボン
ディングの際の機械的なストレスによる剥離が一層発生
しやすくなる。The above problem becomes more remarkable when a low dielectric constant film is used as the insulating film. Silicon oxide film is currently used as an insulating film used to insulate wires from each other in a semiconductor device. However, from the viewpoint of performance improvement due to decrease in wiring delay, relative dielectric constant is higher than that of silicon oxide film. It is more advantageous to use a material with a lower rate and currently HSQ
(Hydrogen Silicesquioxan
e) The utilization of membranes such as membranes is being actively investigated. However, when such a film is used, the adhesion between the copper film and the insulating film, or the diffusion prevention film and the insulating film is reduced, and peeling due to mechanical stress during bonding is more likely to occur. Become.

【００１０】第２の課題として、多層構造を有する従来
の銅製電極パッドにおいては、ボンディングワイヤ圧着
時行われる加熱操作や超音波印加操作により、圧着中に
酸化防止金属膜を含む多層膜が銅膜より容易に剥離する
ことが挙げられる。これは、従来の電極パッドは、電極
パッド形成部でまず銅膜を覆う表面保護膜などが開口さ
れ、その後酸化防止金属膜を含む多層膜で銅膜を覆う工
程で製造されるため、銅膜が開口の際に用いられる化学
薬品などに曝されるため、該銅の表面が劣化し、その後
成膜された膜との接着性が悪いという問題に起因する。As a second problem, in the conventional copper electrode pad having a multi-layer structure, the multi-layer film including the anti-oxidation metal film is formed during the crimping by the heating operation or the ultrasonic wave applying operation performed at the time of crimping the bonding wire. It may be peeled more easily. This is because the conventional electrode pad is manufactured in a process of first opening a surface protective film covering the copper film in the electrode pad forming portion and then covering the copper film with a multilayer film including an antioxidant metal film. Is exposed to the chemicals used during opening, so that the surface of the copper is deteriorated and the adhesion with the film formed thereafter is poor.

【００１１】第３の課題は従来の電極パッドを具備する
半導体装置を電子部品として使用する上での問題であ
る。すなわち、従来の電極パッドでは、酸化防止金属膜
を含む多層膜が半導体装置の表面に突出した構造となっ
ているため、半導体装置間の電極パッドが接触しないよ
うにするため、該半導体装置の間に間隔を設ける必要が
あり、該半導体装置を十分高密度に配置できない。The third problem is a problem in using a conventional semiconductor device having an electrode pad as an electronic component. That is, in the conventional electrode pad, since the multilayer film including the anti-oxidation metal film has a structure protruding on the surface of the semiconductor device, in order to prevent the electrode pad between the semiconductor devices from contacting each other, Therefore, the semiconductor devices cannot be arranged at a sufficiently high density.

【００１２】第４の課題は製造工程に関するものであ
る。従来の電極パッドを製造する方法は、拡散防止膜と
酸化防止金属膜の不要な部分を除去するための目合わせ
工程や、表面保護膜の開口部を作成するための露光、現
像工程など多数の工程よりなり、複雑である。このた
め、従来法では歩留まりが低く、製造コストが高かっ
た。本発明は上記事情に鑑みてなされたものであり、
ワイヤボンディング中に、電極パッドが絶縁膜や絶縁膜
上の拡散防止膜から剥離することなく、ワイヤボンデ
ィング中に、酸化防止金属膜を含む多層膜が銅膜より剥
離することなく、該電極パッドを具備することにより
十分高密度に配置可能で、良好な生産性を有する、電
極パッドを備えた半導体装置を提供することを目的とす
る。The fourth problem relates to the manufacturing process. The conventional method of manufacturing an electrode pad involves a number of steps such as a aligning process for removing unnecessary portions of the diffusion prevention film and the oxidation preventing metal film, an exposure process for forming an opening of the surface protection film, and a development process. It consists of processes and is complicated. Therefore, the conventional method has a low yield and a high manufacturing cost. The present invention has been made in view of the above circumstances,
During wire bonding, the electrode pad does not peel off from the insulating film or the diffusion prevention film on the insulating film, and during wire bonding, the multilayer film including the antioxidant metal film does not peel off from the copper film. An object of the present invention is to provide a semiconductor device provided with an electrode pad, which can be arranged in a sufficiently high density by including it and has good productivity.

【００１３】[0013]

【課題を解決するための手段】上記課題を解決する本発
明によれば、半導体基板上に形成された凹部を有する絶
縁膜と、該凹部に埋め込まれた電極パッドとを備える半
導体装置であって；該電極パッドは、該凹部の内面を覆
う銅系膜と、該銅系膜を覆う酸化防止金属膜とを含んで
なり；該電極パッドを構成する銅系膜の下面が、該絶縁
膜中に形成された銅系アンカー層にビアを介して接続さ
れており；該銅系アンカー層は、該絶縁膜中に形成され
た銅系配線と併用されることを特徴とする半導体装置が
提供される。ここで、本発明における電極パッドとは、
半導体装置に外部より電圧を印加するに必要なボンディ
ングワイヤが結線される部分を意味し、銅系とは、銅お
よび銅を主成分とする合金を意味し、酸化防止金属膜と
は、ボンディングワイヤ結線時に印加される熱や振動に
よって、銅系膜が酸化されることを防ぐ機能を有する金
属膜を意味する。また、前記電極パッドが、半導体基板
上に形成された凹部に埋め込まれた構造となるには、銅
系膜と酸化防止金属膜の膜厚の和は、凹部の深さ以下で
なければならない。According to the present invention for solving the above problems, there is provided a semiconductor device comprising an insulating film having a recess formed on a semiconductor substrate and an electrode pad embedded in the recess. The electrode pad includes a copper-based film that covers the inner surface of the recess and an antioxidant metal film that covers the copper-based film; the lower surface of the copper-based film that constitutes the electrode pad is the insulating film.
Connected via a via to the copper-based anchor layer formed in the film.
The copper-based anchor layer is formed in the insulating film.
Provided is a semiconductor device characterized by being used together with a copper-based wiring . Here, the electrode pad in the present invention means
A semiconductor wire means a portion to which a bonding wire necessary for applying a voltage from the outside is connected, copper-based means copper and an alloy containing copper as a main component, and an antioxidant metal film is a bonding wire. It means a metal film having a function of preventing the copper-based film from being oxidized by heat or vibration applied at the time of connection. Further, in order to have a structure in which the electrode pad is embedded in the recess formed on the semiconductor substrate, the sum of the film thicknesses of the copper-based film and the anti-oxidation metal film must be equal to or less than the depth of the recess.

【００１４】本発明においては、前記電極パッドを構成
する銅系膜の下面が、前記絶縁膜中に形成された銅系ア
ンカー層に接続されていることを特徴とする半導体装置
が提供される。ここで、本発明における銅系アンカー層
とは、前記電極パッドと前記絶縁膜の密着性を向上する
杭として働くものであり、電極パッドの下方に位置する
絶縁膜中に形成され、銅系膜と接続されており、配線と
して絶縁膜中に形成されている銅系配線とは区別される
が、必要に応じて配線として併用されても構わない。In the present invention, there is provided a semiconductor device characterized in that a lower surface of a copper-based film forming the electrode pad is connected to a copper-based anchor layer formed in the insulating film. Here, the copper-based anchor layer in the present invention functions as a pile for improving the adhesion between the electrode pad and the insulating film, and is formed in the insulating film located below the electrode pad. Although it is distinguished from a copper-based wiring which is connected to the wiring and is formed in the insulating film as the wiring, it may be used together as the wiring if necessary.

【００１５】また、本発明によれば、半導体基板上に形
成された凹部を有する絶縁膜と、該凹部の内面を覆う銅
系膜および該銅系膜を覆う酸化防止金属膜を含んでなる
電極パッドとを有する半導体装置であって、前記銅系膜
の下面に接続するように形成された銅系アンカー層を、
前記絶縁膜中に備えることを特徴とする半導体装置が提
供される。Further, according to the present invention, an electrode including an insulating film having a recess formed on a semiconductor substrate, a copper-based film covering the inner surface of the recess, and an antioxidant metal film covering the copper-based film. A semiconductor device having a pad, wherein a copper-based anchor layer formed so as to be connected to a lower surface of the copper-based film,
A semiconductor device is provided which is provided in the insulating film.

【００１６】本発明においては、前記銅系アンカー層の
形状は杭状であってよい。本発明による半導体装置にあ
って、電極パッドを構成する銅系膜の下面が、絶縁膜中
に形成された銅系アンカー層に接続されていれば、該銅
系アンカー層は、ボンディングワイヤ結線時に前記電極
パッドの剥離を防ぐように働く。杭状の形状とは、該働
きをさらに効果的にする形状を意味しており、たとえば
以下のように定義される。すなわち、銅系膜や酸化防止
金属膜を堆積する方向に向く軸に対して、この軸に垂直
な方向の銅系アンカー層の断面積を考えた場合、ある軸
上の位置での断面積が、該位置より表面より離れている
位置での断面積以下である。杭状の形状の具体的な例と
しては、前記軸を含む方向の前記銅系アンカー層の断面
形状の全体、もしくはその一部が、正方形、長方形、逆
Ｔ字、台形などの場合を挙げることができる。In the present invention, the copper-based anchor layer may have a pile shape. In the semiconductor device according to the present invention, when the lower surface of the copper-based film forming the electrode pad is connected to the copper-based anchor layer formed in the insulating film, the copper-based anchor layer is formed when bonding wires are connected. It works to prevent peeling of the electrode pad. The pile-like shape means a shape that makes the function more effective, and is defined as follows, for example. That is, when considering the cross-sectional area of the copper-based anchor layer in the direction perpendicular to the axis in which the copper-based film or the anti-oxidation metal film is deposited, the cross-sectional area at a certain axial position is , The cross-sectional area at a position farther from the surface than the position is less than or equal to. As a specific example of the pile-shaped shape, the case where the entire cross-sectional shape of the copper-based anchor layer in the direction including the axis or a part thereof is a square, a rectangle, an inverted T-shape, a trapezoid, or the like is given. You can

【００１７】本発明においては、前記絶縁膜と、前記銅
系膜と、前記酸化防止金属膜の一部とを覆うように形成
された表面保護膜を備えている半導体装置が好ましい
が、本発明はこれに限定されるものではない。ここで表
面保護膜とは、表面保護膜形成後に行われる工程におい
て、絶縁膜や銅系膜を保護する働きを有する膜をいい、
たとえば、ホトレジスト形成時に絶縁膜や銅系膜を保護
する。また、酸化防止金属膜の一部とは、たとえば、ボ
ンディングワイヤの結線や、バンプ電極の形成に不必要
な部分を意味する。In the present invention, a semiconductor device having a surface protective film formed so as to cover the insulating film, the copper-based film, and a part of the antioxidant metal film is preferable, but the present invention is preferable. Is not limited to this. Here, the surface protective film means a film having a function of protecting the insulating film and the copper-based film in the step performed after the surface protective film is formed,
For example, the insulating film and the copper-based film are protected when the photoresist is formed. Further, a part of the anti-oxidation metal film means, for example, a part which is not necessary for connecting a bonding wire or forming a bump electrode.

【００１８】本発明においては、前記銅系膜と前記酸化
防止金属膜との間に、拡散防止膜を具備する半導体装置
であっても構わない。ここで拡散防止膜とは、銅系膜を
構成する銅成分が酸化防止金属膜に浸透することを防ぐ
膜である。銅系膜より溶出した微量の銅が酸化防止金属
膜に存在すると、ワイヤボンディング時に印加される熱
により酸化防止金属膜中の銅が酸化され、ボンディング
ワイヤの接続不良や酸化防止金属膜の導通不良を引き起
こす可能性があるが、前記拡散防止膜が存在すれば、酸
化防止金属膜中に銅が存在することはなく、接続不良や
導通不良は起こらない。In the present invention, the semiconductor device may include a diffusion prevention film between the copper-based film and the anti-oxidation metal film. Here, the diffusion prevention film is a film that prevents the copper component forming the copper-based film from penetrating into the antioxidant metal film. If a trace amount of copper eluted from the copper-based film is present in the anti-oxidation metal film, the heat applied during wire bonding oxidizes the copper in the anti-oxidation metal film, resulting in poor connection of the bonding wire and poor conduction of the anti-oxidation metal film. However, if the diffusion preventive film is present, copper does not exist in the antioxidation metal film, and no connection failure or conduction failure occurs.

【００１９】また、上記課題を解決する本発明によれ
ば、（ａ）半導体基板上に絶縁膜を成膜し、該絶縁膜に
凹部を形成する工程と、（ｂ）前記凹部を含む所定の領
域に、銅系膜および酸化防止金属膜をこの順で成膜する
工程と、（ｃ）前記凹部以外の領域に形成された銅系膜
および酸化防止金属膜を除去し、電極パッドを形成する
工程とを含むことを特徴とする半導体装置の製造方法が
提供される。According to the present invention for solving the above-mentioned problems, (a) a step of forming an insulating film on a semiconductor substrate and forming a recess in the insulating film; and (b) a predetermined step including the recess. A step of forming a copper-based film and an antioxidant metal film in this order in the region, and (c) removing the copper-based film and the antioxidant metal film formed in the region other than the recess to form an electrode pad. A method for manufacturing a semiconductor device is provided, including the steps of:

【００２０】さらに、本発明によれば、半導体基板上に
形成された凹部を有する絶縁膜と、該凹部の内面を覆う
銅系膜および該銅系膜を覆う酸化防止金属膜を含んでな
る電極パッドとを有する半導体装置であって、前記銅系
膜の下面に接続するように形成された銅系アンカー層
を、前記絶縁膜中に備えることを特徴とする半導体装置
の製造方法が提供される。Further, according to the present invention, an electrode including an insulating film having a recess formed on a semiconductor substrate, a copper-based film covering the inner surface of the recess, and an antioxidant metal film covering the copper-based film. A semiconductor device having a pad, wherein a copper-based anchor layer formed so as to be connected to a lower surface of the copper-based film is provided in the insulating film. .

【００２１】前記銅系アンカー層の製造方法の具体な例
として、（Ａ）半導体基板上に絶縁膜を成膜し、該絶縁
膜に所定の形態を有する溝を形成する工程と、（Ｂ）前
記溝を含む所定の領域に、前記銅系膜を成膜する工程
と、（Ｃ）前記溝以外の領域に形成された銅系膜を、前
記銅系膜の表面と前記絶縁膜の表面が同一平面内となる
よう除去し、銅系アンカー層を形成する工程とを含み、
電極パッドを形成するに先立ち、前記工程（Ａ）乃至
（Ｃ）を１回以上繰り返すことを特徴とする半導体装置
の製造方法が例示される。ここで所定の形態とは、銅系
アンカー層の必要な形態を形成するために要求される形
で、たとえば、銅系膜や酸化防止金属膜を堆積する方向
の断面形状の全体、もしくはその一部が、正方形、長方
形、台形などの場合を挙げることができる。特に、銅系
アンカー層を前記の逆Ｔ字を含む形状とするには、たと
えば、断面が凹字型の形態である溝を用い、最下層では
ない絶縁膜層の溝の底面積が、該層より下位に存在する
少なくとも１層以上の溝の底面積より小さくなるよう、
前記工程（Ａ）乃至（Ｃ）を２回以上繰り返せばよい。
本発明においては、銅系アンカー層を含む半導体装置の
製造方法として、前記工程（ａ）を行うに先立ち、前記
銅系膜の下面に接続する銅系アンカー層を形成する工程
を含むことを特徴とする半導体装置の製造方法が提供さ
れる。すなわち、前記工程（Ａ）乃至（Ｃ）を１回以上
行ったのち、前記工程（ａ）乃至（ｃ）を行い、前記電
極パッドと、前記銅系膜の下面に接続された銅系アンカ
ー層とを形成する工程を含むことを特徴とする半導体装
置の製造方法が提供される。この製造方法によって、銅
系膜の下面が銅系アンカー層に接続されている、絶縁膜
の凹部に埋め込まれた電極パッドを具備する半導体装置
が提供される。As a specific example of the method for manufacturing the copper-based anchor layer, (A) a step of forming an insulating film on a semiconductor substrate and forming a groove having a predetermined shape in the insulating film; and (B) A step of depositing the copper-based film in a predetermined region including the groove; and (C) a copper-based film formed in a region other than the groove, in which the surface of the copper-based film and the surface of the insulating film are Removing so as to be in the same plane, and forming a copper-based anchor layer,
An example of a method for manufacturing a semiconductor device is characterized in that the steps (A) to (C) are repeated one or more times before forming the electrode pad. Here, the predetermined form is a form required to form a necessary form of the copper-based anchor layer, and for example, the entire cross-sectional shape in the direction of depositing the copper-based film or the anti-oxidation metal film, or one of them. The case where the part is a square, a rectangle, a trapezoid, etc. can be mentioned. In particular, in order to form the copper-based anchor layer into the shape including the inverted T shape, for example, a groove having a concave cross section is used, and the bottom area of the groove of the insulating film layer which is not the lowermost layer is So that it is smaller than the bottom area of at least one groove below the layer,
The steps (A) to (C) may be repeated twice or more.
In the present invention, a method of manufacturing a semiconductor device including a copper-based anchor layer includes a step of forming a copper-based anchor layer connected to a lower surface of the copper-based film prior to performing the step (a). A method of manufacturing a semiconductor device is provided. That is, after performing the steps (A) to (C) one or more times, the steps (a) to (c) are performed, and the electrode pad and a copper-based anchor layer connected to the lower surface of the copper-based film. There is provided a method for manufacturing a semiconductor device, the method including the step of forming and. By this manufacturing method, a semiconductor device having an electrode pad embedded in the recess of the insulating film, in which the lower surface of the copper-based film is connected to the copper-based anchor layer, is provided.

【００２２】さらに、本発明においては、前記工程
（ｃ）の後、前記絶縁膜と、前記銅系膜と、前記酸化防
止金属膜の一部とを覆うように表面保護膜を形成する工
程を含むことを特徴とする半導体装置の製造方法が好ま
しいが、本発明はこれに限定されるものではない。この
製造方法の一例として、前記工程（ｃ）を行ったのち、
前記絶縁膜、前記酸化防止金属膜、および少なくとも前
記銅系膜が覆われている形態となるよう、前記表面保護
膜を成膜する工程と、前記酸化防止金属膜の必要な領域
が露出するように、前記表面保護膜を開口し、前記電極
パッドを形成する工程とよりなる一連の操作を挙げるこ
とができる。ここで必要な領域とは、たとえば、ボンデ
ィングワイヤの結線や、バンプ電極の形成に必要な部分
を意味する。本発明においては、前記銅系膜と前記酸化
防止金属膜との間に、拡散防止膜を形成する工程を含む
ことを特徴とする半導体装置の製造方法であっても構わ
ない。Further, in the present invention, after the step (c), a step of forming a surface protective film so as to cover the insulating film, the copper-based film and a part of the antioxidant metal film is included. Although a method for manufacturing a semiconductor device is preferable, the present invention is not limited to this. As an example of this manufacturing method, after performing the step (c),
Forming the surface protection film so that the insulating film, the antioxidant metal film, and at least the copper-based film are covered; and exposing a necessary region of the antioxidant metal film. In addition, a series of operations including a step of opening the surface protective film and forming the electrode pad can be mentioned. The necessary region here means, for example, a portion necessary for connecting a bonding wire or forming a bump electrode. In the present invention, a method of manufacturing a semiconductor device may include a step of forming a diffusion barrier film between the copper-based film and the antioxidant metal film.

【００２３】本発明による半導体装置は、半導体基板上
に形成された絶縁膜と、前記絶縁膜の所定の位置に形成
された凹部と、前記凹部の内面を皮膜する銅系膜と、前
記銅系膜上の所定の領域を皮膜する酸化防止金属膜とを
含んでなる電極パッドを備えており、ボンディングワイ
ヤは、酸化防止金属膜を介して、銅系膜に結線される。
その結果、以下に再述する、従来の銅系電極パッドの問
題点が、以下のように解決される。A semiconductor device according to the present invention comprises an insulating film formed on a semiconductor substrate, a recess formed at a predetermined position of the insulating film, a copper-based film coating the inner surface of the recess, and the copper-based film. An electrode pad including an anti-oxidation metal film that covers a predetermined region on the film is provided, and the bonding wire is connected to the copper-based film through the anti-oxidation metal film.
As a result, the problems of the conventional copper-based electrode pad, which will be described below, are solved as follows.

【００２４】第１に、多層膜構造を有する従来の銅系電
極パッドは、ボンディングワイヤ圧着時に印加される超
音波の振動により、圧着中に絶縁膜より容易に剥離する
ことが問題となっていた。これは、従来の電極パッドに
おいては、銅系膜は酸化防止金属膜により被覆されてお
り表面には露出していないものの、電極パッドの全体は
絶縁膜の表面に突出した構造となっており、振動などの
機械的ストレスにより容易に剥離しやすいという形態上
の問題に起因する。これに対し本発明では、電極パッド
の全体が、絶縁膜中の所定の位置に形成された凹部内に
埋め込まれた形態となっており、電極パッドと絶縁膜の
接触面積が増大すること、特に電極パッドの側面が絶縁
膜と接触していることから、電極パッドと前記絶縁膜の
密着性が構造的に改良され、その結果、ボンディングワ
イヤ圧着時に電極パッドは剥離しない。First, the conventional copper-based electrode pad having a multilayer film structure has a problem that it is easily peeled off from the insulating film during crimping due to vibration of ultrasonic waves applied during crimping of the bonding wire. . This is because, in the conventional electrode pad, the copper-based film is covered with the antioxidant metal film and is not exposed on the surface, but the entire electrode pad has a structure protruding onto the surface of the insulating film. This is due to a morphological problem that it is easily peeled off due to mechanical stress such as vibration. On the other hand, in the present invention, the entire electrode pad is embedded in the recess formed in the insulating film at a predetermined position, and the contact area between the electrode pad and the insulating film is increased. Since the side surface of the electrode pad is in contact with the insulating film, the adhesion between the electrode pad and the insulating film is structurally improved, and as a result, the electrode pad does not peel off when the bonding wire is pressure bonded.

【００２５】さらに、本発明においては、前記電極パッ
ドの下面が、前記絶縁膜中に形成された銅系アンカー層
に接続されている。この絶縁膜中に形成された銅系アン
カー層は、ワイヤボンディング時に杭として働き、電極
パッドが前記絶縁膜より剥離することを効果的に防ぐ。
この銅系アンカー層は、電極パッドが絶縁膜中に埋め込
まれていない場合でも有効である。杭の働きをする銅系
アンカー層の形状として、杭状であることが望ましい。
ここで杭状とは、銅系膜を堆積する方向に向く軸に対し
て、この軸に垂直な方向の銅系アンカー層の断面積を考
えた場合、ある軸上の位置での断面積が、該位置より表
面より離れている位置での断面積以下である形状をい
う。杭状の形状の具体的な例としては、前記軸を含む方
向の前記銅系アンカー層の断面形状の全体、もしくはそ
の一部が、正方形、長方形、逆Ｔ字、台形などの場合を
挙げることができる。このような形状とすることによ
り、杭の効果をより確実にすることができるからであ
る。さらに前記絶縁膜中の所定の位置に形成された凹部
内に埋め込まれた構造となっている前記電極パッドの下
面が、前記の杭の働きをする銅系アンカー層と接続され
ている場合、埋め込まれている効果と杭の効果の相乗作
用により、電極パッドと前記絶縁膜間の接着性はさらに
良好となる。Further, in the present invention, the lower surface of the electrode pad is connected to the copper-based anchor layer formed in the insulating film. The copper-based anchor layer formed in the insulating film acts as a stake during wire bonding, and effectively prevents the electrode pad from peeling off from the insulating film.
This copper-based anchor layer is effective even when the electrode pad is not embedded in the insulating film. The shape of the copper-based anchor layer that functions as a pile is preferably a pile shape.
Here, the pile shape means that the cross-sectional area at a position on a certain axis is the cross-sectional area of the copper-based anchor layer in the direction perpendicular to the axis oriented in the direction of depositing the copper-based film. , A shape having a cross-sectional area equal to or smaller than the cross-sectional area at a position farther from the surface than the position. As a specific example of the pile-shaped shape, the case where the entire cross-sectional shape of the copper-based anchor layer in the direction including the axis or a part thereof is a square, a rectangle, an inverted T-shape, a trapezoid, or the like is given. You can This is because the effect of the pile can be further ensured by using such a shape. Further, when the lower surface of the electrode pad, which has a structure of being embedded in a recess formed at a predetermined position in the insulating film, is connected to the copper-based anchor layer functioning as the pile, it is embedded. Due to the synergistic effect of the effect of the pile and the effect of the pile, the adhesion between the electrode pad and the insulating film is further improved.

【００２６】また、図２６に例示したとおり、従来の電
極パッドが表面保護膜１９を備える場合、銅膜１６上の
酸化防止金属膜１８を含む多層膜の一部が該表面保護膜
１９上に露出した形態となっており、剥離しやすい構造
となってる。これに対し、図１に例示したとおり、本発
明の半導体装置が表面保護膜１９を具備し、電極パッド
の全体が表面保護膜１９の下部に埋没した構造となって
いる場合、電極パッドと前記絶縁膜１２の密着性はさら
に改良されるが、表面保護膜１９が電極パッドを覆う構
造は、本発明では必ずしも要求されない。Further, as shown in FIG. 26, when the conventional electrode pad is provided with the surface protective film 19, a part of the multilayer film including the antioxidant metal film 18 on the copper film 16 is formed on the surface protective film 19. It is exposed and has a structure that is easy to peel off. On the other hand, as illustrated in FIG. 1, when the semiconductor device of the present invention includes the surface protection film 19 and the entire electrode pad is buried under the surface protection film 19, the electrode pad and the Although the adhesion of the insulating film 12 is further improved, the structure in which the surface protective film 19 covers the electrode pad is not always required in the present invention.

【００２７】第２に、図２６に例示された、多層構造を
有する従来の銅製電極パッドにおいては、ボンディング
ワイヤ圧着時行われる加熱操作や超音波印加操作によ
り、圧着中に拡散防止膜１７が、電極パッドを構成する
銅膜１６より容易に剥離する。これは、従来の電極パッ
ドは、まず銅膜上の表面保護膜などが開口され、その後
拡散防止膜１７で銅膜１６を覆う工程で製造されるた
め、開口時に、電極パッドを構成する銅膜１６が、開口
の際に用いられる化学薬品などに曝され、銅膜１６の表
面が劣化し、その後成膜された拡散防止膜１７との接着
性が悪いためである。これに対し、図１２に例示された
本発明の電極パッドを製造するには、銅膜３４を形成
後、ひきつづき拡散防止膜３９により銅膜３４を覆うた
め、銅膜３４はその後の工程で使用される化学薬品に曝
されず、酸化防止金属膜を含む多層膜と銅膜の良好な密
着性が実現できる。その結果、ボンディングワイヤ圧着
時行われる加熱操作や超音波印加操作により、圧着中に
拡散防止膜３９が、銅膜３４より剥離することはない。
このことは、電極パッドが絶縁膜中に埋め込まれてい
る、銅膜の下面が杭の働きをする銅系アンカー層に接続
されているといった、構造的な密着性の改良効果を補う
ものである。Secondly, in the conventional copper electrode pad having the multilayer structure illustrated in FIG. 26, the diffusion preventing film 17 is formed during the crimping by the heating operation and the ultrasonic wave applying operation which are performed at the time of crimping the bonding wire. It is easily peeled off from the copper film 16 forming the electrode pad. This is because the conventional electrode pad is manufactured in a process in which the surface protection film on the copper film is first opened and then the copper film 16 is covered with the diffusion prevention film 17, so that the copper film forming the electrode pad is formed at the time of opening. This is because 16 is exposed to chemicals used during opening, the surface of the copper film 16 is deteriorated, and the adhesion with the diffusion prevention film 17 formed thereafter is poor. On the other hand, in order to manufacture the electrode pad of the present invention illustrated in FIG. 12, after the copper film 34 is formed, the copper film 34 is continuously covered with the diffusion prevention film 39, so that the copper film 34 is used in the subsequent steps. Good adhesion between the multilayer film including the antioxidant metal film and the copper film can be realized without being exposed to the chemicals. As a result, the diffusion preventive film 39 is not peeled off from the copper film 34 during the pressure bonding due to the heating operation or the ultrasonic wave applying operation performed at the time of pressure bonding of the bonding wire.
This supplements the structural improvement effect of the adhesiveness, such as the electrode pad being embedded in the insulating film and the lower surface of the copper film being connected to the copper-based anchor layer that functions as a pile. .

【００２８】第３に、従来の電極パッドでは、酸化防止
金属膜を含む多層膜が半導体装置の表面に突出した構造
となっているため、半導体装置間の電極パッドが接触し
ないようにするため、該半導体装置の間に間隔を設ける
必要があった。これに対し本発明の場合は、電極パッド
の全体が絶縁膜に設けられた凹部内に埋め込まれている
ため、該半導体装置を極めて近距離に配置することが可
能である。Thirdly, in the conventional electrode pad, since the multilayer film including the anti-oxidation metal film is projected on the surface of the semiconductor device, the electrode pads between the semiconductor devices are prevented from contacting each other. It was necessary to provide a space between the semiconductor devices. On the other hand, in the case of the present invention, since the entire electrode pad is embedded in the recess provided in the insulating film, the semiconductor device can be arranged at an extremely short distance.

【００２９】第４に、従来の電極パッドを製造する方法
は、拡散防止膜と酸化防止金属膜の不要な部分を除去す
るための目合わせ工程や、表面保護膜の開口部を作成す
るための露光、現像工程など多数の工程よりなり、極め
て複雑である。このため、従来法では著しく歩留まりが
低く、製造コストが高価となる。これに対し本発明の半
導体装置は、銅系膜と酸化防止金属膜を含む多層膜を成
膜後、たとえばダマシン法などにより、図１０から図１
１に例示されるように、単純な工程で電極パッドを形成
するため製造方法は簡便で、また、銅系膜を開口用の化
学薬品などに曝すことなく製造することが可能なため、
その結果歩留まりが高く、製造コストは安価となる。Fourthly, the conventional method of manufacturing an electrode pad includes a aligning step for removing unnecessary portions of the diffusion prevention film and the anti-oxidation metal film and an opening for the surface protection film. It consists of many steps such as exposure and development, and is extremely complicated. Therefore, in the conventional method, the yield is remarkably low and the manufacturing cost is high. On the other hand, in the semiconductor device of the present invention, after forming a multilayer film including a copper-based film and an anti-oxidation metal film, for example, by a damascene method or the like, as shown in
1, the manufacturing method is simple because the electrode pad is formed by a simple process, and the copper-based film can be manufactured without exposing it to a chemical agent for opening.
As a result, the yield is high and the manufacturing cost is low.

【００３０】以上に述べた利点を有する半導体装置は、
上述した本発明の半導体装置の製造方法により、好適に
製造することができる。本発明の製造方法によれば、簡
便な工程により、電極パッドと絶縁膜の密着性が良好な
半導体装置を製造することができ、得られた半導体装置
の電極パッドは、ワイヤボンディング時に剥離せず、高
い歩留まりが実現できる。A semiconductor device having the above-mentioned advantages is
The semiconductor device can be suitably manufactured by the above-described method for manufacturing a semiconductor device of the present invention. According to the manufacturing method of the present invention, a semiconductor device having good adhesion between the electrode pad and the insulating film can be manufactured by a simple process, and the electrode pad of the obtained semiconductor device does not peel off during wire bonding. High yield can be realized.

【００３１】[0031]

【発明の実施の形態】本発明においては、前記電極パッ
ドの全体が、前記絶縁膜中の所定の位置に形成された凹
部内に存在することを特徴とする半導体装置が提供され
る。前記電極パッドは酸化防止金属膜および銅系膜を備
えており、前記銅系膜の所定の表面露出部分が前記酸化
防止金属膜によって覆われている。なお、酸化防止金属
膜はアルミニウム（Ａｌ）、金（Ａｕ）、銀（Ａｇ）、
またはこれらを含む合金からなることが好ましく、特に
ＡｌＳｉＣｕ、Ａｌ、Ａｕ、Ａｇ、またはＡｇを主成分
とする合金が好ましい。このような材料を選択すれば、
ワイヤボンディング時に印加される熱や振動により前記
電極パッドの表面が酸化されることはなく、したがっ
て、ボンディングワイヤの接続不良や電極パッドの導通
不良の発生が低減される。BEST MODE FOR CARRYING OUT THE INVENTION In the present invention, there is provided a semiconductor device characterized in that the entire electrode pad is present in a recess formed at a predetermined position in the insulating film. The electrode pad includes an antioxidant metal film and a copper-based film, and a predetermined surface exposed portion of the copper-based film is covered with the antioxidant metal film. The anti-oxidation metal film is made of aluminum (Al), gold (Au), silver (Ag),
Alternatively, it is preferably made of an alloy containing them, and particularly preferably AlSiCu, Al, Au, Ag, or an alloy containing Ag as a main component. If you select such a material,
The surface of the electrode pad is not oxidized by the heat or vibration applied during wire bonding, so that the occurrence of connection failure of the bonding wire and conduction failure of the electrode pad is reduced.

【００３２】本発明において、拡散防止膜は、Ｔｉ、Ｔ
ｉＮ、ＴｉＷ、ＴｉＷＮ、Ｗ、ＷＮ、ＮｂＮ、Ｃｒ、Ｔ
ａ、または、ＴａＮから構成されることが望ましい。特
に、Ｔｉ、ＴｉＮ、ＴｉＷ、ＷＮ、Ｔａ、またはＴａＮ
から構成されることが望ましい。なぜなら、このような
材料を選択すれば、銅系膜と拡散防止膜間や、拡散防止
膜間と酸化防止金属膜間の良好な密着性を保ちつつ、銅
の良好なバリヤ性も実現できるからである。In the present invention, the diffusion prevention film is made of Ti, T
iN, TiW, TiWN, W, WN, NbN, Cr, T
It is desirable to be composed of a or TaN. In particular, Ti, TiN, TiW, WN, Ta, or TaN
It is desirable to be composed of. This is because by selecting such a material, good barrier properties of copper can be realized while maintaining good adhesion between the copper-based film and the diffusion prevention film or between the diffusion prevention film and the antioxidation metal film. Is.

【００３３】この拡散防止膜は、銅系膜を成膜したの
ち、酸化防止金属膜を成膜するまえに形成される。詳し
くは、前記工程（ｂ）において、前記銅系膜と前記拡散
防止膜の膜厚の和が、前記凹部の深さより小さい形態と
なるよう、前記拡散防止膜を成膜する。すなわち、（銅
系膜と拡散防止膜の膜厚の和）＜（前記絶縁膜中の凹部
の深さ）であり、好ましくは、（銅系膜と拡散防止膜の
膜厚の和）＜（前記絶縁膜中の凹部の深さ）≦（銅系膜
と拡散防止膜と酸化防止金属膜の和）である。This diffusion prevention film is formed after the copper-based film is formed and before the anti-oxidation metal film is formed. Specifically, in the step (b), the diffusion prevention film is formed such that the sum of the film thicknesses of the copper-based film and the diffusion prevention film is smaller than the depth of the recess. That is, (the sum of the film thicknesses of the copper-based film and the diffusion prevention film) <(the depth of the recesses in the insulating film), and preferably (the sum of the film thicknesses of the copper-based film and the diffusion prevention film) <( The depth of the recess in the insulating film) ≦ (the sum of the copper-based film, the diffusion prevention film, and the antioxidant metal film).

【００３４】さらに各金属膜の膜厚に関する好ましい数
値を述べるが、本発明はこれらの数値に限定されるもの
ではない。銅系膜は０．３μｍ乃至１μｍの範囲であ
り、拡散防止膜は十分に銅の浸透を防ぐために２０ｎｍ
程度必要であるが、一方で膜厚が厚すぎても電極パッド
部での抵抗の増加を引き起こすため、１００ｎｍを超え
ない程度が望ましい。そして酸化防止金属膜の膜厚につ
いては、ワイヤボンディング時に膜の突き抜け等が起こ
らないようにするために、２００ｎｍ乃至５μｍの範囲
とする。必要に応じて、表面保護膜を５０ｎｍ乃至５μ
ｍの範囲で堆積する。Further, preferable numerical values relating to the film thickness of each metal film will be described, but the present invention is not limited to these numerical values. The copper-based film has a thickness in the range of 0.3 μm to 1 μm, and the diffusion prevention film has a thickness of 20 nm to sufficiently prevent the penetration of copper.
On the other hand, if the film thickness is too thick, it causes an increase in resistance in the electrode pad portion. The thickness of the anti-oxidation metal film is set in the range of 200 nm to 5 μm in order to prevent the film from penetrating during wire bonding. If necessary, a surface protection film of 50 nm to 5μ
Deposit in the range of m.

【００３５】本発明における絶縁膜としては、絶縁性の
良好な膜であれば特に制限はなく、たとえばＳｉＯ
2（２酸化珪素）、ＳｉＮ（窒化珪素）、ＳｉＯＮ（酸
窒化珪素）、ＳｉＯＦ（酸弗化珪素）、ＢＣＢ（Ｂｅｎ
ｚｏＣｙｃｒｏＢｕｔｅｎｅ）、ＨＳＱ（Ｈｙｄｒｏｇ
ｅｎ Ｓｉｌｓｅｓ Ｑｕｉｏｘａｎｅ）、またはａ−
Ｃ：Ｆ(アモルファスフッ化カーボン)より構成すること
ができる。The insulating film in the present invention is not particularly limited as long as it is a film having a good insulating property, for example, SiO.
2 (silicon dioxide), SiN (silicon nitride), SiON (silicon oxynitride), SiOF (silicon oxyfluoride), BCB (Ben
zoCycloButone), HSQ (Hydrog
en Silses Quioxane), or a-
It can be composed of C: F (amorphous fluorocarbon).

【００３６】また、本発明における表面保護膜として
は、ＳｉＮ等の非酸化性物質が用いられる。Further, as the surface protective film in the present invention, a non-oxidizing substance such as SiN is used.

【００３７】杭の働きをする銅系アンカー層を形成する
際に、前記工程（Ｂ）にひきつづき、ＳｉＮなどより構
成される反射防止膜など、適当な機能を有する膜を堆積
してもよい。また、杭の働きをする銅系アンカー層を形
成するのと同時に、銅系配線を同時に形成しても構わな
い。When forming the copper-based anchor layer serving as a pile, a film having an appropriate function such as an antireflection film made of SiN may be deposited following the step (B). Further, the copper-based wiring may be formed simultaneously with the formation of the copper-based anchor layer that functions as a pile.

【００３８】本発明においては、前記電極パッド上の、
前記表面保護膜に覆われていない部分に、バンプ電極が
設けられていても構わない。該バンプ電極は、めっき法
により１５μｍ程度の厚さに、Ａｕ、Ｐｄ（パラジウ
ム）、Ｓｎ（すず）などの金属を堆積させることにより
製造されるが、本発明に示すバンプ電極は、これらの形
状や物質に限定されるものではない。バンプ電極が形成
された本発明の半導体装置は、該半導体装置を表面実装
法により基盤に装着する際などに好適に使用される。In the present invention, on the electrode pad,
A bump electrode may be provided in a portion not covered with the surface protective film. The bump electrode is manufactured by depositing a metal such as Au, Pd (palladium), Sn (tin) to a thickness of about 15 μm by a plating method. It is not limited to materials and substances. The semiconductor device of the present invention on which bump electrodes are formed is preferably used when the semiconductor device is mounted on a substrate by a surface mounting method.

【００３９】[0039]

【実施例】（実施例１）本発明について、表面保護膜と
杭の働きをする銅系アンカー層が具備されている場合に
つき、図１２に構造を例示した。半導体基板３１上に絶
縁膜３２があり、電極パッドの杭の役目を果たす銅系ア
ンカー層３４（ａ）がある。酸化防止金属膜４０は銅の
酸化を防止するためのであり、拡散防止膜３９を介して
銅膜３４（ｂ）が存在する構造となっている。また銅膜
３４（ｂ）の下面は銅系アンカー層３４（ａ）と接続さ
れており、電極パッドの剥離を防いでいる。そして、電
極パッド上に堆積された表面保護膜４１が、酸化防止金
属膜４０上の所定の領域のみで開口されており、その部
分でボンディングワイヤ４２が結線されている。Example 1 FIG. 12 illustrates the structure of the present invention in which a surface protective film and a copper-based anchor layer functioning as a pile are provided. An insulating film 32 is provided on the semiconductor substrate 31, and a copper-based anchor layer 34 (a) serving as a pile of electrode pads is provided. The anti-oxidation metal film 40 is for preventing the oxidation of copper, and has a structure in which the copper film 34 (b) exists via the diffusion prevention film 39. The lower surface of the copper film 34 (b) is connected to the copper-based anchor layer 34 (a) to prevent peeling of the electrode pad. Then, the surface protective film 41 deposited on the electrode pad is opened only in a predetermined region on the antioxidant metal film 40, and the bonding wire 42 is connected at that portion.

【００４０】図２から図１２は本実施例にかかる半導体
装置の配線部の形成、およびワイヤボンディングの様子
を工程順に示す断面図である。半導体基板３１上に絶縁
膜３２を形成する。この絶縁膜はＳｉＯ2（２酸化珪
素）、ＳｉＮ（窒化珪素）、ＳｉＯＮ（酸窒化珪素）、
ＳｉＯＦ（酸弗化珪素）、ＢＣＢ（ＢｅｎｚｏＣｙｃｒ
ｏＢｕｔｅｎｅ）、ＨＳＱ（Ｈｙｄｒｏｇｅｎ Ｓｉｌ
ｓｅs Ｑｕｉｏｘａｎｅ）、ａ−Ｃ：Ｆ(アモルファス
フッ化カーボン)などより構成される。次にこの絶縁膜
３２の所定の領域に、図３に示すような銅系アンカー層
形成用溝３３を形成する。これを形成する際には絶縁膜
を多層構造にしてエッチングストップ用の膜を挿入して
ある場合もある。上面から見ると図４に示すようにな
る。次に、図５に示すように銅膜３４（ａ）を堆積す
る。絶縁膜３２がＳｉＯ2などから構成されており、膜
中に銅が拡散するような場合は、銅の拡散防止膜を銅成
膜前に成膜する。該拡散防止膜に用いられる金属はＴ
ａ、ＴａＮ、ＴｉＮ、ＷＮ等である。その後、銅膜３４
（ａ）と拡散防止膜をＣＭＰ（化学機械研磨；Ｃｈｅｍ
ｉｃａｌ Ｍｅｃｈａｎｉｃａｌ Ｐｏｌｉｓｈｉｎ
ｇ）を用いて研磨し、その上に表面保護膜、エッチング
ストッパー膜、および反射防止膜となるＳｉＮなど３５
を堆積する。そしてその上に再び絶縁膜３２を形成する
（図６）。この時形成された銅膜は実際に半導体素子間
を接続するために用いられるわけではなく、上方に形成
する電極パッドの杭の部分となる銅系アンカー層３４
（ａ）である。2 to 12 are cross-sectional views showing, in the order of steps, formation of the wiring portion and wire bonding of the semiconductor device according to this embodiment. An insulating film 32 is formed on the semiconductor substrate 31. This insulating film is made of SiO 2 (silicon dioxide), SiN (silicon nitride), SiON (silicon oxynitride),
SiOF (silicon acid fluoride), BCB (BenzoCycle)
oButone), HSQ (Hydrogen Sil)
ses Quioxane), aC: F (amorphous fluorocarbon), and the like. Next, a copper-based anchor layer forming groove 33 as shown in FIG. 3 is formed in a predetermined region of the insulating film 32. In forming this, the insulating film may have a multi-layered structure and a film for etching stop may be inserted. When viewed from above, it becomes as shown in FIG. Next, as shown in FIG. 5, a copper film 34 (a) is deposited. When the insulating film 32 is made of SiO 2 or the like and copper diffuses in the film, a copper diffusion preventing film is formed before the copper is formed. The metal used for the diffusion barrier is T
a, TaN, TiN, WN and the like. Then, the copper film 34
CMP (Chemical Mechanical Polishing; Chem)
ical Mechanical Polish
35) which is used as a surface protection film, an etching stopper film, and an antireflection film, and is polished on
Deposit. Then, the insulating film 32 is formed thereon again (FIG. 6). The copper film formed at this time is not used for actually connecting the semiconductor elements, but the copper-based anchor layer 34 that will be a portion of the pile of the electrode pad formed above.
It is (a).

【００４１】次に、図７に示すように前記した銅系アン
カー層３４（ａ）とのコンタクトを取るためのビア孔３
６を絶縁膜３２、反射防止膜３５に形成した後、配線溝
３７と電極パッド形成用開口部３８を絶縁膜３２に形成
する。この図７を上方から見た状態を図８に示す。次
に、ビア孔３６から露出している銅系アンカー層３４
（ａ）の表面を洗浄し、必要に応じて銅の拡散防止膜を
成膜し、続いて銅膜３４（ｂ）を成膜する。この際、デ
ュアルダマシン法を用いることによりビア孔３６と配線
溝３７、電極パッド開口部３８を同時に埋め込む。この
時、銅膜の成膜方法はＣＶＤ法、ＰＶＤ法、めっき法を
用いて行うが、配線溝３７、開口部３８のみに選択的に
埋め込むことは困難であるため絶縁膜３２上にも同時に
堆積する。この際、銅膜の堆積は電極パッド開口部３８
の全体を満たすのではなく、開口部の底と側壁が皮膜さ
れる程度で良い。このような形態は、配線部３７と電極
パッド開口部３８の両方を同時に銅で皮膜する場合は、
配線部の幅に比して、電極パッド開口部の幅を大きくす
ることによって実現される。つまり図９に示すように、
銅をビア孔３６、配線溝３７に完全に埋め込み、電極パ
ッド開口部３８においてはの側壁と下部の方にのみ堆積
する。こうしてビア孔３６、配線溝３７と電極パッド部
３８の銅膜３４（ｂ）を同時に成膜することが可能とな
る。また、最初に形成した銅系アンカー層３４（ａ）と
ビア孔３６で銅膜を結合することができる。次に、銅の
拡散防止膜３９をＰＶＤ法、ＣＶＤ法により成膜する。
この拡散防止膜はＴｉＮ、ＴｉＷ、ＴｉＷＮ、Ｗ、Ｗ
Ｎ、ＮｂＮ、Ｃｒ、Ｔａ、ＴａＮを用いることができ
る。さらにその上から酸化防止金属膜４０を成膜する。
酸化防止金属膜４０はＡｌＳｉＣｕ、Ａｌ、Ａｕ、Ａ
ｇ、或いはＡｇを主体とした合金を用いることができ
る。こうして形成された構造について図１０に示す。こ
の図から判るとおり、銅膜と拡散防止膜を堆積した時点
においては開口部中の膜厚は開口部の深さよりも薄い必
要がある。そして、酸化防止金属膜を堆積してはじめて
開口部の深さよりも積層された電極パッドの膜の厚さが
厚くなるようにする。つまり、（銅膜と拡散防止膜の膜
厚の和）＜（開口部の深さ）≦（銅膜と拡散防止膜と酸
化防止金属膜の和）を満たす必要がある。Next, as shown in FIG. 7, a via hole 3 for making contact with the above-mentioned copper-based anchor layer 34 (a).
After 6 is formed on the insulating film 32 and the antireflection film 35, the wiring groove 37 and the electrode pad forming opening 38 are formed on the insulating film 32. FIG. 8 shows a state of FIG. 7 viewed from above. Next, the copper-based anchor layer 34 exposed from the via hole 36.
The surface of (a) is washed, a copper diffusion preventing film is formed if necessary, and then a copper film 34 (b) is formed. At this time, the via hole 36, the wiring groove 37, and the electrode pad opening 38 are simultaneously filled by using the dual damascene method. At this time, although the copper film is formed by using the CVD method, the PVD method, or the plating method, it is difficult to selectively fill only the wiring groove 37 and the opening 38, and thus the copper film is simultaneously formed on the insulating film 32. accumulate. At this time, the copper film is deposited on the electrode pad opening 38.
It is sufficient that the bottom and side walls of the opening are coated instead of filling the entire area. In such a form, when both the wiring portion 37 and the electrode pad opening portion 38 are coated with copper at the same time,
It is realized by making the width of the electrode pad opening larger than the width of the wiring portion. That is, as shown in FIG.
Copper is completely buried in the via hole 36 and the wiring groove 37, and is deposited only on the side wall and the lower part of the electrode pad opening 38. Thus, the via hole 36, the wiring groove 37, and the copper film 34 (b) of the electrode pad portion 38 can be simultaneously formed. Further, the copper film can be bonded to the copper-based anchor layer 34 (a) formed first and the via hole 36. Next, the copper diffusion preventing film 39 is formed by the PVD method or the CVD method.
This diffusion barrier film is made of TiN, TiW, TiWN, W, W
N, NbN, Cr, Ta, TaN can be used. Further, an anti-oxidation metal film 40 is formed thereon.
The antioxidant metal film 40 is made of AlSiCu, Al, Au, A.
An alloy mainly containing g or Ag can be used. The structure thus formed is shown in FIG. As can be seen from this figure, the film thickness in the opening must be smaller than the depth of the opening when the copper film and the diffusion barrier film are deposited. Then, only when the antioxidant metal film is deposited, the film thickness of the laminated electrode pad is made thicker than the depth of the opening. In other words, it is necessary to satisfy (sum of film thickness of copper film and diffusion preventing film) <(depth of opening) ≦ (sum of copper film, diffusion preventing film and oxidation preventing metal film).

【００４２】次に電極パッド形成用開口部３８以外の絶
縁膜３２上に堆積した耐酸化性金属、拡散防止膜、銅膜
の除去をＣＭＰを用いて行う。また、ＣＭＰの方法とし
てはそれぞれの金属膜を別々の条件で研磨する方法と同
条件で研磨する方法のどちらでも良い。このようにして
形成される構造を図１１に示す。Next, the oxidation resistant metal, the diffusion preventive film and the copper film deposited on the insulating film 32 other than the electrode pad forming openings 38 are removed by CMP. The CMP method may be either a method of polishing each metal film under different conditions or a method of polishing each metal film under the same conditions. The structure thus formed is shown in FIG.

【００４３】次に、表面保護膜４１を堆積する。この表
面保護膜４１は電極パッド表面の銅膜３４（ｂ）が露出
している部分が酸化されるのを防止するためにＳｉＮ等
の非酸化性物質である必要がある。そして、電極パッド
部を露出するために表面保護膜４１のパターニングを行
う。この時、大気雰囲気やボンディング時における銅の
酸化を防止するために、銅膜３４（ｂ）の電極パッド表
面部は露出させないようにする。つまり、電極パッドの
うち露出させるのは拡散防止膜３９の表面露出部よりも
内側の部分の必要がある。そして、酸化防止金属膜４０
の電極パッド露出部に、ＡｌまたはＡｕからなるボンデ
ィングワイヤ４２を熱圧着法、または超音波圧着法によ
り接合する（図１２）。Next, the surface protection film 41 is deposited. The surface protection film 41 needs to be a non-oxidizing substance such as SiN in order to prevent the exposed portion of the copper film 34 (b) on the electrode pad surface from being oxidized. Then, the surface protection film 41 is patterned to expose the electrode pad portion. At this time, the electrode pad surface of the copper film 34 (b) is not exposed in order to prevent oxidation of copper during the air atmosphere or during bonding. That is, of the electrode pads, it is necessary to expose the inside of the surface exposed portion of the diffusion prevention film 39. Then, the antioxidant metal film 40
A bonding wire 42 made of Al or Au is bonded to the exposed portion of the electrode pad by thermocompression bonding or ultrasonic pressure bonding (FIG. 12).

【００４４】以上より製造された半導体装置の電極パッ
ドはワイヤボンディング時に酸化されることはなく、剥
離や導通不良も起こさず、配線材料として銅を用いるこ
とにより回路内の抵抗、信頼性を向上することができ、
ボンディング部の信頼性を向上させることができた。さ
らに、生産性や歩留まりも極めて良好であった。The electrode pad of the semiconductor device manufactured as described above is not oxidized during wire bonding, does not cause peeling or defective conduction, and improves the resistance and reliability in the circuit by using copper as the wiring material. It is possible,
The reliability of the bonding part could be improved. Furthermore, the productivity and the yield were extremely good.

【００４５】（実施例２）実施例１においては、電極パ
ッドの下面部と接続されていない銅製配線が単層となっ
ている場合の例を挙げたが、銅製配線が多層配線構造に
なっている場合においても同様なプロセスにより電極パ
ッドの作製が可能である。図１３に示すように絶縁膜中
に第１層目の埋め込み銅製配線用開口部４３を形成した
後、その上にＳｉＮ等の反射防止膜やエッチングストッ
プ膜にもなる反射防止膜３５を形成し、続いて絶縁膜３
２を形成する。また、この第１層目の埋め込み配線を形
成する際に同時に実施例１で述べた銅系アンカー層形成
用溝３３も形成する。この時の銅系アンカー層の膜厚は
銅製配線膜厚と同様であり、杭幅はある程度の幅がない
と杭としての役割を果たさず、さらに埋め込む際に配線
部の埋め込み時間とあまり変化させないようにするた
め、１μｍ乃至５μｍ程度の範囲とする。次に、実施例
１と同様に第１層目配線とのコンタクトを取るためのビ
ア孔３６を絶縁膜３２、反射防止膜３５に形成した後、
第２層目の配線溝３７と電極パッド形成用開口部３８を
絶縁膜に形成する。次に、ビア孔３６から露出している
第１層目の銅を洗浄し、実施例１と同様に必要に応じて
銅の拡散防止膜を成膜し、その後銅膜３４（ｂ）を成膜
する。この際、デュアルダマシン法を用いることにより
ビア孔３６と第２層目配線溝３７を同時に埋め込む。さ
らに、第２層目に形成される電極パッド形成溝において
も、実施例１と同様に配線部が埋め込まれた時点で電極
パッド開口部の下部と側面のみに銅が形成されたような
構造になる（図１４）。その後、拡散防止膜３９、酸化
防止金属膜４０を堆積し、ＣＭＰにより絶縁膜３２と電
極パッド部が同じ高さになるように研磨する。そしてＳ
ｉＮ等の表面保護膜４１を堆積し拡散防止膜３９の露出
部の内側のみを開口し、露出した酸化防止金属膜４０の
電極パッド部にワイヤボンディングを行い図１５のよう
な構造を作製する。(Embodiment 2) In Embodiment 1, an example is given in which the copper wiring not connected to the lower surface of the electrode pad is a single layer, but the copper wiring has a multilayer wiring structure. In the case where the electrode pad is present, the electrode pad can be manufactured by the same process. As shown in FIG. 13, after forming a first layer embedded copper wiring opening 43 in the insulating film, an antireflection film 35 such as SiN or an antireflection film 35 which also serves as an etching stop film is formed thereon. , Then insulation film 3
Form 2. Further, at the same time when the first-layer embedded wiring is formed, the copper-based anchor layer forming groove 33 described in the first embodiment is also formed. The thickness of the copper-based anchor layer at this time is the same as the copper wiring thickness, and the pile width does not function as a pile unless it has a certain width, and does not change much with the embedding time of the wiring part when embedding. For this reason, the range is about 1 μm to 5 μm. Next, after forming a via hole 36 for making contact with the first layer wiring in the insulating film 32 and the antireflection film 35 as in the first embodiment,
The second-layer wiring groove 37 and the electrode pad forming opening 38 are formed in the insulating film. Next, the first layer of copper exposed from the via hole 36 is washed, a copper diffusion preventive film is formed if necessary in the same manner as in Example 1, and then a copper film 34 (b) is formed. To film. At this time, the via hole 36 and the second-layer wiring groove 37 are simultaneously filled by using the dual damascene method. Further, also in the electrode pad forming groove formed in the second layer, a structure in which copper is formed only on the lower portion and the side surface of the electrode pad opening portion at the time when the wiring portion is embedded in the same manner as in the first embodiment. (Fig. 14). Thereafter, a diffusion prevention film 39 and an oxidation preventing metal film 40 are deposited and polished by CMP so that the insulating film 32 and the electrode pad portion have the same height. And S
A surface protection film 41 such as iN is deposited, only the inside of the exposed portion of the diffusion prevention film 39 is opened, and wire bonding is performed on the exposed electrode pad portion of the antioxidation metal film 40 to form a structure as shown in FIG.

【００４６】以上の実施例により、多層銅製配線構造を
持つ半導体装置においても、デュアルダマシンプロセス
を用いて、工程数を増加させることなく銅配線を形成す
ることが可能であり、信頼性の高い電極パッドを有する
半導体装置が製造できた。According to the above embodiments, even in a semiconductor device having a multilayer copper wiring structure, it is possible to form a copper wiring by using the dual damascene process without increasing the number of steps, and a highly reliable electrode is provided. A semiconductor device having a pad can be manufactured.

【００４７】（実施例３）実施例１および２において
は、銅膜３４（ｂ）、拡散防止膜３９、酸化防止金属膜
４０を連続して成膜しＣＭＰすることにより電極パッド
を形成した。この方法は配線溝３７の幅が十分小さい場
合有効であるが、たとえば、配線溝３７の部分が多層配
線となった場合、配線溝３７の幅が大きくなることがあ
る。その場合、配線溝３７の全体積が銅で満たされるま
で銅膜を形成した場合、電極パッド形成用開口部もほぼ
銅で満たされてしまう可能性がある。このような状態
で、拡散防止膜３９、酸化防止金属膜４０を連続成膜し
た場合、図１６のような状態になり、電極パッド用の凹
部内での、酸化防止金属膜４０の形成が不完全となる。
その結果、ＣＭＰを行った場合、図１７に示すように酸
化防止金属膜４０の露出面積が小さく、ボンディングが
困難となる。また、表面保護膜４１をパターニングした
ときに、電極パッド表面部の銅膜３４（ｂ）が露出し、
酸化されてしまう恐れがある。(Embodiment 3) In Embodiments 1 and 2, the copper film 34 (b), the diffusion preventing film 39, and the antioxidation metal film 40 are successively formed and CMP is performed to form the electrode pad. This method is effective when the width of the wiring groove 37 is sufficiently small, but the width of the wiring groove 37 may become large when, for example, the portion of the wiring groove 37 is a multilayer wiring. In that case, when the copper film is formed until the entire area of the wiring groove 37 is filled with copper, the opening for electrode pad formation may be almost filled with copper. When the diffusion preventing film 39 and the oxidation preventing metal film 40 are continuously formed in such a state, the state becomes as shown in FIG. 16, and the formation of the oxidation preventing metal film 40 in the recess for the electrode pad is unsuccessful. Be complete.
As a result, when CMP is performed, the exposed area of the antioxidant metal film 40 is small as shown in FIG. 17, and bonding becomes difficult. When the surface protection film 41 is patterned, the copper film 34 (b) on the surface of the electrode pad is exposed,
It may be oxidized.

【００４８】このような問題点が回避された例を述べ
る。まず、図１８に示すようにダマシン法を用いた通常
の埋め込み配線を形成するのと同様に銅膜３４（ａ）を
成膜してＣＭＰを行い銅製配線、及び電極パッド部を作
製した後に、その上に表面保護膜４１を成膜する。その
後、表面保護膜をパターニングし電極パッド部上部を開
口し、その上からＰＶＤ法、またはＣＶＤ法により拡散
防止膜３９、酸化防止金属膜４０を成膜する（図１
９）。そして、ＣＭＰ法により酸化防止金属膜４０及び
拡散防止膜３９を平坦化し電極パッド部を形成し、ワイ
ヤボンディングを行う（図２０）。この場合、銅膜３４
（ａ）は開口時に用いられる化学薬品に曝されることと
なり、さらに表面保護膜の下に電極パッドの全体が埋め
込まれている構造とはなっていないが、電極パッド部分
全体は絶縁膜の凹部に埋め込まれた構造となっており、
さらに杭の働きをする銅系アンカー層３４（ｂ）の働き
により、電極パッドと絶縁膜間の密着性は、依然良好で
あった。An example in which such a problem is avoided will be described. First, as shown in FIG. 18, a copper film 34 (a) is formed and CMP is performed to form a copper wiring and an electrode pad portion, as in the case of forming a normal embedded wiring using a damascene method. A surface protective film 41 is formed on top of it. After that, the surface protection film is patterned to open the upper part of the electrode pad portion, and the diffusion prevention film 39 and the oxidation prevention metal film 40 are formed thereon by PVD method or CVD method (FIG. 1).
9). Then, the antioxidant metal film 40 and the diffusion preventive film 39 are planarized by the CMP method to form an electrode pad portion, and wire bonding is performed (FIG. 20). In this case, the copper film 34
(A) is exposed to the chemicals used at the time of opening, and the entire electrode pad is not buried under the surface protection film, but the entire electrode pad part is a recess of the insulating film. It has a structure embedded in
Further, due to the function of the copper-based anchor layer 34 (b) functioning as a pile, the adhesion between the electrode pad and the insulating film was still good.

【００４９】（実施例４）以上の実施例ではワイヤボン
ディング用の電極パッドの形成に関して述べたが、今回
の発明は、これに限らず電極パッド上にバンプ電極を形
成してなる半導体装置にも容易に適用することができ
る。図２１に示すように電極パッド部を実施例１と同様
にして形成する。次に図２２に示すように、表面保護膜
４１のパターニングに用いるフォトレジスト４４を表面
保護膜除去後も残存させる。そして、図２３に示すよう
にめっき法により１５μｍ程度バンプ電極４５となる金
属を堆積させる。この際バンプ電極に用いる金属はＡ
ｕ、Ｐｄ（パラジウム；Ｐａｌｌａｄｉｕｍ）、Ｓｎ
（すず；Ｓｔａｎｎｕｍ）である。酸化防止金属膜４０
がめっき時の電極となるため、下地形成等のプロセスを
省くことが可能となる。バンプ電極４５堆積後、フォト
レジスト４４を除去して図２４に示すようなバンプ電極
４５を形成することができる。以上のことより銅製配線
を用いた半導体装置を、バンプ法によりチップ外部と接
続する場合にも、銅を酸化させずに行うことが可能とな
り信頼性、性能が低減するのを防止することができる。(Embodiment 4) In the above embodiments, the formation of the electrode pad for wire bonding was described. However, the present invention is not limited to this, and a semiconductor device having a bump electrode formed on the electrode pad is not limited to this. Can be easily applied. As shown in FIG. 21, the electrode pad portion is formed in the same manner as in the first embodiment. Next, as shown in FIG. 22, the photoresist 44 used for patterning the surface protective film 41 is left after the surface protective film is removed. Then, as shown in FIG. 23, a metal to be the bump electrode 45 is deposited by about 15 μm by a plating method. At this time, the metal used for the bump electrode is A
u, Pd (Palladium), Sn
(Tin; Stannum). Antioxidant metal film 40
Since this becomes an electrode during plating, it is possible to omit processes such as base formation. After depositing the bump electrodes 45, the photoresist 44 can be removed to form the bump electrodes 45 as shown in FIG. From the above, even when the semiconductor device using the copper wiring is connected to the outside of the chip by the bump method, it can be performed without oxidizing the copper, and it is possible to prevent the reliability and performance from being reduced. .

【００５０】[0050]

【発明の効果】以上説明したように本発明の半導体装置
では、電極パッド部の銅系膜が酸化防止金属膜により被
覆されており、電極パッドの全体が、半導体基板上に形
成された絶縁膜の所定の位置に形成された凹部内に埋め
込まれていることや、電極パッドの下面が杭の働きをす
る銅系アンカー層に接続されていることにより、電極パ
ッドと絶縁膜との良好な密着性が実現されている。As described above, in the semiconductor device of the present invention, the copper-based film of the electrode pad portion is covered with the anti-oxidation metal film, and the entire electrode pad is the insulating film formed on the semiconductor substrate. Since it is embedded in the recess formed in the predetermined position of the electrode pad and the lower surface of the electrode pad is connected to the copper-based anchor layer that functions as a pile, good adhesion between the electrode pad and the insulating film is achieved. Is realized.

【００５１】また、本発明の製造方法によれば、前記の
電極パッド部分が絶縁膜に埋めこまれた構造や、電極パ
ッドの下面が杭の働きをする銅系アンカー層に接続され
ている構造を有する半導体装置を、簡便な工程により、
高い生産性で製造することができる。また、該電極パッ
ドを、銅系膜を開口用の化学薬品などに曝すことなく形
成することが可能なため、歩留まりは良好で、生産コス
トも安価である。According to the manufacturing method of the present invention, the structure in which the electrode pad portion is embedded in the insulating film, or the structure in which the lower surface of the electrode pad is connected to the copper-based anchor layer serving as a pile A semiconductor device having
It can be manufactured with high productivity. Further, since the electrode pad can be formed without exposing the copper-based film to a chemical agent for opening, the yield is good and the production cost is low.

【図面の簡単な説明】[Brief description of drawings]

【図１】本発明の半導体装置の一例を示す概略断面図で
ある。FIG. 1 is a schematic sectional view showing an example of a semiconductor device of the present invention.

【図２】本発明の実施例１を工程順に示す断面図であ
る。FIG. 2 is a cross-sectional view showing the first embodiment of the present invention in the order of steps.

【図３】本発明の実施例１を工程順に示す断面図であ
る。FIG. 3 is a cross-sectional view showing the first embodiment of the present invention in the order of steps.

【図４】本発明の実施例１を工程順に示す平面図であ
る。FIG. 4 is a plan view showing the first embodiment of the present invention in the order of steps.

【図５】本発明の実施例１を工程順に示す断面図であ
る。5A to 5C are cross-sectional views showing the first embodiment of the present invention in the order of steps.

【図６】本発明の実施例１を工程順に示す断面図であ
る。FIG. 6 is a cross-sectional view showing the first embodiment of the present invention in the order of steps.

【図７】本発明の実施例１を工程順に示す断面図であ
る。FIG. 7 is a cross-sectional view showing the first embodiment of the present invention in the order of steps.

【図８】本発明の実施例１を工程順に示す平面図であ
る。FIG. 8 is a plan view showing the first embodiment of the present invention in the order of steps.

【図９】本発明の実施例１を工程順に示す断面図であ
る。FIG. 9 is a cross-sectional view showing the first embodiment of the present invention in the order of steps.

【図１０】本発明の実施例１を工程順に示す断面図であ
る。FIG. 10 is a cross-sectional view showing the first embodiment of the present invention in the order of steps.

【図１１】本発明の実施例１を工程順に示す断面図であ
る。FIG. 11 is a cross-sectional view showing the first embodiment of the present invention in the order of steps.

【図１２】本発明の実施例１の半導体装置を示す断面図
である。FIG. 12 is a sectional view showing a semiconductor device according to a first embodiment of the present invention.

【図１３】本発明の実施例２を工程順に示す断面図であ
る。FIG. 13 is a cross-sectional view showing a second embodiment of the present invention in process order.

【図１４】本発明の実施例２を工程順に示す断面図であ
る。FIG. 14 is a cross-sectional view showing a second embodiment of the present invention in process order.

【図１５】本発明の実施例２の半導体装置を示す断面図
である。FIG. 15 is a sectional view showing a semiconductor device according to a second embodiment of the present invention.

【図１６】本発明の実施例３を工程順に示す断面図であ
る。FIG. 16 is a cross-sectional view showing a third embodiment of the present invention in the order of steps.

【図１７】本発明の実施例３を工程順に示す断面図であ
る。FIG. 17 is a cross-sectional view showing a third embodiment of the present invention in process order.

【図１８】本発明の実施例３を工程順に示す断面図であ
る。FIG. 18 is a cross-sectional view showing the third embodiment of the present invention in the order of steps.

【図１９】本発明の実施例３を工程順に示す断面図であ
る。FIG. 19 is a cross-sectional view showing the third embodiment of the present invention in the order of steps.

【図２０】本発明の実施例３の半導体装置を示す断面図
である。FIG. 20 is a sectional view showing a semiconductor device according to a third embodiment of the present invention.

【図２１】本発明の実施例４を工程順に示す断面図であ
る。FIG. 21 is a cross-sectional view showing a fourth embodiment of the present invention in process order.

【図２２】本発明の実施例４を工程順に示す断面図であ
る。FIG. 22 is a cross-sectional view showing the fourth embodiment of the present invention in the order of steps.

【図２３】本発明の実施例４を工程順に示す断面図であ
る。FIG. 23 is a cross-sectional view showing the fourth embodiment of the present invention in the order of steps.

【図２４】本発明の実施例４の半導体装置を示す断面図
である。FIG. 24 is a sectional view showing a semiconductor device according to a fourth embodiment of the present invention.

【図２５】通常用いられている銅製配線半導体装置の電
極パッドの公知例である。FIG. 25 is a known example of an electrode pad of a commonly used copper wiring semiconductor device.

【図２６】銅製配線半導体装置の電極パッドに多層構造
を持つ公知例である。FIG. 26 is a known example in which an electrode pad of a copper wiring semiconductor device has a multilayer structure.

【符号の説明】[Explanation of symbols]

１、１１、３１ 半導体基板 ２、１２、３２ 絶縁膜 ３ 保護膜（密着膜） ４、１６ 電極パッドを構成する銅膜 ５ パッシベーション膜 １３ 銅系アンカー層（上部） １５ 銅系アンカー層（下部） ２０ ボンディング用開口部 ３３ 銅系アンカー層形成用溝 ３４（ａ） 銅膜（銅系アンカー層） ３４（ｂ） 銅膜（電極パッドを構成する銅膜） ３５ 反射防止膜 ３６ ビア孔 ３７ 配線溝 １４、３８ 電極パッド形成用開口部 １７、３９ 拡散防止膜 １８、４０ 酸化防止金属膜 １９、４１ 表面保護膜 ６、２１、４２ ボンディングワイヤ ４３ 銅系アンカー層形成用開口部 ４４ フォトレジスト ４５ バンプ電極 1, 11, 31 Semiconductor substrate 2, 12, 32 insulating film 3 Protective film (adhesion film) 4, 16 Copper film forming electrode pad 5 Passivation film 13 Copper anchor layer (upper part) 15 Copper anchor layer (bottom) 20 Bonding openings 33 Copper-based anchor layer forming groove 34 (a) Copper film (copper-based anchor layer) 34 (b) Copper film (copper film forming electrode pad) 35 Antireflection film 36 Via hole 37 Wiring groove 14, 38 Opening for electrode pad formation 17,39 Diffusion prevention film 18,40 Antioxidant metal film 19, 41 Surface protection film 6, 21, 42 Bonding wire 43 Copper Anchor Layer Opening 44 photoresist 45 bump electrode

Claims (15)

(57)【特許請求の範囲】(57) [Claims] 【請求項１】 半導体基板上に形成された凹部を有する
絶縁膜と、該凹部に埋め込まれた電極パッドとを備える
半導体装置であって、 該電極パッドは、該凹部の内面を覆う銅系膜と、該銅系
膜を覆う酸化防止金属膜とを含んでなり、該電極パッドを構成する銅系膜の下面が、該絶縁膜中に
形成された銅系アンカー層にビアを介して接続されてお
り、 該銅系アンカー層は、該絶縁膜中に形成された銅系配線
と併用される ことを特徴とする半導体装置。1. A semiconductor device comprising: an insulating film having a recess formed on a semiconductor substrate; and an electrode pad embedded in the recess, the electrode pad covering a copper-based film covering an inner surface of the recess. And an anti-oxidation metal film covering the copper-based film, and the lower surface of the copper-based film forming the electrode pad is in the insulating film.
It is connected to the formed copper-based anchor layer through a via.
The copper-based anchor layer is a copper-based wiring formed in the insulating film.
A semiconductor device characterized by being used together with . 【請求項２】 前記銅系配線は多層配線構造であること
を特徴とする請求項１記載の半導体装置。 2. The copper-based wiring has a multilayer wiring structure.
The semiconductor device according to claim 1, wherein: 【請求項３】 前記銅系アンカー層は、他の銅系配線の
少なくとも何れかと同層に形成されることを特徴とする
請求項１又は２記載の半導体装置。 3. The copper-based anchor layer is used for another copper-based wiring.
Characterized by being formed in the same layer as at least one of them
The semiconductor device according to claim 1 or 2. 【請求項４】 前記銅系アンカー層と前記ビアとからな
る形状は杭状であることを特徴とする請求項１乃至３何
れかに記載の半導体装置。4. The copper-based anchor layer and the via
That shape semiconductor device according to any one of claims 1 to 3, characterized in that a pile-like. 【請求項５】 前記杭状形状の断面は、逆Ｔ字であるこ
とを特徴とする請求項４記載の半導体装置。 5. The pile-shaped cross section has an inverted T shape.
The semiconductor device according to claim 4, wherein 【請求項６】 前記杭状の形状は、前記銅系膜および前
記酸化防止金属膜を堆積する方向に向く軸に対して、該
軸に垂直な断面積を考えた場合、該軸上のある位置での
断面積が、該位置より表面より離れている位置での断面
積以下であることを特徴とする請求項４又は５記載の半
導体装置。 6. The pile-like shape is the copper-based film and the front.
The above-mentioned anti-oxidation metal film is
Considering the cross-sectional area perpendicular to the axis, at a certain position on the axis
Cross-section at a position where the cross-sectional area is farther from the surface than that position
The product according to claim 4 or 5, characterized in that it is less than or equal to the product.
Conductor device. 【請求項７】 前記絶縁膜と、前記銅系膜と、前記酸化
防止金属膜の一部とを覆うように形成された表面保護膜
を備えていることを特徴とする請求項１乃至６何れかに
記載の半導体装置。7. The surface protection film formed so as to cover the insulating film, the copper-based film, and a part of the antioxidant metal film. The semiconductor device according to 1. 【請求項８】 前記電極パッド上の、前記表面保護膜に
覆われていない部分に、バンプ電極が設けられているこ
とを特徴とする請求項７記載の半導体装置。8. The semiconductor device according to claim 7, wherein a bump electrode is provided on a portion of the electrode pad which is not covered with the surface protective film. 【請求項９】 前記銅系膜と前記酸化防止金属膜との間
に、拡散防止膜を具備することを特徴とする請求項１乃
至８何れかに記載の半導体装置。9. The semiconductor device according to claim 1, further comprising a diffusion preventive film between the copper-based film and the antioxidant metal film. 【請求項１０】 前記拡散防止膜はＴｉ、ＴｉＮ、Ｔｉ
Ｗ、ＴｉＷＮ、Ｗ、ＷＮ、ＮｂＮ、Ｃｒ、Ｔａ又はＴａ
Ｎからなることを特徴とする請求項９記載の半導体装
置。10. The diffusion barrier film is made of Ti, TiN, or Ti.
W, TiWN, W, WN, NbN, Cr, Ta or Ta
10. The semiconductor device according to claim 9, wherein the semiconductor device is made of N. 【請求項１１】 前記酸化防止金属膜はアルミニウム
（Ａｌ）、金（Ａｕ）、銀（Ａｇ）又はこれらを含む合
金からなることを特徴とする請求項１及至１０何れかに
記載の半導体装置。11. The semiconductor device according to claim 1, wherein the anti-oxidation metal film is made of aluminum (Al), gold (Au), silver (Ag) or an alloy containing them. 【請求項１２】 （ａ）半導体基板上に絶縁膜を成膜
し、該絶縁膜に凹部を形成する工程と、 （ｂ）該凹部を含む所定の領域に、銅系膜および酸化防
止金属膜をこの順で成膜する工程と、 （ｃ）該凹部以外の領域に形成された銅系膜および酸化
防止金属膜を除去し、電極パッドを形成する工程とを含
み、該工程（ａ）を行うに先立ち、該銅系膜の下面に接続す
る銅系アンカー層を形成する工程と、 該電極パッドを構成する銅系膜の下面と、該絶縁膜中に
形成された該銅系アンカー層とを接続するビアを形成す
る工程と を含むことを特徴とする半導体装置の製造方
法。12. A step of: (a) forming an insulating film on a semiconductor substrate and forming a recess in the insulating film; and (b) a copper-based film and an antioxidant metal film in a predetermined region including the recess. a step of forming in this order, the (c) removing the concave copper formed in a region other than the portion film and oxide barrier metal layer, and forming an electrode pad, said step (a) Before performing, connect to the lower surface of the copper-based film.
The step of forming a copper-based anchor layer, the lower surface of the copper-based film forming the electrode pad, and the insulating film.
A via is formed to connect with the formed copper-based anchor layer.
A method of manufacturing a semiconductor device, comprising: 【請求項１３】 前記工程（ｃ）の後、前記絶縁膜と、
前記銅系膜と、前記酸化防止金属膜の一部とを覆うよう
に表面保護膜を形成する工程を含むことを特徴とする請
求項１２記載の半導体装置の製造方法。13. The insulating film after the step (c),
13. The method of manufacturing a semiconductor device according to claim 12, further comprising the step of forming a surface protection film so as to cover the copper-based film and a part of the antioxidant metal film. 【請求項１４】 前記工程（ｂ）において、銅系膜と前
記酸化防止金属膜との間に拡散防止膜を形成することを
特徴とする請求項１２又は１３記載の半導体装置の製造
方法。14. The method for manufacturing a semiconductor device according to claim 12, wherein in the step (b), a diffusion barrier film is formed between the copper-based film and the antioxidant metal film. 【請求項１５】 前記銅系アンカー層を形成する工程に
おいて、前記絶縁膜中の銅系配線も同時に形成すること
を特徴とする請求項１２乃至１４何れかに記載の半導体
装置の製造方法。 15. A step of forming the copper-based anchor layer
At the same time, copper-based wiring in the insulating film should be formed at the same time.
15. The semiconductor according to claim 12, wherein
Device manufacturing method.
JP18657499A 1999-06-30 1999-06-30 Semiconductor device and manufacturing method thereof Expired - Fee Related JP3365495B2 (en)

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