JP3359518B2 - Rake synthesis circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a rake (RAKE) combining circuit having improved reception characteristics of a communication system using a spread spectrum communication technique based on a direct sequence code division multiple access (DS-CDMA) system.

[0002]

2. Description of the Related Art In a communication system such as a mobile communication, in order to enable a large number of system users to exist,
One technique is direct sequence code division multiple access (DS-CD
MA: Direct Sequence Code Multiple Access) method is used.

In the DS-CDMA system, a unique code (spreading code) is assigned to each of a plurality of terminals, and the signal is transmitted while being superimposed on a signal. On the receiving side, the spreading code is known from among a plurality of signals and addressed to itself. This is a method for extracting only signals. By superimposing the code on the transmission signal in this way, the frequency component of the signal spreads over the entire band, and is also called a spread spectrum communication system.

That is, on the transmitting side of the terminal, spreading processing of the assigned unique spreading code and signal, that is, modulus 2 addition (EX
-OR logic), a signal in which a band generated and spread is used as a transmission output, and transmission outputs from a plurality of terminals are transmitted on a common carrier. The receiving side performs a despreading process, that is, performs a modulo-2 addition (EX-OR logic) with the received signal as a despreading code using a unique spreading code assigned to each terminal. Can be received.

In mobile communication, fading, which is a random change in amplitude and phase, having a maximum frequency determined by the speed of a mobile object and the frequency of a carrier wave occurs. Very difficult to receive.

The above spread spectrum communication method is effective in reducing the deterioration due to the influence of such frequency selective fading. This is because such a spread spectrum technique spreads a narrow band signal to a high band and transmits the signal.Thus, even if the received electric field strength drops in a specific frequency band, information from other bands can be transmitted with few errors. It is expected that it can be restored.

Further, when a delayed wave from a distant high-rise building or a mountain causes fading similar to the above due to the environment around the receiver, a multipath fading environment is created. In the case of the DS-CDMA system, the delayed wave becomes a coherent wave with respect to the spreading code, so that the reception characteristic is deteriorated.

A rake receiving method is known as one of the methods for positively using the delayed wave for improving characteristics. In this method, despreading is performed for each delay arriving wave, the delay amounts are made uniform, and weighting is performed according to the reception level to perform addition and synthesis.

FIG. 10 shows an example of an assumed configuration of a radio using such a rake combining circuit. On the transmission side of the wireless device, a transmission signal is input to the encoder 1, and a process of superimposing the transmission signal on a unique spreading code for each channel is performed to perform spectrum spreading. Specifically, modulo 2 addition (EX-OR logic) between the transmission signal and the unique spreading code is performed to generate a spread signal.

The spread signal from the encoder 1 is input to a mapping circuit 2 and converts a serial signal into a parallel signal. Here, the signals are arranged in any of the four quadrants according to the logic of each two bits of the signal, and the I-axis and Q-axis signs are removed through the waveform shaping filters 3 and 4 to remove unnecessary bands. Then
The signals are input to the I-axis component digital / analog converter 5 and the Q-axis component digital / analog converter 6, and are converted into corresponding analog signals.

The converted I-axis analog signal and Q-axis analog signal from the I-axis component digital / analog converter 5 and the Q-axis component digital / analog converter 6 are quadrature-modulated in the quadrature modulation circuit 7.

Next, the quadrature modulation signal from the quadrature modulation circuit 7 is modulated into a radio frequency signal by the RF / IF conversion circuit 8, guided to the antenna 10 through the duplexer 9, and transmitted.

On the other hand, on the receiving side of the radio, the radio frequency reception signal is demodulated into an IF signal in an RF / IF conversion circuit 11 and then separated into an I-axis component and a Q-axis component in a quadrature detection circuit 12. The I-axis component and the Q-axis component are converted into digital signals in an I-axis component analog / digital converter 13 and a Q-axis component analog / digital converter 14, respectively.

The digital signals from the I-axis component analog / digital converter 13 and the Q-axis component analog / digital converter 14 are combined with a rake combining / demodulating unit 15 and a path search circuit 1.
6 is input.

The rake combining / demodulating unit 15 has one configuration example,
As shown in FIG. 11, this is a configuration example in the case of having three fingers realized by using one despreading circuit per finger. Here, the finger is a term indicating a system that demodulates a reception signal of one reception path, assuming each finger of a rake (bear hand).

On the other hand, there are a case where the receiving side independently estimates the delay wave position and a case where the delay wave position is controlled based on information notified from the transmitting side. In the former, a correlation detection function unit (not shown) of the path search unit 16 in FIG. 10 obtains a correlation value between the code to be predicted and the received signal, and estimates the number of fingers by estimating the position of the delayed wave from the one with the larger correlation value. Is done.

In the latter method, for example, the base station performs the above-described detection, and notifies the mobile station of the information through a control channel or the like.

FIG. 12 shows the rake combining / demodulating unit 15 shown in FIG.
6 is a time chart for explaining the operation of FIG. In FIG. 12, P1, P2, and P3 are three fingers corresponding to three fingers selected by the path search unit 16 from those having higher levels.
6 is a timing signal of a correlation value a estimated as one delayed wave position. Therefore, the timing signals P1, P2, P3 of these three correlation values and the time differences d1, d2, d3 between the timing signals are notified from the path search unit 16 to the rake combining / demodulating unit 15.

At this time, if the received signal is phase-modulated, the magnitude comparison of the correlation values is performed by individually obtaining the correlation values in quadrature phases and comparing the power or the sum of squares. Also, in order to improve the accuracy of the detection timing, a value that appears periodically is usually obtained by integration such as time averaging.

As shown in FIG. 11, the timing signals P 1, P 2, P 3 are input to respective despreading circuits 151, 152, 153 of the rake combining / demodulating unit 15. On the other hand, the time difference d1 between the timing signals of the estimated correlation value
, D2, d3 are despreading circuits 151,
Delay circuits 351 corresponding to each of 152, 153,
352, 353.

Therefore, the despreading circuits 151, 152, 15
In No. 3, a despreading code is generated at the timing signals P1, P2 and P3, respectively, and the received signal is despread for each of Ich and Qch.

If it is phase modulation, if it is phase modulation,
Demodulation circuit 25 decodes the despread I and Q symbol data.
Demodulated at 1, 252, 253. After that, of the corresponding delay amounts d1, d2, d3, the other two are shifted by a delay circuit in accordance with the slowest one, and the positions of the demodulated signals are aligned.

Further, this is weighted by an adder 150 for each reception level and added to obtain a composite signal CO. The comparator 17 determines the logic 0 or 1 based on the result, and becomes the received data.

[0024]

The rake receiver is constructed as described above. In mobile communication, one or both environments of transmission and reception change with time. For this reason, the path search unit 16 in the above configuration needs to infer from the amount of transition delay and reception level that the path is the same as the path received so far, and to follow its own cycle (for example, frame). There is.

In some cases, a new path with a different delay amount from the three paths that were initially determined may be more reliable. In this case, path switching is performed, but if one environment of transmission and reception changes with time, a part of the spreading period is missing, and if both environments of transmission and reception change with time, more is lost. It can happen.

As shown in FIG. 12, the path Pa is changed to the path Pb.
, Some symbols (see c in FIG. 12) are missing depending on the reception environment and the symbol period.

In estimating the path, a delay locked loop (DLL: Delay Locked Loop) is prepared for each path in order to accurately determine the same path from the frequency accuracy and fading speed of the system carrier and the clock, and the path is prepared. A problem that requires special control arises.

Accordingly, it is an object of the present invention to provide a communication system using spread spectrum communication technology that prevents loss of symbols due to such path switching and does not require additional functions and control circuits for each path. A rake combining circuit is provided.

[0029]

A first configuration of a rake combining circuit for achieving the above object of the present invention is to receive a plurality of delayed arriving waves, despread and demodulate each of the received signals, and provide a mutual delay amount. A rake combining circuit that adjusts and combines the signals, a path control unit that specifies a path to be despread according to the delay amount for each received signal and the reception level, and generates a despread code with a delay timing corresponding to the specified delay amount A despreader for despreading each received signal, the number of despreaders being equal to the number of paths selected and designated by the path control unit, at least one spare despreader, The number of despreaders corresponding to the number of paths specified by the path control unit has an adder that adjusts the delay amount specified by the path control unit to combine the signals despread corresponding to the received signals. Selected by the path control unit. When the path to be constant delay amount switches is changed, and switches the despreader for the pre, a despreader being received.

Furthermore, a second configuration of the rake combining circuit that achieves the object of the present invention is to receive a plurality of delayed arriving waves, despread demodulate each received signal, and adjust the mutual delay amount to combine the signals. In the rake combining circuit, a path control unit that specifies a path to be despread according to the delay amount for each received signal and the reception level, and generates a despread code at a delay timing corresponding to the specified delay amount. A despreader for despreading a signal, comprising a pair of despreaders corresponding to each path selected and designated by the path control unit, and a despreader corresponding to a path selected and designated by the path control unit. Has an adder that adjusts the delay amount specified by the path control unit to synthesize the despread signal, and alternately uses a pair of despreaders for each of the paths as a working and a protection. Features.

A third configuration of the rake combining circuit for achieving the object of the present invention is characterized in that, in the second configuration, the pair of despreaders are commonly used for a predetermined time.

Further, a fourth configuration of the rake combining circuit for achieving the object of the present invention is the rake combining circuit according to the third configuration, further comprising a buffer circuit for storing a despread received signal corresponding to each despreader. , And is configured to absorb overlapping reception signals corresponding to the commonly used time.

Further, a fifth configuration of the rake combining circuit that achieves the object of the present invention is the rake combining circuit according to the third configuration, further comprising a third despreader for each path selected and designated by the path control unit, The pair of despreaders are used as a spare while commonly used as a current.

Further, in a sixth configuration of the rake combining circuit that achieves the object of the present invention, in any one of the second to fifth configurations, the received signal includes a continuation of a frame including a preamble portion and a data portion. Extracting frequency information and timing information of a received signal from a preamble portion of one frame and a preamble portion of a subsequent frame,
It is characterized in that it is used for demodulating the data portion of the one frame.

According to a seventh aspect of the rake combining circuit for achieving the object of the present invention, in any one of the second to fifth aspects, the received signal comprises a sequence of frames including a preamble portion and a data portion. The frequency information and the timing information of the received signal are extracted from the preamble part of one frame and the data part of the previous frame.
For demodulating the data portion of the frame.

Further, an eighth configuration of the rake combining circuit that achieves the object of the present invention is the rake combining circuit according to any one of the second to fifth configurations, wherein the received signal is formed by a sequence of frames including a preamble portion and a data portion. That is, frequency information and timing information of a received signal are extracted from a preamble part of one frame and a preamble part of an earlier frame, and are used for demodulation of a data part of the one frame.

[0037]

Embodiments of the present invention will be described below with reference to the drawings. In the drawings, the same or similar components will be described with the same reference numerals or reference symbols.

FIG. 1 is a block diagram showing a first embodiment of a rake combining / demodulating unit 15 according to the present invention, which is implemented in the radio having the configuration described in FIG. 10, and FIG. 2 is an operation time chart thereof. It is.

In this embodiment, a three-finger demodulation system is provided, and one despreading circuit per finger and a total of four despreading circuits 151 to 154 using one spare despreading circuit are provided. Have.

Further, buffer circuits 451 to 454 corresponding to the despreading circuits 151 to 154, a selector 155 to which outputs of the buffer circuits 451 to 454 are input,
And a selector 156 to which delay amount signals d1 to d4 from the path search unit 16 are input.

Referring to FIG. 2, the operation of the embodiment of FIG. 1 will be described. First, as a result of performing path estimation by path search section 16 as described earlier with reference to FIG. The information of the four timing signals P1 to P4 and the respective delay adjustment amounts d1 to d4 are obtained.

The four timing signals P1 to P4 from the path search section 16 are input to the despreading circuits 151 to 154 such that they do not overlap. Each despreading circuit 1
In steps 51 to 154, despreading codes are generated based on their own timing signals P1 to P4, and the received data is despread.

The despread received data is input to the corresponding buffer circuits 451 to 454. Since it is a three-finger demodulation system, the buffer memories 451 to 45
From the four despread results inputted to the selector 4, three other than the standby system are selected by the selector 15 based on the select signal.
Select with 5.

The result of the despreading selected by the selector 155 is input to the corresponding demodulation circuits 251 to 253. Therefore, in the case of phase modulation, phase demodulation is performed from despread I and Q symbol data. Thereafter, the top three path estimations of the correlation value level follow their own paths.

Further, in FIG. 1, the second selector 15
In FIG. 6, similarly, three delay amount signals d1 to d3 corresponding to the despread result other than the standby system are obtained from the delay amount signals d1 to d4 input from the path search unit 16 by the selector signal.
Is selected. Then, the corresponding delay circuits 35
1 to 353 to provide a corresponding delay amount, and then add the adder 150 to output a composite signal CO.

Now, in FIG. 1, when the paths corresponding to the first to third timing signals P1 to P3 are active, the timing signal P4 selects a more probable path than the top three paths. are doing. Here, when the likelihood of the fourth correlation value becomes higher than any of the top three, one of the timings of the three correlation values that have been the top one becomes the same as the timing of the fourth correlation value. Replace it. Then, the same operation as the path of the fourth correlation value is performed, and the path is followed.

In the operation example of FIG. 2, the timing of the correlation value of path 4 is selected instead of the timing of the correlation value of path 2. Here, in the present invention, in order to solve the problem that information is lost at the moment of switching in the configuration of FIG.
The result of despreading is as described above, and the buffer memory 451-
It is stored in 454 and output. Buffer memory 451-
The capacity of 454 is determined by the delay difference allowed by the system, but is equivalent to several symbols since it is after despreading. The output from each of the demodulation circuits 251 to 254 is
At 1 to 353, the delay amounts are combined and added by the adder circuit 150 to be synthesized, and then data determination is performed.

According to the first embodiment of the present invention as described above, the problem of lack of information that occurs at the time of switching path selection as the first problem described above with reference to FIGS. 11 and 12 is solved. . In more general terms, the number of despreading circuits is larger than the number of fingers, and the number of despreading circuits is larger than the number of fingers, as compared with the frequency of occurrence of path selection switching estimated from the capability (such as carrier frequency and moving speed) required by the system. I have.

That is, since three fingers are used in the embodiment of FIG. 1, four or more despreading circuits are provided. For example, if four systems satisfy the requirements of the system, of the four despreading circuits, the first to third despreading circuits correspond to three fingers respectively, and the fourth is a spare.

Larger reception level (more likely)
Occurs, the fourth path corresponds to the fourth despreading circuit, and corresponds to the path having the minimum (uncertain) reception level among the three paths, for example, the third path.
Of the path despreading circuit of FIG.

Here, FIG. 3 showing a configuration example of the despreading circuits 151 to 154 in the embodiment of FIG. 1 which is common to the following embodiments will be described. Modulus 2 adder (EX-OR circuit) 3 corresponding to each of the Ich and Qch signals
1 and 32; adder circuits 33 and 34; chip-unit buffer flip-flops 35 and 36; and symbol-unit buffer flip-flops 37 and 38.

Here, the chip refers to one bit of the spread code, and the symbol refers to one bit of the transmission signal.

Further, a common code generator 30 is provided. The code generator 30 generates, as a despread code, the same code as the spread code obtained by modulo-2 addition with the transmission signal for spread spectrum at the transmission side. Therefore, the EX-OR circuits 31 and 32 determine the modulo-2 addition of the spread code generated from the code generator 30 and the Ich and Qch components of the received signal.

The outputs of the EX-OR circuits 31 and 32 are
Addition circuits 33 and 34 add the previous one-chip signal set in the chip-unit buffer flip-flops 35 and 36. Further, the data is buffered for one symbol by the symbol unit buffer flip-flops 37 and 38 and output.

Next, as a second problem, there is a lack of information which occurs at the time of path following, and the delay lock loop (DLL) is large in scale or difficult to intelligently control. Embodiments will be described below.

Here, the change in the delay amount due to the path following is as follows.
Since the frequency is determined by the accuracy of the system clock and the like, all fingers may change simultaneously. Therefore,
To cope with this, it is desirable to provide a spare despreading circuit in every finger.

Accordingly, FIG. 4 shows an example of a configuration in which a spare despreading circuit is provided for all such fingers. Assuming that there are three fingers as in the embodiment of FIG. 1, each finger is provided with two despreading circuits 1a and 1b and a selector 157 for selecting one of them. Each finger is alternately used as a working and standby system. FIG. 4 shows the configuration of only the first finger 1 for simplification of the drawing.

In other words, as a result of performing path estimation by the path search unit 16 in the same manner as in the previous embodiment, the three most probable timing information P1 to P3 are used as the current despreading circuits for the respective fingers 1 to 3. Notify 1a or 1b.

Each despreading circuit generates a despreading code based on its own timing information and despreads the received data. Next, as a result of performing a new path estimation in the path search unit 16, the timing information of the three paths with the highest probability is notified to the respective backup despreading circuits 1a or 1b.

In each of the despreading circuits 1a and 1b,
A despreading code is generated based on the own timing information, and the received data is despread. By alternately performing the above, it is possible to despread the latest and most probable path for which path estimation has been performed.

Therefore, the embodiment shown in FIG. 4 does not need to follow the path. The despread result is stored in the buffer memories 455 and 456 and output to the demodulation circuits 241 to 253 in order to prevent loss of information at the moment of switching. The capacity of the buffer memory is determined by the delay difference allowed by the system, but is equal to several symbols since it is after despreading. Subsequent operations are the same as in the previous embodiment.

FIG. 5 is an operation time chart corresponding to FIG. 4, showing only one finger. As is apparent from the above description, when the selection timing of the correlation value is changed within one finger, the control circuit 158 switches the supply destination of the timing signal from the working despreading circuit 1a or 1b to the spare despreading circuit 1b or 1a. I'm trying to switch.

That is, in the same manner as in the above-described embodiment, the corresponding finger system among the three finger timing signals P1 to P3 detected by the path search unit 16 is:
The corresponding timing signal P1 and delay amount signal d1 (for finger 1) are input.

FIG. 5 shows a time chart of the first finger 1, so that only the timing signal P1 is shown. In the figure, the timing signals P1a and P1b are the timing signals P1 respectively corresponding to the first and second despreading circuits 1 and 2.
These are timing signals when they are alternately input to a and 1b.

For example, every time the path estimation is completed,
The timing signal P1 is supplied to the first and second despreading circuits 1a, 1
If the timing signals P1a and P1b alternately input to b are switched, no omission occurs. As shown in FIG. 5, the switching timing of the timing signals P1a and P1b needs to be switched according to the data size necessary for information reproduction, and the despread signals obtained by the first and second despreading circuits 1a and 1b are used. a, b
Partially overlap, which can be absorbed in buffers 455, 456.

Therefore, by setting the operation of the path search unit 16 to a plurality of samples per chip, a delay lock loop (DLL) is not required, and a path which is likely to be reliable without intellectual control is always despread. Will be.

FIG. 6 is an operation time chart of the third embodiment of the present invention. The configuration of the rake combining / demodulating unit 15 is the same as that shown in FIG.

Accordingly, the three fingers are constituted by a total of six despreading circuits using two despreading circuits 1a and 1b per finger as active and standby.

The basic operation is the same as that of the embodiment shown in FIG. The embodiment according to the operation time chart of FIG. 6 relates to a case where a part of the operation of a part not used for actual demodulation as a spare is used.

For demodulation of received data, frequency information, clock timing information and the like are sometimes extracted from the preamble part, and the data part is reproduced. When the preamble portion is received on the same path, reproduction is performed on the assumption that the deviation information of the preamble portion is the same in the data portion. However, if the preamble portion length is short, sufficient accuracy cannot be obtained.

Therefore, in the embodiment shown in the operation time chart of FIG. 6, the next preamble from the despreading circuit, which is continuously switched from working to spare by switching, is treated as a postamble for the previous data, and the accuracy of deviation detection is improved. ing.

In FIG. 6, PR01 is a preamble signal of a despread signal from the despreading circuit 1a functioning as a working, and PR02 is a preamble signal of the next frame.

In the embodiment according to the operation time chart of FIG. 5, the next frame is switched to the despread signal from despreading circuit 1b and becomes a spare signal and is not used.

On the other hand, in the present invention, the preamble signal PR of the next frame which is switched as a spare is
02 is recognized and used as if it were a postamble portion of the previous frame. Therefore, even when the preamble signal PR01 itself is short, a double length can be obtained by using the postamble part PR02.

Therefore, even when the preamble signal PR01 is short, frequency information, clock timing information, and the like can be extracted, and the accuracy of deviation detection can be improved.

As described above, this embodiment can be realized by adjusting the timing of the despread timing signal and the delay amount adjustment signal from the path search unit 16, and there is a path switching from the time chart of FIG. Fig. 5
Is similar to the second embodiment shown in FIG. Further, when there is no switching, it can be understood that the case where the preamble signal of the next frame becomes short can be supplemented by using the postamble signal according to the present embodiment.

FIG. 7 shows a fourth embodiment of the present invention. In addition, three despreading circuits 1a, 1b, and 1c are used for one finger and two spares per one finger with three fingers.
FIG. 2 is a configuration block diagram of an embodiment including a total of nine despreading circuits. In addition to the configuration in FIG. 4, a third despreading circuit 1c per finger and a buffer memory 457 corresponding to the third despreading circuit 1c are further provided. In the present embodiment, this means an extension of the embodiment of FIG. That is, in the embodiment of FIG. 6, when sufficient characteristics cannot be obtained by using only the preamble PR01 and the postamble PR02, it is possible to cope by requiring data of the same path for a longer time.

That is, since the frequency information, clock timing information, and the like can be obtained from the data portion, the accuracy can be improved by referring to the preceding and following data and the preamble portion. Thus, desired characteristics can be obtained by increasing the number of despreading circuits as needed.

FIG. 8 is an operation time chart corresponding to the configuration example of FIG. 7, and shows a time chart for one finger similarly to FIG. FIG. 8 further shows a timing signal P1c for switching and inputting the timing signal P1 to the third despreading circuit 1c.

Further, in the figure, PR is a preamble portion of one frame, and DT is a data portion of the frame. Further, DT0 is a feature of the present embodiment, and the data portion of the destination frame referred to in order to increase the reliability of frequency information and clock timing information obtained from the preamble portion PR and the data portion DT of one frame. It is. Then, the data portion DT0 of the preceding frame is a portion that is not used for original data reception as a spare.

In the present embodiment, at least two spare despreading circuits are provided for each finger, and the data portion of the previous frame that is not used is referred to. In this case, each of the buffer memories 455, 456, and 457 for preventing information loss requires all of the data part to be referred to and a plurality of symbols of the part to be actually demodulated.

Next, FIG. 9 is an operation time chart of still another fifth embodiment of the present invention. In this embodiment, the configuration of the rake combining / demodulating unit 15 is the same as that of the previous embodiment shown in FIG. 7, and the three fingers and three despreading circuits 1a, 1b, and 1c per finger are used for the current working. This is realized by a total of nine despreading circuits used as two spares.

The basic operation is the same as that of the embodiment shown in FIG. In the above embodiment, the accuracy of frequency information, clock timing information, and the like is improved by using the data portion of the previous frame in the preliminary state and the preamble portion and the data portion of the working frame.

However, information may not be available in data portions that are random. Therefore, the despread timing output from the path search unit 16 and the rake combining / demodulating unit 1
The method of despreading only the preamble part before and after the preamble part can be realized by adjusting the capture timing in step 5. In the operation of the present embodiment, a reference is made to the briamble of the previous frame.

That is, in FIG. 9, taking the despread signal a as an example, PR and DT are the preamble part and the data part of the currently despread frame, respectively. Then, in the present embodiment, the preamble portion PR0 of the previous frame not used as a spare is referred to in order to increase the reliability of data.

Thus, the preamble part PR0 is
Despreading timing output from the path search unit 16;
By adjusting the capture timing in the rake combining / demodulating unit 15, the preamble portion PR and the data portion DT of the working frame are despread together.

For this purpose, the buffer memories 455, 456, and 457 for preventing information loss include preamble portions PR0 and PR to be referred to and a data portion DT to be actually demodulated.
A few symbols are sufficient.

[0088]

As described above with reference to the drawings, the present invention can prevent loss of information at the time of path selection switching. Since despreading is performed based on the latest and most probable path estimation result, rake combining can be realized without having a function of following or estimating an intelligent path.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of a rake combining / demodulating unit 15 according to the present invention, which is implemented in the wireless device described in FIG.

FIG. 2 is an operation time chart of the embodiment of FIG.

FIG. 3 shows the despreading circuits 151 to 151 in the embodiment of FIG.
154 is a block diagram illustrating a configuration example.

FIG. 4 is a block diagram showing a configuration example in a case where a spare despreading circuit is provided for all fingers.

5 is an operation time chart corresponding to the configuration example of FIG. 4, and is a diagram showing only one finger.

FIG. 6 is an operation time chart according to the third embodiment of the present invention.

FIG. 7 is a configuration block diagram of a fourth embodiment of the present invention.

FIG. 8 is an operation time chart according to the fourth embodiment of the present invention.

FIG. 9 is an operation time chart according to the fifth embodiment of the present invention.

FIG. 10 is a block diagram illustrating an example of an assumed configuration of a wireless device using a rake combining circuit.

11 is a block diagram showing an example of a configuration of a rake combining / demodulating section 15 of FIG.

FIG. 12 is a time chart for explaining the operation of the rake combining / demodulating unit 15 of FIG. 11;

[Explanation of symbols]

 Reference Signs List 1 spreading coding circuit 2 mapping circuit 3, 4 waveform shaping filter 5, 6 D / A conversion circuit 7 quadrature modulation circuit 8, 11 RF / IF conversion circuit 9 duplexer circuit 10 antenna 12 quadrature detection circuit 13, 14 A / D conversion Circuit 15 Rake combining / demodulating unit 16 Path search unit 17 Comparison circuit 151-154 Despreading circuit, 451-454 Buffer circuit 155, 156 Selector circuit 251-253 Demodulation circuit 351-353 Delay circuit 150 Addition circuit

Continued on the front page (72) Inventor Masahiko Shimizu 4-1-1, Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Prefecture Inside Fujitsu Limited (72) Inventor Shigeyuki Yoshioka 2-3-9 Shin-Yokohama, Kohoku-ku, Yokohama-shi, Kanagawa Fujitsu Digital Technology Co., Ltd. (56) References JP-A-8-56384 (JP, A) JP-A-7-131380 (JP, A) JP-A-7-231278 (JP, A) JP-A-10 −178672 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H04J 13/00-13/06 H04B 1/69-1/713

Claims (8)

(57) [Claims] A rake combining circuit for receiving a plurality of delayed arriving waves, despreading and demodulating each of the received signals, and adjusting and synthesizing each other's delay. A path control unit that specifies a path to be despread, and a despreader that generates a despread code at a delay timing corresponding to the specified delay amount and despreads each received signal. Despreaders for the number of paths designated and designated, at least one spare despreader, and despreaders for the number of paths designated by the path control unit correspond to the respective received signals. An adder for adjusting the delay amount designated by the path control unit and combining the signals despread by the path control unit, and when the path selected and designated by the path control unit is switched and the delay amount changes, A spare despreader, A rake combining circuit for switching between a despreader and a receiving despreader. 2. A rake combining circuit for receiving a plurality of delayed arriving waves, despreading and demodulating each of the received signals, and adjusting and synthesizing each other's delay. A path control unit that specifies a path to be despread, and a despreader that generates a despread code at a delay timing corresponding to the specified delay amount and despreads each received signal. A pair of despreaders corresponding to each path selected and designated, and a despread signal from the despreader corresponding to the path selected and designated by the path control unit, and a delay designated by the path control unit. A rake combining circuit comprising an adder for adjusting the amount and combining, and alternately using a pair of despreaders for each path as a working and a spare. 3. A rake combining circuit according to claim 2, wherein said pair of despreaders are commonly used for a predetermined time. 4. The apparatus according to claim 3, further comprising a buffer circuit corresponding to each despreader for storing the despread reception signal, and absorbing a duplicate reception signal corresponding to the commonly used time. A rake combining circuit characterized in that: 5. The apparatus according to claim 3, further comprising a third despreader for each path selected and designated by said path control unit, wherein said pair of despreaders are commonly used as active in use. A rake combining circuit characterized by being used for applications. 6. The reception signal according to claim 2, wherein the reception signal comprises a continuation of a frame including a preamble portion and a data portion, and includes a preamble portion of one frame and a preamble portion of a subsequent frame. Characterized in that the frequency information and the timing information are extracted and used for demodulating the data portion of the one frame. 7. The reception signal according to claim 2, wherein the reception signal is composed of a continuation of frames including a preamble portion and a data portion, and is received from a preamble portion of one frame and a data portion of an earlier frame. A rake combining circuit for extracting frequency information and timing information of a signal and using the extracted information for demodulation of a data portion of the one frame. 8. The reception signal according to claim 2, wherein the reception signal is composed of a continuation of a frame including a preamble portion and a data portion, and is received from a preamble portion of one frame and a preamble portion of a previous frame. Extract frequency information and timing information of the signal,
A rake combining circuit for demodulating the data portion of the frame.