JP3355100B2 - Display panel drive - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to relates to a driving device for a display panel having a non-linear element to the picture element, in particular, a display panel driven by dividing the selection period for determining a pixel display state into a plurality of periods The present invention relates to a driving device.

[0002]

2. Description of the Related Art In recent years, liquid crystal display devices have
(Audio Visual) equipment or OA (Office Aut)
omation) It is used in various fields such as equipment. Low-end products include, for example, STN (Super Twisted
Nematic), etc., are equipped with a passive type liquid crystal display device without a switching element for each picture element, but high-end products include an active matrix liquid crystal display with a switching element for each picture element. The device is mounted. The active matrix drive type liquid crystal display device is a CRT (Cathode-Ray-Tube) in terms of color reproducibility, thinness, light weight, and low power consumption.
) And its applications are currently expanding rapidly.

In the above liquid crystal display device, as a switching element, for example, a three-terminal element represented by a TFT (Thin-Film-Transistor) or an MIM (Metal-Insulator-M).
etal) is used. However, manufacturing a TFT requires 6 to 8 or more thin film deposition steps and a photolithographic step, which has the problem of increasing costs. In contrast, in the case of a liquid crystal display device using a two-terminal non-linear element such as an MIM as a switching element,
The number of thin film forming steps and photolithographic steps can be reduced to about half. As a result, a liquid crystal display device having an advantage in manufacturing cost as compared with a liquid crystal display device using a TFT and having an advantage in display quality as compared with a liquid crystal display device of a passive type can be realized. Therefore, among active-matrix-driven liquid crystal display devices, particularly, a liquid crystal display device using a two-terminal nonlinear element is expected to rapidly spread.

[0004] Specifically, a two-terminal nonlinear element has a characteristic that the equivalent resistance decreases as the applied voltage increases. Therefore, as shown in FIG. 15, as the applied voltage increases, the current flowing through the two-terminal nonlinear element rapidly increases. Note that the current-voltage characteristics are substantially symmetrical with respect to the origin, so that the description when a negative voltage is applied is omitted. Thus, the voltage applied to the pixel during the selection period is maintained even during the non-selection period. As a result, in an active matrix type liquid crystal display device using a two-terminal type non-linear element, high duty driving can be performed as compared with a simple matrix type liquid crystal display device.

Further, the active matrix type liquid crystal display device can be driven by a voltage averaging method in which a voltage shown in FIG. 16 is applied to picture elements, similarly to a simple matrix type liquid crystal display device. In the voltage averaging method, when lighting a picture element,
As shown by a solid line in the drawing, a high-level voltage is applied to the picture element during a period in which the picture element performs display (a selection period described later). On the other hand, when the light is turned off, a low-level voltage is applied during the selection period, as indicated by a broken line. Since the display state of the picture element can be controlled by the magnitude of the applied voltage in the selection period, high contrast and uniform display can be realized in the active matrix liquid crystal display device.

[0006] When a DC (direct current) component is accumulated in the liquid crystal element, the reliability decreases. Therefore, in order to avoid this, the polarity of the applied voltage is usually reversed every frame, or every plural frames or every plural lines.

Here, an entire conventional liquid crystal display device 201 including a picture element driving circuit will be described with reference to FIG. In the conventional liquid crystal display device 201, the display panel 203 includes data electrode lines X1 to Xn and scanning electrode lines Y1 to Ym that intersect with the data electrode lines X1 to Xn. And each scanning electrode line Yj
Are arranged between the pixel elements 202 having a liquid crystal element and a two-terminal non-linear element connected in series.

On the other hand, an external interface signal IN supplied from an external circuit (not shown) to the control unit 206 of the liquid crystal display device 201 usually changes the display state of each picture element 202 in a time-division manner in synchronization with the reference clock CLK. The data signal DATA to be transmitted is included. The external interface signal IN is a data signal D for one scan electrode line Yj.
A horizontal synchronization signal LP given for each ATA, a vertical synchronization signal FP given for each screen (frame),
For example, it includes an alternating signal M that is inverted at a predetermined cycle such as every one scan. In addition, 1 of the horizontal synchronization signal LP
The number of times the reference clock CLK is applied in the cycle varies depending on, for example, the number of data electrode lines Xi provided on the display panel 203, and thus differs for each liquid crystal display device 201.

The control unit 206 generates a control signal indicating the drive voltage and timing of each of the electrode lines Xi and Yj based on the external interface signal IN, and sends the control signal to the scan electrode drive circuit 204 and the data electrode drive circuit 205. I do. Based on these control signals, the scan electrode drive circuit 204 sequentially selects each scan electrode line Yj and applies a predetermined voltage. Further, the data electrode drive circuit 205 controls each data electrode line X1 in accordance with the display data of the picture elements 202.
To a predetermined voltage.

Here, the voltage applied to the picture element 202 provided at the intersection of a certain data electrode line X1 and a certain scanning electrode line Y1 will be briefly described with reference to FIGS. .

As shown in FIG. 18A, the horizontal synchronization signal LP is a data signal DAT for one scan electrode line Yj.
A is applied for each A. The period corresponding to the scanning electrode line Y1 between the horizontal synchronization signals LP is the picture element 20.
The selection period is 2.

During the non-selection period, scan electrode driving circuit 204
1 corresponds to the AC signal M shown in FIG.
As shown in 8 (c), the application of voltages V ₁ or V ₃ to the scan electrode lines Y1. On the other hand, as shown in FIG. 18D, the data electrode drive circuit 205 determines whether the currently selected scan electrode line Yj and the data electrode line X1
The voltage to be applied to the data electrode line X1 is selected depending on whether or not the picture element 202 connected to the data electrode line X1 is turned on.
For example, when the AC signal M is at a high level, the voltage V ₀
Alternatively, when V ₂ is selected and the level is low, the voltage V
₃ or V ₅ is selected. Thus, during the non-selection period, the voltage applied to the picture element 202 provided between the scan electrode line Y1 and the data electrode line X1 is changed from the ground level GND as shown in FIG. , Within the width of the voltage Vb.

On the other hand, during the selection period, the scanning electrode line Y1
The, as shown in (c) of FIG. 18, contrary to the alternating signal M, the voltage V ₅ or V ₀ is applied. As a result,
When the data signal DATA instructs lighting, FIG.
As shown in the (e), the voltage of -V ₀ or V ₀ is applied to the pixel 202, the picture element 202 is lighted. Similarly, if you are instructed off, the applied voltage of -V ₂ or V _2, pixel 202 unlit (unlit). Thereby, both driving circuits 204 and 205 can drive each picture element 202 by the voltage averaging method.

However, the liquid crystal display device 201 having the above configuration
In the case of (1), there is a problem that an afterimage (burn-in) easily occurs. Specifically, for example, the liquid crystal display device 20
In the case where 1 is a normally white mode (a mode in which black is displayed when the liquid crystal display element is turned on), the display panel 20
The display pattern of No. 3 is changed, and as shown in FIG. When the key (gray) is to be displayed, as shown in FIG. 19B, a display difference occurs between the central portion P1 displaying white and the peripheral portion P2 displaying black. That is, the entire screen of the display panel 203 is not uniform, and the previous display pattern remains.

This afterimage is caused by a shift of the voltage-dependent current-voltage characteristic in the two-terminal nonlinear element of the picture element 202. Specifically, as shown in FIG. 15, when the voltage is continuously applied to the two-terminal nonlinear element, the current-voltage characteristic shifts as shown by a broken line in the figure. The solid line indicates the initial current-voltage characteristics. Accordingly, in a liquid crystal element provided in the same picture element 202,
As shown in FIG. 20, the transmittance (T) -voltage (V) characteristic shifts from the characteristic shown by the solid line to the characteristic shown by the broken line. As a result, for example, the voltage at which the transmittance becomes 50% is:
It changes from V50 to V50 'by ΔV. Note that ΔV
Is V50'-V50. The shift amount ΔV changes according to the voltage application time as shown in FIG.
Further, the shift amount ΔV increases as the applied voltage increases. In addition, in the figure, the solid line shows the case where a voltage higher than the broken line is applied.

In the state where the pattern shown in FIG. 19A is displayed, the picture element 202 of the peripheral part P2 is added to the central part P1.
Is applied. Therefore, the shift amount ΔV is larger in the peripheral portion P2. As a result, when the entire screen is switched to the halftone state, the peripheral portion P2
19 is higher than that of the central portion P1, and an afterimage occurs as shown in FIG.

To reduce this afterimage, for example, as disclosed in Japanese Patent Application Laid-Open No. HEI 8-29748, one selection period is divided into a plurality of periods, and different levels of voltage are applied to each division period. Has been found to be effective.

[0018]

However, as described above, the external interface signal IN externally applied to the liquid crystal display device 201 includes a signal for dividing one selection period into a plurality of division periods. Not.
Therefore, it is necessary to change the external interface signal IN and apply a signal indicating each divided period to the liquid crystal display device 201, or the control unit 206 needs to newly generate a timing indicating each divided period.

For example, when changing the external interface signal IN, a signal different from the conventional one must be given to the liquid crystal display device 201. So, for example,
A circuit for transmitting display data of the liquid crystal display device 201,
External circuit needs to be changed. As a result, there is a problem that it takes time and money to replace a liquid crystal display device that does not divide the selection period with a liquid crystal display device that divides the selection period.

On the other hand, when generating based on the external interface signal IN similar to the conventional one, the control unit 206 needs to set the generation timing in accordance with the waveform of the external interface signal IN. However, as the specification of the liquid crystal display device 201 as a general-purpose product, the number of reference clocks in the selection period cannot be limited to one type. Each timing is generated by preparing the unit 206 or the like.

The fields in which the liquid crystal display device 201 is used include, for example, a portable computer and a POS (P
oint Of Sale) There are various fields such as terminals, and even if the liquid crystal display device 201 is the same, the waveform of the external interface signal IN that is different for each set specification that the user finally commercializes is input to the liquid crystal display device 201. Is done. In this case, the waveforms of the external interface signal IN differ from each other in the number of reference clocks CLK in one selection period, and the timings generated by the control unit 206 also differ. Therefore, an extremely large number of types of control units 206 must be prepared according to the type of the external interface signal IN waveform requested by the user. As a result, every time the required specifications of the user are different, it takes time and effort to design a new control unit 206, and the control unit
06 cannot be shared, and there is a major problem in the production management and inventory management of the control unit 206.

The present invention has been made in view of the above-mentioned problems, and an object of the present invention is to provide a display panel having the same external interface as the conventional one, but different in the number of reference clock signals within a selection period. Another object of the present invention is to provide a display panel driving circuit capable of dividing a selection period into a desired number.

[0023]

Means for Solving the Problems A table according to the invention of claim 1
In order to solve the above problem, the display panel driving device divides a selection period for setting a display state of a picture element having a non-linear element into a plurality of periods, and applies different voltages to each of the divided periods. In a display panel driving device for applying a voltage to the element, the following means are taken.

That is, based on a reference clock synchronized with the selection period and having a shorter cycle than the selection period and a signal indicating the selection period, a parameter calculation means for calculating parameters for dividing the subsequent selection period. And storage means for storing the parameter, based on the parameter, from a signal indicating the selection period and a reference clock,
Timing generating means for generating a timing signal for dividing a subsequent selection period into each division period.

[0025] In addition, the parameter calculating means, the above
A first counter for repeating the reference clock by a constant based on the division ratio of the division period; and a second counter for counting the number of repetition periods of the first counter. as a parameter, the first
The first counter at the end of counting by the two counters
And a storage area for storing the second count value of the second counter during the selection period, and the timing generation means stores the second count value in the selected period. A counter for equally dividing the reference clock repeatedly according to each selection period.
The reference clock is counted according to the first count value.
The timing signal is generated in accordance with the synchronization counter and the repetition cycle of the equal counter .
The synchronization counter sets the reference clock according to the first count value.
The timing signal is output only during the clock counting period
That it has an output unit for adjusting.

In the above configuration, the timing generation means
Before generating the timing signal, the parameter calculation means
Is the parameter for each display panel based on the reference clock.
Meter, and the timing generation means
A timing signal is generated based on the data. This allows
Drive device regardless of the number of reference clocks in one selection period
Can divide each selection period at a desired division ratio. But
Therefore, external inputs with different reference clock numbers within one selection period
Interface between different users using interface signals
Can be shared.

As a reference clock, for example,
An external display panel such as a signal synchronized with the panel video signal
The signal provided to the channel is available. Therefore, for example
For example, an external circuit such as a circuit that provides a video signal
Interface is set as before.
Generate a new signal to divide the selection period.
There is no need to As a result, the interface with the external circuit
Interface can be maintained as before, and the selection period
Drives that do not split or that have different split ratios
The circuit can be shared. In addition, PLL (Phase Locked)
Loop) circuit and other circuits that generate the signal are unnecessary.
Ri, it is possible to simplify the structure of the drive device for a display panel
Wear.

Further, when the division ratio is represented by an integer, the first counter repeatedly counts the reference clock by a constant based on the division ratio, such as the sum of the division ratios. The second counter counts the number of repetition periods of the first counter. Further, the storage means stores the count value of the second counter during the selection period as a second count value. Thus, when the selection period is equally divided into the above-mentioned constant, a value corresponding to the reference clock number for each equally divided period is stored in the predetermined storage area of the storage means. Hereinafter, the equally divided period is referred to as an equal period, and the constant is referred to as an equal constant.

On the other hand, in the timing generating means, the equal division counter is, for example, up to the second count value.
The reference clock is counted by the number based on the second count value. Thus, the repetition period of the equal division counter is
It will be an equal period. Further, the output unit outputs a timing signal by combining the equal division periods.

For example, when the division ratio is 2: 1: 1, the equalization constant is 4, and the equalization counter divides the selection period into four equal periods. Further, the output unit outputs a timing signal at the start of the first, third, and fourth equal periods. As a result, a timing signal having a desired division ratio is obtained.

Thus, regardless of the number of reference clocks in one selection period, the driving device can divide each selection period at a desired division ratio. Therefore, the driving device of the display panel can be shared between users having different reference clock numbers within one selection period without changing the external interface as in the related art.

[0032] Incidentally, when dividing between selected択期in a desired division ratio, the reference clock number can not be divided if an integer in the selection period, the second count value, an integer that indicates the number of reference clocks in equal periods Therefore, repeat the equal division counter
Equal multiple of the duration of the period of the selection period will not match.

However, in the above configuration, every selection period,
The synchronization counter counts the reference clock according to the first count value. Since this period coincides with the period of the error, the occurrence of the error can be prevented by adjusting the timing signal output point during the period.
As a result, even when the number of reference clocks in the selection period cannot be divided by an integer, the selection period and the timing signal can be reliably synchronized.

Further, the display panel according to the second aspect of the present invention is provided.
The drive unit is provided with an external interface to solve the above problems.
Each selection period is divided into a plurality of division periods based on the face signal.
And generate a timing signal indicating each divided period
A control unit provided with a timing generation circuit;
The timing generator generates a horizontal synchronization signal and a reference clock.
And a constant based on the split ratio of each of the above split periods
First count indicating the error when the above selection period is equally divided by
Value and number of reference clocks in equal time periods
Calculates an initial parameter consisting of a second count value indicating
Initial parameter calculation unit that holds both count values
Memory and the second count value held in the memory.
Generate a pulse signal for each equally divided period
Based on the pulse signal, the
Timing signal generation for generating a timing signal indicating the interval
And a first count value stored in the memory.
Delay or advance the generation of the timing signal,
Synchronizing section that synchronizes the selected period with the above timing signal
And is characterized by having.

Incidentally, the timing generation circuit is provided.
Control unit is, for example, another display panel having a different number of picture elements.
Connected to the reference clock within the selection period
The number varies. However, the initial parameter calculation unit
Calculate the first and second count values from the start of the selection period
Beginning to issue, at the end of the selection period, the first and
The second count value is stored. Furthermore, the equal period generation unit
Is the repetition of the output signal based on the second count value.
Since setting the period of the teeth, the timing generating circuit, any
The selection period can be divided at a predetermined division ratio without any trouble. Ma
Further, the synchronization unit is configured to control the first count value held in the memory.
Of the selection period and the timing signal based on
Take the time As a result, for example, display patterns with different numbers of picture elements are displayed.
The number of reference clocks within one selection period is different, such as between channels.
Between different users using external interface signals
The timing generation circuit can be shared.

[0036]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows an embodiment of the present invention.
This will be described below with reference to FIG.
That is, as shown in FIG. 2, the liquid crystal display device 1 according to the present embodiment includes the data electrode lines X1 to Xn and the scanning electrode lines Y1 arranged to intersect with the data electrode lines X1 to Xn.
, And a display panel (liquid crystal display element) 3 having picture elements 2... Provided in respective regions separated by the electrode lines X1 to Xn and Y1 to Ym. As shown in FIG. 3, each picture element 2 has, for example, an MIM (Metal-Insulator).
-Metal) and a liquid crystal element 2
b. The two elements 2a and 2b are connected in series with each other, the remaining electrodes of the two-terminal nonlinear element 2a are connected to the corresponding scanning electrode line Yj, and the remaining electrodes of the liquid crystal element 2b are connected to the corresponding data. Electrode wire Xi
It is connected to the.

The liquid crystal display device 1 has a display panel 3
A scanning electrode driving circuit 4 for driving the scanning electrode lines Y1 to Ym line-sequentially, a data electrode driving circuit 5 for applying a driving voltage to the data electrode lines X1 to Xn line-sequentially, and an external circuit (not shown). External interface signal IN
And a control unit 6 for controlling both of the drive circuits 4 and 5 based on the above. Each of the circuits 4, 5, and 6 corresponds to a driving device described in the claims.

As shown in FIG. 4, the external interface signal IN is the same signal as in the conventional liquid crystal display device. Specifically, the data signal DATA indicating the display state of each picture element 2 is transmitted to the picture element 2 connected to the same scan electrode line Yj.
.. Are transmitted in a predetermined order and in a time-division manner in synchronization with the reference clock CLK. When transmission for one scan electrode line Yj is completed, the next scan electrode line Yk
Is selected, and the data of the scanning electrode line Yk is transmitted. The external circuit can specify the display state of the entire display panel 3 to the liquid crystal display device 1 by transmitting the data of each scanning electrode line Yj in a predetermined order.

Each time the data signal DATA for one screen is transmitted, the vertical synchronizing signal FP is applied, and each time the data signal DATA for one scanning electrode line Yj is transmitted.
A horizontal synchronization signal LP is applied. Thereby, each data signal DATA and each picture element 2 are associated one-to-one. The data enable signal ENAB is applied except during a period when the data signal DATA is unstable, such as before and after a period during which the horizontal synchronization signal LP is applied. Therefore, the liquid crystal display device 1 can reliably acquire the data signal DATA. The above signals FP, LP, ENA
B and DATA are signals that change in synchronization with the reference clock CLK.

The scan electrode drive circuit 4 comprises, for example, a controller section, a shift register, an analog switch and the like, and a driver IC (integrated circuit) 4 for scan electrode signals for driving the scan electrode lines Y1 to Ym.
a, and a voltage switching circuit 4b for applying a drive voltage to the driver IC 4a. The voltage switching circuit 4b selects one of a plurality of levels of voltages applied from a power supply circuit (not shown) according to an instruction from the control unit 6, and supplies the selected voltage to the driver IC 4a. This allows
The scan electrode drive circuit 4 can apply a drive voltage according to the instruction of the control unit 6 to the selected scan electrode line Yj during the selection period.

On the other hand, the data electrode driving circuit 5 includes a driver IC 5a for data electrode signals for driving each of the data electrode lines X1 to Xn, and a voltage switching circuit for applying a driving voltage to the driver IC 5a as in the voltage switching circuit 4b. And a circuit 5b. The driver IC 5a includes, for example, a controller, a shift register, a latch, and an analog switch.
j data signals DATA can be held. Further, during the selection period corresponding to the scan electrode line Yj, a drive voltage can be applied to each of the data electrode lines X1 to Xn based on the held data signal DATA.

Further, the control section 6 divides each selection period at a desired division ratio based on the external interface signal IN and generates a timing signal for generating a signal indicating a plurality of division periods T1 such as two or three. A circuit 10 is provided. The configuration and operation of the timing generation circuit 10 will be described later in detail.

During each selection period, the selected scanning electrode line Yj
Are applied with a voltage that is the difference between the drive voltage of the data electrode line Xi and the drive voltage of the scan electrode line Yj. In the picture element 2, the equivalent resistance of the two-terminal nonlinear element 2a shown in FIG. 3 decreases as the applied voltage increases. Therefore, as the applied voltage increases, the current flowing through the two-terminal nonlinear element 2a sharply increases. And the current decreases as the applied voltage decreases. As a result, the voltage applied to the picture element 2 during the selection period is maintained even during the non-selection period.
In each picture element 2, the transmittance of the liquid crystal element 2b is determined according to the voltage between both ends, so that the transmittance of the picture element 2 is kept constant during the selection period.

The voltage switching circuits 4b and 5b of the driving circuits 4 and 5 apply different voltages for each of the divided periods T1 to each driver IC in accordance with the instruction of the timing generation circuit 10.
4a and 5a. The number and division ratio of each of the divided periods T1 and the level of the drive voltage given for each of the divided periods T1 are the current-voltage generated when the voltage is continuously applied to the two-terminal nonlinear element 2a. The value is set to a value that cancels the shift of the characteristic. In the present embodiment, for example, the division ratio is set to 2: 1: 1, and the three divided periods are referred to as T1, T2, and T3, respectively. As a result, a high-quality display can be obtained by canceling the afterimage caused by the shift.

By repeating the same operation for each scanning electrode line Yj, the display state of all the picture elements 2 provided in a matrix on the display panel 3 is determined.
The drive circuits 4 and 5 determine the polarity of the drive voltage for each frame, or for each of a plurality of frames or a plurality of lines. With this AC conversion, it is possible to prevent a decrease in the reliability of the liquid crystal element 2b due to accumulation of a DC (direct current) component.

The timing generation circuit 10 according to the present embodiment
Is configured such that the selection period can be divided at a desired division ratio regardless of the number of reference clocks CLK applied during the selection period. Hereinafter, the configuration and operation of the timing generation circuit 10 will be described in detail.

The timing generation circuit 10 according to the present embodiment
Generates a timing indicating each divided period based on the equally divided period based on the reference clock CLK and a predetermined number obtained from the division ratio. In the following, the predetermined number is referred to as an equal division constant, and the equally divided period is referred to as an equal period. When the division ratio is expressed as an integer, the equalization constant can be calculated by the sum of the division ratios, and is set to 2 if the division ratio is 1: 1. Also, if the division ratio is 2: 1, it is set to 3, and if it is 1: 1: 1, it is set to 3. In the case of the present embodiment, as described above, since the division ratio is set to 2: 1: 1, the equal division constant of each selection period is 4, and the selection period is divided into four equal periods. .

Specifically, as shown in FIG. 1, the timing generation circuit 10 counts a count value C1 indicating an error at the time of equal division based on the horizontal synchronization signal LP and the reference clock CLK, and the like. Reference clock CL in minute period
Initial parameter calculating unit (parameter calculating means) for calculating an initial parameter including a count value C2 indicating the number of K
11 and both count values C1 and C2 are
A memory (storage means) 12 for holding as M2;
3, an equal-period generation unit 14 that generates a pulse signal SIG4 for each equal period based on the count value M2, and each divided period T1 · T based on the pulse signal SIG4.
And a timing signal generator 15 for generating timing signals P1, P2, and P3 indicating 2.T3. Thereby, the timing generation circuit 10 can divide the selection period at a desired division ratio regardless of the number of reference clocks CLK applied in the selection period. Note that the synchronization unit 13, the equal period generation unit 14, and the timing signal generation unit 15 correspond to the timing generation unit described in the claims, and the timing signal generation unit 15 further corresponds to the output unit. I have.

The initial parameter calculating section 11 sorts the horizontal synchronization signal LP alternately to generate signals DLP1 and DLP2 indicating the start and end of the selection period, and an initializer for each timing of the start signal DLP1. A first counter 22 that repeatedly counts the number of reference clocks CLK to an equal constant, and a horizontal synchronization signal L
A second counter 23, which is initialized for each P and counts up one by one each time the first counter 22 overflows and outputs the carry signal SIG1. As a result, at the time of the end signal DLP2, the count value C1 of the first counter 22 is obtained by dividing the total number of reference clocks CLK in the period from the start signal DLP1 to the end signal DLP2, that is, in the selection period, by an equal constant. It corresponds to the remainder of time. Similarly, the count value C of the second counter 23
2 corresponds to a quotient.

For example, as shown in FIG. 5, the classifier 21 includes a D-type flip-flop circuit (hereinafter, a D-FF).
Circuit 41). The D-FF circuit 4
A signal obtained by inverting the horizontal synchronization signal LP is applied to one clock terminal CK via an inverter 42.
The output Q of the D-FF circuit 41 is inverted and applied to the input terminal D via the inverter 43. In addition, D-FF
In the circuit 41, the power supply voltage Vcc is applied to the negative logic preset terminal PRN and the clear terminal CR so that the preset and clear are not performed (neither is shown). Further, the output Q of the D-FF circuit 41,
The inversion signal of the output Q generated by the inverter 44 is ANDed with the horizontal synchronization signal LP by the AND circuits 45a and 45b, and output as start and end signals DLP1 and DLP. Accordingly, the classifier 21 alternately distributes the horizontal synchronization signal LP, and outputs the start and end signals DLP1 and DLP2.
Can be generated.

The first counter 22 is a quaternary counter that repeatedly counts the reference clock CLK up to an equal division constant. For example, as shown in FIG.
Terminals Qa and Qb for outputting lower and upper bits of
A terminal Qc for outputting a carry signal SIG1 indicating that the first counter 22 has overflowed.
Further, the first counter 22 is provided with three D-FF circuits 51a to 51c each having the output Q connected to each of the terminals Qa to Qc. An inverter 52 for inverting the reference clock CLK is connected to a clock terminal CK of each of the D-FF circuits 51a to 51c. Further, the D-FF circuit 51
The start signal DLP1 from the classifier 21 shown in FIG. 1 is applied to the input terminal D of “a” via the OR circuit 53.
The other input of the OR circuit 53 is connected to an AND circuit 54a.
Through the inverter 5 for inverting the start signal DLP1
5 is connected. The other input of the AND circuit 54a is connected to the output Q of the D-FF circuit 51a via an inverter 56. Also, the input D of the D-FF circuit 51b
Is connected to the inverter 55 via an AND circuit 54b.
Is connected. The other input of the AND circuit 54b is connected to an XOR circuit 57 that performs an exclusive OR operation on the outputs of the D-FF circuits 51a and 51b. Further, DF
The input D of the F circuit 51c is connected to a BAND circuit 58 that performs a logical AND between the inputs D of the D-FF circuits 51a and 51b as a negative logic input and a positive logic output.

When the start signal DLP1 is at "H" level,
The output of the OR circuit 53 becomes "H" level, and the outputs of the AND circuits 54a and 54b become "L" level. Therefore, an “H” level is input to the lower D-FF circuit 51a, and an “L” level is input to the upper D-FF circuit 51b. Therefore, at the fall of the reference clock CLK, the outputs of the D-FF circuits 51a and 51b become "H" level and "L" level, respectively, and the count value C1 of the first counter 22 becomes "1". Become. Since the first counter 22 according to the present embodiment is a quaternary counter, Qa is at “H” level and Qb is
Is set to the "L" level. However, even if the counter is a decimal number, at the time of initialization, the output terminal corresponding to the least significant bit of the count value C1 is set to the "H" level, and the terminal corresponding to the remaining bits. Is set to “L”, the count value C1
Can be initialized to “1”, so that the same effect as in the present embodiment can be obtained.

On the other hand, the start signal DLP1 is "L".
In the case of the level, the inputs of both D-FF circuits 51a and 51b are connected to the inverter 55 or the XOR circuit 57, respectively.
Output. Therefore, the first counter 22
Counts up the count value C1 by 1 at the fall of the reference clock CLK. The input D of the D-FF circuit 51c is connected to both the D-FF circuits 51a and 51b.
Becomes "H" level only when the input D is at "L" level. Thus, the D-FF circuit 51c counts the count value C
Only when “1” is “0”, the “H” level carry signal SIG1 is output from the terminal Qc.

On the other hand, the second counter 23 shown in FIG.
It is a binary counter of bits. Here, the second counter 2
The bit width of 3 is set to a value that does not overflow during one selection period. For example, if the first counter 22 is 4
When the maximum value of the reference clock CLK applied within one selection period is 901 in the binary counter, 90 カ ウ ン タ = 225,
Since the remainder is 1, the second counter 23 at least
It is necessary to count numbers up to 225. Therefore, the bit width required for the second counter 23 is 8 bits or more. In this case, since the second counter 23 can count up to 255, even if 1023 (255 × 4 + 3) reference clocks CLK are applied during one selection period, the second counter 23 does not overflow. .

For example, as shown in FIG. 7, the second counter 23 counts the count value C2 in order from the least significant bit.
And D-FF circuits 61a to 61h corresponding to the respective bits. The carry signal SIG1 from the first counter 22 shown in FIG. 1 is input to the clock terminal CK of each of the D-FF circuits 61a to 61h, and the negative logic preset terminal PR
N is an inverter 62 for inverting the horizontal synchronization signal LP.
It is connected to the. In the following, the D-FF circuit 61
When the members are not distinguished from each other as in a case where a to 61h are collectively referred to, the reference is made by omitting lowercase letters, such as a D-FF circuit 61, for example. The power supply voltage V is applied to a negative logic clear terminal CR (not shown) of each D-FF circuit 61.
cc is applied.

The input D of the lowest D-FF circuit 61a is connected to an inverter 63, to which a signal obtained by inverting the output Q of the D-FF circuit 61a is applied. Also,
The input D of the next-stage D-FF circuit 61b is the D-FF of the previous stage.
It is connected to an XOR circuit 64b that performs an exclusive OR operation on the output Q of the circuit 61a and its own output Q. Further, in the third stage, the AND circuit 65c is connected to both the D-FF circuits 61a.
The logical product of the outputs Q and Q of 61b is output, and the XOR circuit 6
4c is the output of the AND circuit 65c and the D-FF
The exclusive OR of the output Q of the circuit 61c and the D-FF circuit 6
Apply to input D of 1c. In the fourth and subsequent stages, the output of the preceding AND circuit 64 and the D
-The output Q of the FF circuit 61 is ANDed. In addition, an XOR circuit 64 is connected to the input D of the D-FF circuit 61 of the stage.
As a result, the output of the AND circuit 65 and the D-F
An exclusive OR with the output Q of the F circuit 61 is applied.

Thus, while the horizontal synchronization signal LP is at "H", the second counter 23 outputs "2" as the count value C2 regardless of the carry signal SIG1 of the first counter 22.
FFh ”and the carry signal S during the“ L ”level.
At the rise of IG1, the count value is counted up. Hereinafter, when the count value is described, the symbol “h” added at the end indicates that the count value is 16 or less.
Indicates that the value is expressed in hexadecimal.

On the other hand, as shown in FIG.
At the timing of the signal DLP2 generated by the classifier 21, 1
This is a latch type memory that stores 0-bit width data. In the memory 12, a 2-bit input terminal D
0.D1 is connected to the output terminals Qa and Qb of the first counter 22, and the remaining input terminals D2 to D9 are connected to the output terminals Qa to Qh of the second counter 23. The memory 12 includes, for example, D-FF circuits (storage areas) 71... Corresponding to each bit as shown in FIG. The input D of each D-FF circuit 71 is connected to the corresponding one of the input terminals D0 to D9,
The output Q is connected to corresponding output terminals Q0 to Q9. The clock signal CK of each D-FF circuit 71 is supplied to the signal D every two selection periods from the classifier 21 shown in FIG.
LP2 is input. As a result, the count values of both counters 22 and 23 are held and output from output terminals Q0 to Q9 until signal DLP2 is applied next.

As shown in FIG. 1, the synchronization unit 13
A third counter (synchronization counter) that reads the count value of the first counter 22 from the memory 12 at the rise of the horizontal synchronization signal LP and counts down until the count value becomes “0” at the rise of the clock terminal CK. And an inverter 25 for inverting and applying the reference clock CLK to the clock terminal CK of the third counter 24
An OR circuit 26 that performs an OR operation on the count values Qa and Qb output from the third counter 24;
A D-FF circuit 27 for D-latching the output of the OR circuit 26 at the rise of LK.

The third counter 24 is a 2-bit down counter. For example, as shown in FIG. 9, a D-FF circuit 81a which outputs the lower bit Qa of the count value
And a D-FF circuit 81b that outputs the upper bit Qb. The reference clock CLK is applied to the clock terminals CK and CK of the D-FF circuits 81a and 81b via the inverter 25. Also, the third counter 2
Reference numeral 4 denotes a 3-input AND circuit 83a in which an inverter 82 for inverting the horizontal synchronization signal LP is connected to one of the inputs corresponding to the D-FF circuit 81a, and a horizontal synchronization signal LP having one input. Second, a two-input A
An ND circuit 84a and an OR circuit 85 for applying the logical sum of the outputs of the AND circuits 83a and 84a to the D-FF circuit 81a
a. The remaining input of the AND circuit 83a is connected to an inverter 86 for inverting the output Q of the D-FF circuit 81a and the output Q of the D-FF circuit 81b. The other input of the AND circuit 84a is connected to the input terminal A.

Similarly, the third counter 24 has D-
AND circuits 83b and 84b and an OR circuit 85b corresponding to the FF circuit 81b are provided. However, DF
Unlike the case of the F circuit 81a, the outputs of the D-FF circuits 81a and 81b are input to the input of the AND circuit 83b.
The input terminal B is connected to the input of the AND circuit 84b. Both AND circuits 83b and 84b
The other inputs are connected to the horizontal synchronization signal LP and the like, similarly to the AND circuits 83a and 84a.

When the horizontal synchronization signal LP is at "H" level, the outputs of the three-input AND circuits 83a and 83b are always at "L" level. On the other hand, a two-input AND circuit 84
The output of a · 84b becomes the level of the input terminals A and B.
Therefore, the third counter 24 supplies the reference clock CLK
1 reads the count value applied to both inputs A and B.

On the other hand, when the horizontal synchronization signal LP is "
In the case of L level, two-input AND circuits 84a and 84b
Is always at "L" level. Therefore, the third
The counter 24 counts down the current count value one by one at the fall of the reference clock CLK.
Further, when the count value becomes “0”, a three-input AND
Since the outputs of the circuits 83a and 83b are always at "L" level, the third counter 24 outputs the count value "0" again at the fall of the reference clock CLK.

Further, as shown in FIG.
Outputs a signal of “H” level while the count value of the third counter 24 is not “0”, and outputs the signal of the D-FF circuit 27.
Latches the signal at the rising edge of the reference clock CLK. Thus, the delay circuit 13 can output the signal SIG2 which becomes “H” level while counting the reference clock CLK by the count value of the first counter 22.

On the other hand, based on the read signal SIG3 output from the NOR circuit 28, the equal period generation unit 14 reads the count value M2 from the memory 12 and counts down at the falling edge of the reference clock CLK.
When the count value reaches “0”, a fourth counter (equivalent counter) 2 that outputs an “H” level signal Q0
9, an inverter 30 that inverts and applies the reference clock CLK to the clock terminal of the fourth counter 29, and a signal that D-latches the output signal Q0 at the rise of the reference clock CLK to indicate the end of the equal period. And a D-FF circuit 31 that outputs SIG4.

The NOR circuit 28 performs a logical negation on the output signal SIG2 of the synchronization section 13, the horizontal synchronization signal LP, and the output signal SIG4. Therefore, the NOR circuit 28 operates while the horizontal synchronization signal LP is applied, while the output signal SIG2 of the synchronization unit 13 instructs the stop of the equal period generation unit 14, or Is the signal SIG4 indicating the end of the equal period
In any period during which is output, the "L" level signal SIG3 can be applied to the fourth counter 29 to instruct the reading of the count value M2.

The fourth counter 29 is provided, for example, as shown in FIG.
As shown by 0, D-FF circuits 91a to 91h are provided in order from the lowest order, corresponding to each bit of the count value. The clock terminals CK of these D-FF circuits 91.
, A reference clock CLK inverted by the inverter 30 is applied. The D-FF circuit 91 has a negative logic preset terminal PRN and a clear terminal CL.
The power supply voltage Vcc is applied to RN (not shown).

The fourth counter 29 stores the lowest D value.
A negative logic read signal L corresponding to the FF circuit 91a;
AND circuit 9 in which DN is directly applied to one of the inputs
2a and an AND circuit 9 to which the read signal SIG3 inverted by the inverter 93 is applied to one of the inputs
4a and the OR of the outputs of the AND circuits 92a and 94a are calculated and applied to the input D of the D-FF circuit 91a.
A circuit 95a is provided. Similarly, corresponding to the D-FF circuits 91b to 91h at the next stage and thereafter, both AND circuits 92b to 92h, 94b to 94h, and O
R circuits 95b to 95h are provided. The other inputs of the AND circuits 94... Connected to the inverter 93 are connected to input terminals A to H for reading the count values from the memory 12 shown in FIG.

On the other hand, the other input of the lowest-order AND circuit 92a is connected to an inverter 96 for inverting the main power Q of the D-FF circuit 91a. Further, D-FF circuits 91a and 91a are connected to the other inputs of the second-stage AND circuit 92b.
An XNOR circuit 97b that performs a NOT operation of exclusive OR is connected to the output Q · Q of b. In addition, in the third stage, the OR circuit 98c is connected to both the D-FF circuits 9
The XOR circuit 97c ORs the outputs Q and Q of the stages 1a and 92b and the output of the OR circuit 98c and the D-
The output Q of the FF circuit 91c is connected. In the subsequent stages, the OR circuit 98 and the D-FF circuit 91 of the preceding stage are input to the OR circuit 98 of the stage, and the input of the XNOR circuit 97 is connected to the OR circuit 98 and the D-FF circuit 91 of the stage.
Is connected.

Further, the fourth counter 29 has an 8-input B
An AND circuit 99 is provided. The BAND circuit 98
Has negative logic inputs connected to the outputs Q of the D-FF circuits 91a to 91h, respectively, and outputs a logical product of positive logic.

The NOR circuit 28 shown in FIG. 1 outputs the "L" level read signal SIG3 to the negative logic read terminal L.
When the voltage is applied to the DN, the fourth counter 29 reads the count value from the memory 12 shown in FIG. 1 to each of the D-FF circuits 91a to 91h at the fall of the reference clock CLK. On the other hand, the read signal SI
When G3 is at “H” level, the fourth counter 29 counts down the count value one by one at the falling edge of the reference clock CLK. When the count value becomes “0”, all the inputs of the BAND circuit 98 become “L” level. Therefore, the fourth counter 29 outputs the "H" level signal Q0 only when the count value is "0".

As shown in FIG. 1, the D-FF circuit 31
At the rising edge of the reference clock CLK, the signal QO is D-latched, and a signal SIG4 indicating the end of each equal period is generated. Further, the signal SIG4 is output as a read signal SIG3 via the NOR circuit 28 to the fourth counter 2.
9 When the read signal SIG3 is input, the fourth counter 29 reads the count value M2 from the memory 12, and starts counting down again. The NOR circuit 28 has an output signal S
Since IG2 and the horizontal synchronization signal LP are also applied, the fourth counter 29 does not start counting down while both signals SIG2 and LP are applied. As a result, the equal period generation unit 14 outputs the signal SI for each equal period.
G4 can be generated.

Further, the timing signal generator 15 includes a fifth counter 32 for counting the number of pulses of the signal SIG4, and the signal SIG for one reference clock CLK.
And a delayed signal S
An output unit 34 that generates timing signals P1, P2, and P3 indicating the respective divided periods T1, T2, and T3 based on the IG5 and the count value of the fifth counter 27.

The fifth counter 32 has a value of 2 which can be cleared to 0.
This is a binary counter having a bit width, and for example, as shown in FIG. 11, includes D-FF circuits 101a and 101b corresponding to the lower bit Qa and the upper bit Qb of the count value. In both D-FF circuits 101a and 101b, the signal SIG4 is applied to the clock terminal CK from the equal period generation unit 14 shown in FIG. The negative logic clear terminal CLRN is connected to an inverter 102 that inverts the horizontal synchronization signal LP. The power supply voltage Vcc is applied to the negative logic preset terminal PRN (not shown). The input D of the D-FF circuit 101a is connected to an inverter 103 that inverts the output Q of the D-FF circuit 101a. On the other hand, the input D of the D-FF circuit 101b is input to both D-FF circuits 101a and 101a.
XOR circuit 1 for calculating exclusive OR of outputs Q and Q of b
04 is connected. Thereby, the fifth counter 32
When the horizontal synchronization signal LP is at "H" level, the count value C5 is forcibly set to "0", and when the horizontal synchronization signal LP is at "L" level, the count value C5 is set to 1 at the rising edge of the signal SIG4. You can count up by one. Therefore, the count value C5 of the fifth counter 32 indicates the number of the current equal period in the selection period.

On the other hand, as shown in FIG.
Reference numeral 3 D-latches the signal SIG4 at the rise of the reference clock CLK to generate a signal SIG5. As a result, the signal SIG5 is delayed by one reference clock CLK as compared with the signal SIG4. In addition,
In the D-FF circuit 33, a negative logic preset terminal P
The power supply voltage Vcc is applied to the RN and the clear terminal CRN (not shown).

The output section 34 outputs the timing signal P
A 3-input AND circuit 35a that outputs 1 · P2 · P3
35b and 35c are provided. Each AND circuit 35a-3
The signal SIG5 is applied to one of the inputs of 5c. On the other hand, the lower bit Qa of the count value of the fifth counter 32 is input to the other via the inverter 36a or as it is. One of the remaining
Similarly, the bit Qb of the count value is applied via the inverter 36b or as it is.

Whether the inverters 36a and 36b are connected to the inputs of the AND circuits 35a to 35c is set according to the division ratio of the division periods T1, T2 and T3.
In the present embodiment, since the division ratio is set to 2: 1: 1, the invar 36a is connected to the AND circuits 35a and 35a.
5b is connected to the inverter 36b and the AND circuit 3
5a is connected. Note that the count values Qa and Qb of the fifth counter 32 are applied as they are to other inputs.

The operation of each part of the timing generation circuit 10 having the above configuration will be described below with reference to the timing charts shown in FIGS. Note that the timing generation circuit 10 according to the present embodiment can divide the selection period at a desired division ratio regardless of the number of reference clocks CLK applied in one selection period. A case where 17 reference clocks CLK are applied in each cycle of the direction synchronization signal LP will be described.

Further, during each horizontal synchronization signal LP, any one of the scanning electrode lines Y1 to Ym is selected.
The timing generation circuit 10 divides the selection period,
The timing signals P1, P2, and P3 are generated. Therefore, hereinafter, a period from one horizontal synchronization signal LP to the next horizontal synchronization signal LP is simply referred to as a selection period without distinction of which of the scanning electrode lines Y1 to Ym is selected.

As shown in FIG. 12, in the initial parameter calculator 11, the classifier 21 outputs the horizontal synchronization signal LP.
Are alternately distributed to generate a start signal DLP1 and an end signal DLP2. Therefore, the start signal DLP
1 indicates the start of a certain selection period, and the end signal DL
P2 indicates the end of the selection period.

The sorter 21 outputs the "H" level start signal DL
While outputting P1, the first counter 22 sets the count value C1 to "0" at the falling of the reference clock CLK.
Set to. Also, during this period, the horizontal synchronization signal L
Since P is also at the “H” level, the second counter 23 sets the count value C2 to “FFh”.

When the start signal DLP1 goes to "L" level, the first counter 22 increases the count value C1 by one every time the reference clock CLK falls. In the present embodiment, the division ratio of the division periods T1, T2, and T3 is 2:
It is set to 1: 1 and the equalization constant is 4. Therefore, when the count value C1 exceeds 3, the first counter 22 sets the count value C1 to “0” and outputs the carry signal SIG1 to the second counter 23. As a result,
As shown in FIG. 12, the count value C of the first counter 22 is
1 changes like 1, 2, 3, 0, 1, etc. The count value C1 corresponds to the remainder when the number of reference clocks CLK input from the start signal DLP1 to the present time is divided by an equal constant.

On the other hand, while the horizontal synchronization signal LP is at the "L" level, the second counter 23 outputs the carry signal SI.
G1 is counted. Therefore, the count value C2 of the second counter 23 starts from “FFh”, and every time the count value C1 becomes “0”, “00h”, “01”
h ”,“ 02h ”, and“ 03h ”, the count value increases in a cycle four times the reference clock CLK.
Is equivalent to a quotient obtained by dividing the number of reference clocks CLK input from the start signal DLP1 to the present time by an equal constant.

When the next horizontal synchronization signal LP is applied, the discriminator 21 outputs the end signal DLP2, and the memory 12 stores the two count values C1 and C2 at the rise of the end signal DLP2. . FIG. 12 shows a case where 17 reference clocks CLK are applied for each horizontal synchronization signal LP. Therefore, at the time when the end signal DLP2 rises, the count values C1 and C2 of the counters 22 and 23 are used. Are “1” and “03h”. As a result, the count value M1 ·
M2 is “1” and “03h”.

These values M1 and M2 are the remainder and the quotient obtained by dividing the number of reference clocks CLK applied in one selection period by an equal constant (in this case, 17/4 = 4, remainder 1). It corresponds to. Therefore, the count value M2 is
The number of reference clocks CLK for each equal period is indicated, and the count value M1 indicates the length of a period other than the equal number of equally divided periods in the selection period.

The synchronization unit 13 provided after the memory 12
And the equal period generation unit 14 calculates the count value M1 · M
2, a signal SIG3 for equally dividing each selection period by a predetermined equally constant is generated. Specifically, as shown in FIG. 13, when the horizontal synchronization signal LP is at the “H” level, the third counter 24 of the synchronization unit 13 outputs the count value from the memory 12 at the falling edge of the reference clock CLK. Read M1. In this case, since the memory 12 stores “1” as the count value M1, the count value C3 of the third counter 24 becomes “1”. On the other hand, since the horizontal synchronization signal LP is at “H” level, the NOR circuit 28 in the equal period generation unit 14 outputs the signal SIG3 at “L” level. Thus, the fourth counter 29 reads the count value M2 from the memory 12 at the falling edge of the reference clock CLK. In this case, the count value C4 of the fourth counter 29 is initialized to “03h”.

Subsequently, when the horizontal synchronizing signal LP goes to the “L” level, the third counter 24
Counts the count value C3 one by one at the fall of the reference clock CLK. Therefore, the count value C3 of the third counter 24 decreases to "1" and "0".
Further, the OR circuit 26 applies an “H” level signal to the D-FF circuit 27 while the count value C3 is not “0”, and the D-FF circuit 27 outputs the signal at the rise of the reference clock CLK. D latch. As a result, the synchronization unit 13
Is a period from when the horizontal synchronizing signal LP becomes “L” level to when the reference clock CLK is counted by the count value M1 stored in the memory 12 (in this case, one time), and The signal SIG2 is output.

As a result, in the equal period generation unit 14, the NOR circuit 28 also applies the “L” level signal SIG 3 to the fourth counter 29 during this period. Therefore, during this period, the count value C4 of the fourth counter 29
Is maintained as “03h”. Further, since the count value C4 of the fourth counter 29 has not reached “00h”, the equally-divided period generation unit 14 outputs the “L” level signal SIG.
4 is continuously output.

When the above period elapses, the third counter 24
Becomes zero, the output signal SIG2 of the synchronization unit 13 changes to the “L” level. At this time, the output signal SIG4 of the equal period generation unit 14 and the horizontal synchronization signal LP are also kept at the “L” level. Therefore, the output signal SIG2 of the NOR circuit 28
Changes to "H", and the fourth counter 29 starts counting down the count value C4 one by one from the next fall of the reference clock CLK.

Each time the reference clock CLK falls, the count value C4 of the fourth counter 29 becomes "03h", "0".
When the count value C4 reaches "00h", the fourth counter 29 outputs a signal at the "H" level, and the equally-divided period generation unit 14 outputs the signal from the next rising of the reference clock CLK. Output signal S of "H" level for one cycle
IG4 is output. Further, the output signal SIG4 becomes “H”.
During the level, the NOR circuit 28 includes the fourth counter 29
Then, the signal SIG3 of the "L" level is applied. Thus, the count value C4 of the fourth counter 29 is stored in the memory 12
Is initialized to the count value M1 stored in on the other hand,
Next, until the horizontal synchronization signal LP is applied, the third
Since the count value C3 of the counter 24 is maintained at "0", the output signal SIG2 of the synchronization section 13 is maintained at the "L" level. Therefore, the output signal SIG4
Becomes "L" level, the fourth counter 29 indicates "
The read signal SIG3 of H level is applied.

Thus, the count value C of the fourth counter 29 is maintained until the next horizontal synchronization signal LP is applied.
4 is initialized for each count value M2 stored in the memory 12 every time it reaches “00h”,
Outputs an output signal SIG4 at a constant cycle corresponding to the count value M2. In this case, since the count value M2 is "03h", the cycle of the output signal SIG4 is
The period becomes four times the period of the reference clock CLK.

On the other hand, the fifth counter 32 shown in FIG. 1 is initialized to “0” while the horizontal synchronization signal LP is at “H” level, as shown in FIG. Each time the output signal SIG4 is applied from the unit 14, the count value C5 is increased by one. The count value C
Reference numeral 5 indicates how many times the output signal SIG4 has been applied during the current selection period, that is, what number of equal periods the current time is. The D-FF circuit 33 outputs the output signal SIG4 at the rising of the reference clock CLK.
At the time of generating the timing signals P1, P2, and P3, the reference pulse signal SIG5 is generated.

In the output section 34, when the count value C5 is "
During the period of “0”, both the output signals Qa and Qb of the fifth counter 32 are at the “L” level.
Of the inputs of the D circuit 35a, the inputs corresponding to both outputs Qa and Qb are both at the “H” level. Therefore, during this period, the timing signal P1 changes to the pulse signal SI.
It is output at the timing of G5. On the other hand, the count value C5
Is "0", one of the remaining inputs of the AND circuits 35b and 35c is always at "L" level. Therefore, the timing signals P2 and P3 are maintained at "L" level regardless of the pulse signal SIG5.

While the count value C5 is "1", one of the inputs of each of the AND circuits 35a to 35c is always "L".
Level, the timing signals P1 and P2
P3 is always kept at the “L” level. Similarly, while the count value C5 is "2", the timing signal P
Only 2 changes according to the pulse signal SIG5, and while the count value C5 is "3", only the timing signal P3 changes according to the pulse signal SIG5.

As described above, the period during which the equal period generation unit 14 applies the pulse signal SIG5 is constant, and the number applied during the selection period is set to an equal constant. Therefore, the timing signal generator 15 sets the selection period to 2:
The timing signals P1, P2, and P3 can be output at timings divided at a division ratio of 1: 1.

As shown in FIG. 12, the initial parameter calculator 11 starts calculating the count values C1 and C2 every time the signal DLP1 indicating the start of the selection period is applied. Each time the signal DLP2 indicating the end is applied, both count values C1 and C2 are stored as M1 and M2. On the other hand, as shown in FIGS. 13 and 14, every time the horizontal synchronization signal LP is applied, the third to fifth signals are applied.
Since the counters 23, 29, and 32 are initialized, the synchronizing unit 13, the equal period generation unit 14, and the timing signal generation unit 15 repeat the same operation. Therefore, in the subsequent selection periods, the timing generation circuit 10 divides each selection period into the divided periods T1, T2, T
It can be divided into three.

When the control unit 6 having the timing generation circuit 10 is connected to another display panel 3 having a different number of picture elements, for example, the number of reference clocks CLK in the selection period changes. However, also in this case, the initial parameter calculating unit 11 similarly starts calculating the count values C1 and C2 from the start of the selection period, and
2 stores the count values M1 and M2 at the end of the selection period. For example, when the number of the reference clocks CLK is 901, since 901 = 4 × 225 + 1, “1” is stored as the count value M1 in the memory 12, and “E0h (224)” is stored as the count value M2. Is stored.
Since the equal period generation unit 14 sets the cycle of the output signal SIG4 based on the count value M2, the timing generation circuit 10 can divide the selection period at a predetermined division ratio without any problem. Further, when an equal period is generated based on the count value M2, the total of the four equal periods is 900 for the reference clock CLK, and one for the reference clock CLK during the selection period. An error occurs. However, the synchronization unit 13 stops the operation of the equally-divided period generation unit 14 from the falling of the horizontal synchronization signal LP to the counting of the reference clock CLK by the count value M1 (“1”). Let it. As a result, the first equal period is extended by the above error, and the last divided period T
In the end time point of 3, that is, in the next selection period, the start time point of the first divided period T1 exactly matches the start time point of the selection period.

As described above, the timing generation circuit 10 according to the present embodiment includes the two-terminal nonlinear element 2a shown in FIG.
1. A circuit for generating a timing for applying a voltage to the picture element 2 having a reference clock CLK, which is synchronized with the selection period and has a shorter period than the selection period, as shown in FIG.
And an initial parameter calculating unit 11 for calculating parameters for dividing the subsequent selection period based on the horizontal synchronization signal LP indicating the selection period, a memory 12 for storing the parameters, and , A synchronizing unit 13 for generating timing signals P1, P2, and P3 for dividing the subsequent selection period into respective division periods from the reference clock CLK, an equal period generation unit 14, and a timing signal generation unit 15.

In the above configuration, before the timing signal generator 15 generates the timing signal, the initial parameter calculator 11 calculates the parameters for each display panel 3 based on the reference clock CLK, The equal period generation unit 14 and the timing signal generation unit 15 generate the timing signals P1, P2, P based on the parameters.
3 is generated. Thus, regardless of the number of reference clocks in one selection period, the timing generation circuit 10 can divide each selection period at a desired division ratio, and can reduce afterimages on the display panel 3 and the like. As a result, for example, the timing generation circuit 10 can be shared between different users using the external interface signals IN having different reference clock numbers within one selection period, such as between the display panels 3 having different numbers of picture elements 2.

As the reference clock CLK, a signal externally applied to the liquid crystal display element such as a signal synchronized with the data signal DATA can be used. Therefore, for example, even when the interface between the external circuit and the timing generation circuit 10 such as a circuit that supplies the data signal DATA is set in the same manner as in the related art, it is necessary to newly generate a signal for dividing the selection period. Disappears.
As a result, the external interface signal IN can be set in the same manner as in the related art, and an external circuit can be shared between driving devices that do not divide the selection period and driving devices having different division ratios. In addition, a circuit for generating the signal, such as a PLL (Phase Locked Loop) circuit, becomes unnecessary, and the timing generation circuit 10
Can be simplified.

Further, in addition to the above configuration, the initial parameter calculator 11 according to the present embodiment includes a first counter 2 for repeatedly counting the reference clock CLK by an equal constant.
2 and a second counter 23 that counts the number of cycles of the first counter 22. The memory 12 stores, as the parameter, the count value C2 of the second counter 22 during the selection period, the count value M2 Is provided. Further, a fourth counter 29 that repeatedly counts the reference clock CLK according to the count value M2, and a cycle of the fourth counter 29 according to the cycle of the fourth counter 29
A timing signal generator 15 for generating the timing signals P1, P2, and P3. Thereby, the memory 12 stores the count value M2 corresponding to the reference clock number for each equal period.

On the other hand, the fourth counter 29 counts the reference clock CLK by the number based on the count value C2, for example, up to the count value M2. As a result, the fourth
The cycle of the counter 29 is an equal period. Further, the timing signal generator 15 outputs the timing signals P1, P2, and P3 by combining the equal time periods.

As a result, regardless of the number of reference clocks in one selection period, the timing generation circuit 10 can divide each selection period at a desired division ratio. Therefore, the timing generation circuit 10 can be shared between the display panels 3 having different ratios between the period of the reference clock CLK and the selection period using the same external interface signal IN as in the related art.

When the selection period is divided by a desired division ratio, an error occurs when the reference clock number within the selection period cannot be divided by an integer. Specifically, since the count value M2 is an integer indicating the number of reference clocks within the equal period, the period equal to a constant constant multiple of the cycle of the fourth counter 29 does not match the selection period.

On the other hand, the timing generation circuit 10 according to the present embodiment has the
At the end of counting by the second counter 23, the count value C1 of the first counter 22 is stored as a count value M1, and the synchronizing unit 13 stores, for each selection period,
A fourth counter that counts the reference clock CLK according to the count value M1 is provided.

The count value M1 indicates the remainder when the number of reference clocks in the selection period is divided by an equal constant. Therefore, the time when the timing signals P1, P2, and P3 are output is adjusted only during the period in which the third counter 24 counts, for example, by stopping the operation of the equal period generation unit 14, thereby generating the error. Can be prevented. As a result, even when the number of reference clocks in the selection period cannot be divided by an integer, the selection period can be reliably synchronized with the timing signals P1, P2, and P3.

In this embodiment, the count value M2
Indicates a quotient obtained by dividing the number of reference clocks in the selection period by an equal constant, and the decimal part is truncated. As a result, the selection period is longer than a period that is a constant multiple of the equal period. Therefore, the synchronization unit 13
Although the generation of the timing signals P1, P2, and P3 is delayed, the present invention is not limited to this. For example, when the value after the decimal point is rounded up, the selection period is shorter, so only during the period indicated by the count value M1 stored in the memory 12,
The timing signals P1, P2, and P3 may be generated earlier by shortening one of the equal periods. Also,
The timing signals P1, P2, and P3 may be synchronized with the selection period by adjusting the count value of the fourth counter 29, for example, at the time of application of the horizontal synchronization signal LP.
In any case, since the synchronization with the selection period can be achieved, the same effect as that of the present embodiment can be obtained. However,
In these cases, it is necessary to set the count value of the fourth counter 29 to a small value in a certain equal period, so that the circuit becomes more complicated than the configuration of the present embodiment.

In the present embodiment, the maximum countable values of the first to fifth counters 22, 23, 24, 29, and 32 are 4, 256, 4, 25, respectively.
6 and 4, but are not limited to this.
The maximum values of the first, third, and fifth counters may be the same as the equal constants. Also, the second and fourth counters 23
As described above, if the maximum value of 29 is set according to the maximum value of the reference clock CLK applied during the selection period, the same effect as in the present embodiment can be obtained.

Further, in this embodiment, each counter 22
Reference numerals 23, 24, 29, and 32 denote binary counters. Each count value is incremented or decremented by one in binary notation. However, the present invention is not limited to this. For example, a gray code may be used. Count-up, count-down, and match / mismatch with the initial value can be uniquely defined, the first and third counters 23 and 24 have the same code, and the second and fourth counters 23 and 29 have the same code. Then, the same effect as in the present embodiment can be obtained.

[0110]

As described above, the display panel driving apparatus according to the first aspect of the present invention is based on the reference clock synchronized with the selection period and having a shorter period than the selection period and the signal indicating the selection period. Parameter calculation means for calculating a parameter for dividing the subsequent selection period, storage means for storing the parameter, based on the parameter,
From the signal and a reference clock indicating the selection period, Bei example a timing generating means for generating a timing signal for dividing a subsequent selection period to the divided periods, the parameter calculation
The output means is a constant based on the division ratio of the above division period
A first counter for counting the reference clock repeatedly.
And a second counting the number of repetition periods of the first counter.
A counter, and the storage means stores the parameter
At the end of the counting by the second counter.
Storage area for storing the first count value of the first counter
And the second counter of the second counter during the selection period.
And a storage area for storing default values.
The timing generating means is responsive to the second count value.
And a counter for evenly counting the reference clock repeatedly.
For each selection period according to the first count value.
A synchronization counter for counting quasi-clocks and the
The above timing signal is output according to the cycle of the
And the synchronization counter generates the first count value.
Timing signal only during the period when the reference clock is counted
And an output unit that adjusts the time at which the signal is output .

In the above configuration, before the timing generation means generates the timing signal, the parameter calculation means calculates a parameter for each display panel based on the reference clock, and the timing generation means calculates the parameter based on the parameter. Generate a timing signal. This allows
Regardless number of reference clocks in one selection period, the driving device can divide each selection period at the desired division ratio, the display panel
Etc. can be reduced afterimage Le. As a result, there is an effect that the drive device of the display panel can be shared between users having different reference clock numbers within one selection period while maintaining the same external interface as the conventional one.

Further, in the above configuration, the synchronization counter counts the reference clock according to the first count value for each selection period. Since this period coincides with the period of the error, the timing of outputting the timing signal is adjusted only during this period, so that even if the reference clock number in the selection period cannot be divided by an integer, This has the effect that the period and the timing signal can be reliably synchronized.

A driving device for a display panel according to the second aspect of the present invention.
The position is based on the external interface signal as described above.
Divides each selected period into a plurality of divided periods, and
Timing generation circuit for generating a timing signal indicating the interval
The timing generation circuit having a control unit provided with
Is based on the horizontal sync signal and the reference clock.
The above selection period is a constant based on the division ratio of each division period.
A first count value indicating an error when equally divided, and equally divided
Second count indicating the number of reference clocks in the specified period
Initial parameters for calculating initial parameters consisting of default values
A calculating unit, a memory for holding the two count values,
Equally divided based on the second count value held in the memory
An equal-period generation unit that generates a pulse signal for each set period,
Timing that indicates each divided period based on the pulse signal
A timing signal generator for generating a switching signal, and the memory
Based on the first count value held in
Delay or advance the generation of the analog signal to adjust the error at the same time
And synchronizes the selection period with the timing signal.
This is a configuration including a synchronization unit.

Therefore, the selection period and the timing signal
Synchronization is possible and the reference clock within one selection period
Using external interface signals with different numbers of locks,
If the timing generation circuit can be shared between different users
This has the effect.

[Brief description of the drawings]

FIG. 1 illustrates one embodiment of the present invention, and is a block diagram illustrating a main part of a timing generation circuit that generates drive timing in a liquid crystal display device.

FIG. 2 is a block diagram showing a main part of the entire liquid crystal display device.

FIG. 3 is a circuit diagram showing a main configuration of a picture element in the liquid crystal display device.

FIG. 4 is a waveform chart showing an example of a signal supplied from the outside in the liquid crystal display device.

FIG. 5 is a circuit diagram showing a main configuration of a classifier for classifying a horizontal synchronization signal in the timing generation circuit.

FIG. 6 is a circuit diagram showing a main configuration of a first counter that repeatedly counts a reference clock up to an equal constant in the timing generation circuit.

FIG. 7 is a timing generation circuit that counts the number of cycles of the first counter in one selection period.
FIG. 3 is a circuit diagram illustrating a main configuration of a counter.

FIG. 8 is a circuit diagram showing a main configuration of a memory for holding count values of the first and second counters in the timing generation circuit.

FIG. 9 is a circuit diagram showing a main configuration of a third counter that counts reference clocks by the count value of the first counter held by the memory in the timing generation circuit.

FIG. 10 is a circuit diagram showing a main configuration of a fourth counter that counts reference clocks by the count value of the second counter held by the memory in the timing generation circuit.

FIG. 11 is a circuit diagram showing a main configuration of a fifth counter for counting the number of cycles of the fourth counter in the selection period in the timing generation circuit.

FIG. 12 is a timing chart showing an operation of an initial parameter calculation unit in each selection period in the timing generation circuit.

FIG. 13 is a timing chart showing the operation of the synchronization section and the equal period generation section during each selection period in the timing generation circuit.

FIG. 14 is a timing chart showing an operation of a timing signal generation unit in each selection period in the timing generation circuit.

FIG. 15 illustrates a conventional example, and is a graph illustrating current-voltage characteristics of a two-terminal nonlinear element used as a switching element in a picture element of a liquid crystal display device.

FIG. 16 is a waveform diagram showing a voltage applied to the picture element when driving by a voltage averaging method.

FIG. 17 is a block diagram illustrating a main configuration of the entire liquid crystal display device.

FIG. 18 is a waveform diagram showing a voltage applied to a certain picture element in the liquid crystal display device.

FIGS. 19A and 19B show an afterimage phenomenon that occurs in the liquid crystal display device. FIG. 19A is an explanatory diagram showing an original image, and FIG. 19B is an explanatory diagram showing an image in which an afterimage has occurred.

FIG. 20 is a graph showing transmittance-voltage characteristics of a liquid crystal element in a picture element of the liquid crystal display device.

FIG. 21 illustrates a shift amount of a voltage at which the transmittance of a liquid crystal element becomes 50% in the above liquid crystal display device, and illustrates a relationship between a shift amount and an application time when different voltages are applied to picture elements. It is a graph shown.

[Explanation of symbols]

2 picture elements 2a 2-terminal type non-linear element (nonlinear element) 3 display panel 4 scan electrode driving circuit (driving device) 5 data electrode driving circuit (driving device) 6 control unit (driving unit) 11 initial parameter calculation unit (parameter calculation Means) 12 memory (storage means) 13 synchronization section (timing generation means) 14 equally-divided period generation section (timing generation means) 15 timing signal generation section (timing generation means;
Output section) 22 First counter 23 Second counter 24 Third counter (synchronization counter) 29 Fourth counter (equal counter) 71 D-FF circuit (storage area)

Claims (2)

(57) [Claims] 1. A display panel driving apparatus which divides a selection period for setting a display state of a picture element having a non-linear element into a plurality of periods and applies different voltages to the picture element for each divided period. Parameter calculating means for calculating a parameter for dividing a subsequent selection period based on a reference clock synchronized with the selection period and having a shorter cycle than the selection period, and a signal indicating the selection period; storage means for storing, based on the parameter, from the signal and a reference clock indicating the selection period, e Bei and timing generating means for generating a timing signal for dividing a subsequent selection period to each division period, the parameters The calculating means is based on the division ratio of the division period.
The above reference clock is counted repeatedly by the constant
A first counter and the number of repetition periods of the first counter
And a second counter for counting the second counter, and the storage means stores the second counter as the parameter.
At the end of counting of the counter.
A storage area for storing one count value and a storage area within a selection period
Storage area for storing a second count value of the second counter
And the timing generation means according to the second count value.
And a counter for evenly counting the reference clock repeatedly.
And a reference clock for each selection period according to the first count value.
The above counter is determined according to the synchronization counter for counting locks and the repetition period of the equal counter.
Generates an imaging signal and the counter for synchronization
This is the period when the reference clock is counted according to the first count value.
And an output unit for adjusting the timing of outputting the timing signal.
A driving device for a display panel, comprising: 2. The method according to claim 2 , wherein each of the
Divide the selection period into multiple division periods and indicate each division period
A timing generation circuit for generating a timing signal is provided.
It has a control unit, the timing generation circuit, the horizontal synchronizing signal and the reference clock
Based on the lock and the split ratio of each of the above split periods
The first factor that indicates the error when the selection period is equally divided by the constant
Count and the reference clock for the time period
Initial parameter consisting of a second count value indicating the number of
An initial parameter calculation unit which calculates a memory for holding the two count values, based on the second count value held in the memory, etc.
Equal period generation unit that generates a pulse signal for each divided period
And a timing indicating each divided period based on the pulse signal.
A timing signal generating unit for generating a switching signal, and a first count value stored in the memory.
Delay or advance the generation of the timing signal
A synchronization unit for synchronizing the period with the above timing signal is provided.
A driving device for a display panel, comprising: