JP3353771B2 - Power delay circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power supply delay circuit, and more particularly, to a power supply delay circuit that takes measures against power supply delay and electromagnetic interference.

[0002]

2. Description of the Related Art In a normal power supply circuit, a plurality of output voltages are output almost simultaneously. For example, integrated circuits (Integrated
Circuit: hereinafter referred to as IC) 3.3V, 5V, 12
V may be output to the IC almost simultaneously. recently,
Further, the power supply voltage is set to another voltage value (for example, 2.5 V).
To be input to an IC.

FIG. 4 shows a general conventional power supply delay circuit.
This will be described with reference to FIG. FIG. 4 is a block diagram when an IC is connected to a general power supply delay circuit of the related art. A general conventional power supply delay circuit includes a regulator 1 and a regulator 2 when two power supply voltages each having a predetermined voltage value are converted and input to two input terminals of the circuit. In the block diagram shown in FIG. 4, the predetermined voltage values of the respective power supplies are 5 V and 12 V, and the circuit that inputs the converted voltages is the IC 13 that inputs 2.5 V and 3.3 V. This conventional power supply delay circuit has a 12 V
Is connected to the input terminal of the regulator 1, and the output terminal of the regulator 1 is connected to the input terminal of the IC 13 for inputting the 3.3V voltage. A 5V power supply is connected to the input terminal of the regulator 2, and the output terminal of the regulator 2 is connected to the I terminal.
Connect to the input terminal of C13 for inputting 2.5V voltage.
That is, the regulator 1 converts a voltage of 12V to 3.3V, and the regulator 2 converts a voltage of 5V to 2.5V.

[0004] 2.5 V after voltage conversion by a regulator (1, 2) in a general conventional power supply delay circuit and 3.
The rising of the voltages of 3 V and 5 V will be described with reference to FIG. FIG. 5 shows a change in a voltage value with respect to time on a line to which a voltage value of 2.5 V, 3.3 V, and 5 V is applied in a general conventional power supply delay circuit. The operating potential at which the IC 13 becomes operable is usually about 2.5V. As shown in FIG. 5, in the conventional power supply delay circuit described above, the IC 13
Becomes operable at 2.5V compared to 2.5V.
3V reaches the operating potential at an earlier time.

However, in the specification of IC13, 3.3 V
Since it is necessary to input a voltage of 2.5 V to the IC 13 earlier than the voltage of the IC 13, the conventional power supply delay circuit shown in FIG. 5 has a problem that the input power supply sequence of the IC 13 is ignored. .

In order to solve this problem, there is a circuit having a delay circuit including a capacitor and a resistor in addition to the above-described conventional power supply delay circuit. In this circuit, the rise time of the voltage is delayed by a predetermined amount by adjusting the capacitance and the resistance value of the capacitor. If this delay circuit is connected to a line to which a 3.3V voltage is applied, it is 3.3V compared to 2.5V.
V can reach the operating potential at a later time.

[0007]

However, the delay circuit composed of the capacitor and the resistor has an electromagnetic interference (ElectroMagneti).
c Interference: hereinafter referred to as EMI). In addition, since the noise (hereinafter, referred to as EMI noise) due to the EMI to the power supply is large, there is a problem that the EMI noise is further amplified by a power supply cable or the like. Further, there may be a case where a product error occurs in the capacitance of the capacitor, and in this case, the shift of the delay time differs for each power supply delay circuit, and there is a problem that the product reliability of the power supply delay circuit decreases.

In view of the above-mentioned problems in the prior art, the present invention can control the rising times of a plurality of output voltages,
It is an object of the present invention to provide a power supply delay circuit that reduces I noise and has an accurate delay time.

[0009]

According to a first aspect of the present invention, there is provided a power supply delay circuit for converting an input voltage value into a predetermined value and outputting the converted value, and having a reduced number of input terminals.
Both have at least two or more regulators provided two or more, is applied an input voltage to an input terminal of at least one regulator Rutotomoni, the other input terminal, the line length
Other regulation via a connection line adjustable to a given length
The output terminal of the power supply is connected .

Therefore, according to the power supply delay circuit of the first aspect of the present invention, it becomes possible to apply input terminals in a desired order to a plurality of input terminals such as ICs. For example, it becomes possible to follow the sequence of the input power of the IC. Further, since the regulator performs voltage transformation using transistors, noise such as EMI noise can be reduced as compared with a voltage transformation circuit using only an inductance and a capacitor. Here, the predetermined value is a voltage value required by a circuit to be driven by supplying a voltage. For example, in the power supply delay circuit according to the embodiment of the present invention, a circuit to be driven by supplying a voltage corresponds to the IC 13 as shown in FIG. Therefore, in the example of FIG. 1, the predetermined values are 2.5V and 3.3V. Also, the input terminal of one regulator
If the line length with the output terminal of another regulator is adjusted, I
Multiple outputs of power delay circuit input to input terminals such as C
The delay time can be freely adjusted between the voltages.
In other words, the longer the line length, the longer the delay time and the shorter the line length.
If this is done, the delay time can be shortened. here
The predetermined length is defined as a power supply delay input to an input terminal such as an IC.
Connected with this line among multiple output voltages of the extension circuit
Between the voltages output from the two regulators.
This value is proportional to the delay time. This delay time and predetermined
The relationship with the length of
Is set in advance using the calculation by

The power supply delay circuit according to the second aspect of the present invention is the power supply delay circuit according to the first aspect of the present invention, wherein one end of a resistor is connected to a line connecting an input terminal of a predetermined regulator to an output terminal of another regulator. And the other end of the resistor is grounded.

Therefore, according to the power supply delay circuit of the second aspect of the present invention, when the regulator that connects one end of the resistor to the line to which the output terminal is connected is off, the output terminal of this regulator is connected to the input terminal. A low (about 0 V) signal can be secured at the output terminal of the regulator that connects one end of the resistor to the line to which the output terminal is connected so that the regulator does not turn on. here,
The predetermined regulator is the input terminal of this regulator (inputs the signal to turn on and off the output of the regulator)
Is connected to the output terminal of another regulator, and outputs a voltage delayed with respect to the output voltage of the other regulator.

The power supply delay circuit according to the third invention of the present application is the power supply delay circuit according to the first invention or the second invention of the present application ,
A capacitor is connected to at least one of the input line and the output line of the regulator.

Therefore, according to the power supply delay circuit of the third invention of the present application, the EM mainly due to the high frequency electromagnetic wave component is generated.
I noise can be suppressed.

A power supply delay circuit according to a fourth aspect of the present invention is the power supply delay circuit according to any one of the first to third aspects of the present invention, wherein an output terminal of the regulator is connected to an input terminal of the integrated circuit. It is characterized by the following.

Therefore, according to the power supply delay circuit of the fifth aspect of the present invention, the voltage to be input to the input terminal of the IC can be input in a desired order, and the voltage is applied to the IC so as to match the sequence of the IC. It becomes possible to apply a voltage.

According to a fifth aspect of the present invention, there is provided the power supply delay circuit according to any one of the first to fourth aspects of the present invention, wherein the input line of the regulator includes an inductance.

Therefore, according to the fifth power supply delay circuit of the present application, EMI noise caused by the power supply delay circuit can be further reduced.

[0019]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A power supply delay circuit according to an embodiment of the present invention will be described with reference to FIGS.

A power supply delay circuit according to the present embodiment will be described with reference to FIG. FIG. 1 shows a power supply delay circuit according to the present embodiment in which the output is I
It is a block diagram in case C is installed. The power supply delay circuit according to the present embodiment includes a regulator 1, a regulator 2, a decoupling capacitor 3, a decoupling capacitor 4, a decoupling capacitor 5, and a resistor 14. The regulator 1 and the regulator 2 include a transistor (not shown) and are switched by the transistor.

A power supply 10 is connected to the input terminals (6, 8) of the regulator 1 and the regulator 2, respectively. One end of the decoupling capacitor 3 is connected between the input terminals (6, 8) of the regulators 1 and 2, and the power supply 10, and the other end is grounded. The output terminal 7 of the regulator 1 is connected to the input terminal 11 of the IC 13. Also,
One end of the decoupling capacitor 4 is connected between the output terminal 7 and the input terminal 11, and the other end is grounded. Output terminal 9 of regulator 2 is connected to input terminal 12 of IC 13. One end of the decoupling capacitor 5 is connected between the output terminal 9 and the input terminal 12, and the other end is grounded. One end of the resistor 14 is connected between one end of the decoupling capacitor 5 and the output terminal 9, and the other end is grounded. Further, the input terminal 61 of the regulator 1
And the output terminal 9 are connected.

Since the regulators (1, 2) perform voltage transformation using transistors, noise such as EMI noise can be reduced as compared with a voltage transformation circuit (not shown) using only an inductance and a capacitor.

Next, the operation of the power supply delay circuit according to the present embodiment will be described with reference to FIG. A voltage of 5 V from the power supply 10 is input to respective input terminals (6, 8) of the regulator 1 and the regulator 2. The regulator 2 receives the voltage of 5V, and the output terminal 9
Output a voltage of 2.5V. Here regulator 2
The regulator 1 is not operating when operates. The regulator 1 operates only when a predetermined voltage value (2.5 V in the present embodiment) is applied to the input terminal 61. Then, the voltage applied to the input terminal 6 is converted into a predetermined voltage value (3.3 V in the present embodiment) and output from the output terminal 7. Therefore, the regulator 1 receives a voltage of 5 V at the input terminal 6, and further receives a voltage of 2.5 V at the input terminal 61 from the output terminal 9 of the regulator 2.
A voltage of 3.3 V is output from the output terminal 7.

The decoupling capacitors (3, 3)
4, 5) are provided to suppress EMI noise. In the present embodiment, for example, a capacitor of about 0.1 μF or less is used. This makes it possible to suppress EMI noise mainly caused by high frequency electromagnetic wave components. Further, when the regulator 2 is off, the resistor 14 prevents the regulator 1 from turning on.
Is installed in order to secure a low (about 0 V) signal at the output terminal. By the operation of the power supply delay circuit according to the present embodiment, the power supply voltage of 5 V is changed to 2.5 V, 3.3 V
To 3.3V and delay 3.3V compared to 2.5V to IC
13 can be input.

IC in power supply delay circuit according to the present embodiment
The history of the voltage value at the second input terminal will be described with reference to FIG. FIG. 2 is a diagram showing a change in the voltage value with respect to time when the voltage values of 2.5 V and 3.3 V in the power supply delay circuit of the present embodiment are applied to the two input terminals of the IC 13, respectively. As shown in FIG. 2, the 2.5V voltage output from the output terminal 9 is output earlier than the 3.3V voltage output from the output terminal 7, and the operating voltage value ( About 2.5 V). Therefore, a voltage of 3.3 V is applied to the input terminal 11 of the IC 13 later than the input terminal 12, and a voltage of 2.5 V is applied to the input terminal 12 earlier than the input terminal 11. it can. As a result, a voltage of 2.5 V can be input to the IC 13 earlier than a voltage of 3.3 V, and the sequence of the input power supply of the IC 13 can be followed.

In the power supply delay circuit according to the present embodiment, the line length from the output terminal 9 to the input terminal 61 is adjusted to output from the output terminal 7 in comparison with the voltage output from the output terminal 9. The time that the voltage is delayed can be adjusted. That is, if the line length from the output terminal 9 to the input terminal 61 is increased, the propagation delay time from the output terminal 9 to the input terminal 61 is increased. The time to delay the output voltage becomes longer. For example, in the voltage time history curve shown in FIG. 2, the line length from the output terminal 9 to the input terminal 61 is set to about 5 cm. In FIG. 2, the time for delaying the voltage output from the output terminal 7 compared to the voltage output from the output terminal 9 is about 250 μsec. Since the delay time can be easily adjusted by the line length from the output terminal 9 to the input terminal 61, there is almost no need to consider a manufacturing error of the regulator component. In addition, the delay time adjustment method allows the delay time to be set accurately.

Further, in the power supply delay circuit according to the present embodiment, an inductance 15 may be inserted between the power supply 10 and the input terminals 6 and 8 of the regulators 1 and 2 as shown in FIG. . FIG. 3 shows two regulators (1, 1) in the power supply delay circuit of the present embodiment.
It is a block diagram in the case where the inductance 15 is inserted between each input terminal (6, 8) of 2) and the power supply 10. By inserting the inductance 15 in this manner, it is possible to further reduce EMI noise caused by the power supply delay circuit.

In the power supply delay circuit of the present embodiment, IC1
Since there were two input terminals of the regulator 3, the regulator (1,
2) were provided. However, when there are three or more terminals of an IC or the like for inputting the transformed voltage and the respective voltage values are different, the same number of regulators as the number of input terminals are provided. Each of the regulators has at least two or more input terminals. At least one of the regulators has an input terminal to which an input voltage is applied, and an other input terminal to which an output voltage from another regulator is applied. This makes it possible to input the voltage to be input to the input terminal of the IC or the like in a desired order.

According to the power supply delay circuit of the embodiment of the present invention, the input voltage value (5 V) is changed to the predetermined value (2.5 V,
3.3V), there are two (1, 2) regulators each including a transistor for outputting the converted voltage. Each of the regulators has at least two or more input terminals. Is applied, and the output voltage (2.5V voltage) from the regulator 2 is applied to the other input terminal 61, so that the 5V power supply voltage is converted to 2.5V, 3.3V, and 2.5V. Can be input to the IC 13 with a delay of 3.3 V. Therefore, the sequence of the input power supply of the IC 13 can be followed. The regulator (1,
The EMI noise can be suppressed by connecting the decoupling capacitors (3, 4, 5) to the input line and the output line in 2). In addition, the regulator (1,
When the input line 2) includes the inductance 15, the EMI noise caused by the power supply delay circuit can be further reduced.

[0030]

As described above, in the power supply delay circuit of the present invention, noise such as EMI noise can be reduced as compared with a transformer circuit using an inductance and a capacitor. Further, it is possible to control the rising time of a plurality of output voltages from the power supply delay circuit. Further, it becomes possible to suppress EMI noise caused by high frequency electromagnetic wave components. Further, the delay time can be set accurately. Further, by inserting an inductance, EMI noise due to the regulator can be further reduced. In addition, there is no need to make fine adjustments such as delaying the rise time by using a capacitor or the like, so that there is an effect that it is not necessary to consider manufacturing errors of parts.

[Brief description of the drawings]

FIG. 1 is a block diagram when an IC is provided at an output as a device driven by a power supply in a power supply delay circuit according to an embodiment of the present invention.

FIG. 2 is a diagram showing a change in voltage value with respect to time when voltage values of 2.5 V and 3.3 V are applied to two input terminals of an IC in a power supply delay circuit according to an embodiment of the present invention; .

FIG. 3 is a block diagram of the power supply delay circuit according to the embodiment of the present invention when an inductance is inserted between each input terminal of the two regulators and the power supply.

FIG. 4 is a block diagram in a case where an IC is connected to a general conventional power supply delay circuit.

FIG. 5 shows a change in a voltage value with respect to time on a line to which a voltage value of 2.5 V, 3.3 V, and 5 V is applied in a general conventional power supply delay circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Regulator 2 Regulator 3 Decoupling capacitor 4 Decoupling capacitor 5 Decoupling capacitor 6 Input terminal 61 Input terminal 7 Output terminal 8 Input terminal 9 Output terminal 10 Power supply 11 Input terminal 12 Input terminal 13 IC 14 Resistance

Claims (5)

(57) [Claims] A transistor for converting an input voltage value to a predetermined value and outputting the converted value; and at least two input terminals are provided.
The input voltage is applied to one input terminal of at least one regulator.
At the same time , adjust the wire length to the specified length for other input terminals.
Output terminals of other regulators
A power supply delay circuit characterized by being connected . 2. The circuit according to claim 1, wherein one end of a resistor is connected to a line connecting an input terminal of a predetermined regulator to an output terminal of another regulator, and the other end of the resistor is grounded. Power delay circuit. 3. A power delay circuit according to claim 1 or claim 2, wherein at least a capacitor to one of the regulator input and output lines are characterized by being connected. 4. A according claim 1, the regulator of the output terminals, characterized in that it is connected to an input terminal of the integrated circuit
Item 4. The power supply delay circuit according to any one of Items 3 . 5. The power supply delay circuit according to claim 1, wherein an input line of the regulator includes an inductance.