JP3353739B2 - Calculation method and calculation device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method and an apparatus for calculating a delay between gates in designing a semiconductor integrated circuit.

[0002]

2. Description of the Related Art In designing a semiconductor integrated circuit (LSI), it is important to accurately determine a delay time between gates. For example, in the layout design, a performance-oriented layout that optimizes a wiring delay by performing a timing analysis based on a virtual wiring length at an arrangement stage is performed. For that purpose, it is necessary to obtain a delay time between gates with high accuracy. Further, in order to minimize the delay in a long wiring length between gates, the wiring is divided into a plurality of parts by some inverters. In order to determine the insertion pitch of the inverter that minimizes the delay, It is necessary to accurately determine the delay time of the wiring between them.

As a delay equation used for calculating a gate-to-gate delay, there is an Elmore delay equation. Elmore's delay equation is derived by assuming a step pulse as an input signal and solving a differential equation.
For example, as shown in FIG. 25, the output resistance of the gate is R _gout ,
The input capacitance of the next stage gate is C _gin , the wiring resistance and the wiring capacitance per unit length between the gates are R _int and C _int ,
Assuming that the wiring length between gates is L _int , the delay T _d between gates
Is calculated as follows according to Elmore's delay equation:

T _d = R _gout (C _int L _int + C _gin ) + R _int L _int (0.5 C _int L _int + C _gin ) (1)

As an improved version of Elmore's delay formula,
Bakoglu has proposed the following delay equation:

T _d = R _gout (0.7 C _int L _int +0.7 C _gin ) + R _int L _int (0.4 C _int L _int +0.7 C _gin ) (2)

On the other hand, a technique for obtaining delay data between gates from an actually manufactured semiconductor device instead of a theoretical method is described in Japanese Patent Application Laid-Open No. Hei 3-228353. In this technique, a TEG for measuring a delay time of a logic circuit is used.
Using a ring oscillator as a (Test Element Group), a ring oscillator using the same gate as that constituting the circuit of the gate array is formed on each gate array chip formed on the wafer, and the ring oscillator is Try to get delayed data.

A technique for extracting some element characteristics from an actually manufactured semiconductor device is disclosed in Japanese Patent Application Laid-Open No. 9-12843.
No. 3 also describes this. The technology described in the publication is
The purpose is to calculate the diffusion resistance value of the impurity diffusion layer,
Several calculation formulas for calculating the diffusion resistance value of the impurity diffusion layer are prepared, and each calculation formula is applied to a figure constituting the impurity diffusion layer in the LSI layout pattern to calculate the diffusion resistance value. A circuit simulation was performed by applying the calculated diffusion resistance values to the netlist corresponding to the LSI layout pattern, and a specific value indicating the delay time was determined for each application of the diffusion resistance value, and actually measured from the actually created LSI. By comparing with a characteristic value, it is determined which calculation formula is optimal.

[0009]

Problems to be Solved by the Invention
The delay value obtained by the technique described in Japanese Patent Application Laid-Open Publication No. 3 (2003) only indicates the value of the inter-gate delay when the same gate as that constituting the circuit of the gate array is used. Therefore, although it is a useful technique in a semiconductor device in which the same kind of gates are regularly arranged like a gate array, various kinds of gates having different gate sizes, wiring widths between gates, wiring lengths, and the like are mixed. It cannot be applied to a simple semiconductor device. The reason is,
This is because the number of combinations of all gates having different gate sizes and gate lengths between gates is enormous, and it is difficult to create and measure a ring oscillator for each of them.

On the other hand, the delay equation of Elmore or Bacogul can be used for general purposes. However, the delay is slightly different from the delay in the semiconductor device actually designed and manufactured because it is purely theoretical. The reason is that a step pulse is assumed as an input signal, but in an actual circuit, since an input signal of one circuit is an output signal of another circuit, it cannot be a step pulse. It is. FIG. 26 shows a result of comparing a delay value obtained by a simulation by SPICE with values calculated from Elmore's delay equation and Bacogul's delay equation for an actual semiconductor device. In FIG. 26, the data plotted with black circles is the SPICE simulation result. As can be seen from the figure, a larger value is calculated according to the Elmore delay formula, and a smaller value is calculated according to the Bacogul delay formula, and it can be seen that both values are significantly different from the SPICE simulation results. When the Elmore delay equation is used, the margin becomes too high, so that high integration is difficult. On the other hand, the use of the Bacogul's delay formula eliminates the margin and causes design errors.

Therefore, it is necessary to obtain a delay equation that matches the actual delay with sufficient accuracy. However, at present, no effective method for obtaining such a delay equation has been proposed. Although the idea described in Japanese Patent Application Laid-Open No. 9-128433 may be applied to the determination of the delay equation between gates, it is necessary to assume many delay equations in order to derive a highly accurate delay equation. Yes, the number of circuit simulations becomes enormous, which is extremely difficult.

[0012]

[0013]

Therefore, the object of the present invention is to make the actual delay
It is an object of the present invention to provide a method and an apparatus for optimizing a wiring delay by using a delay equation that matches with high precision .

It is another object of the present invention to provide a method for real delay and
It is an object of the present invention to provide a method and an apparatus for accurately calculating a wiring delay between gates using a delay expression that matches with a sufficient accuracy .

[0016]

[0017]

[0018]

[0019]

[0020]

[0021]

[0022]

[0023]

[0024]

[0025]

[0026]

[0027]

[0028]

[0029]

According to a first aspect of the present invention, there is provided a method for calculating an insertion pitch of an inverter when the wiring is divided by a plurality of inverters in order to minimize a wiring delay. As a delay expression for calculating the delay amount of the wiring, a first term relating to the output resistance and the input capacitance of the gate and a second term relating to the wiring resistance and the wiring capacitance are provided on the right side of the calculation expression of the delay amount. A value β according to a semiconductor manufacturing process for a chip on which the wiring is formed is used as a coefficient of the first term, and a value α in a range of 0.33 to 0.42 is used as a coefficient of the second term. The output resistance and the input capacitance of the minimum size inverter are R _out0 and C _in0 , and the wiring resistance and the wiring capacitance per unit length of the wiring are R _int and C in
_{When int} is used, the insertion pitch of the inverter that gives the minimum delay condition is obtained as (βR _out0 C _in0 / αR _int C _int ) ^1/2 .

According to a second aspect of the present invention, there is provided a calculating apparatus for calculating an insertion pitch of an inverter when the wiring is divided by a plurality of inverters in order to minimize a wiring delay. As the delay expression to be calculated, the right side of the expression for calculating the amount of delay includes a first term relating to the output resistance and the input capacitance of the gate, and a second term relating to the wiring resistance and the wiring capacitance. A delay equation using a value β according to the semiconductor manufacturing process for the chip on which the wiring is formed as the coefficient of the term and using a value α in the range of 0.33 to 0.42 as the coefficient of the second term is stored. delay equation storing section and the output resistance of the minimum size of the inverter R _out0 and the input capacitance C _in0, the wiring resistance per unit length of the wiring R _int and wiring capacitance C _int, input unit for inputting a length l _int of the wiring , The output resistance R _out0 and the input capacitance of the minimum size of the inverter input by the input unit C _in0, the wiring resistance R per unit length of the wiring
a register holding the _int and the wire capacitance C _int , the length l _{int of the} wire, and the data held in the register, and applying the delay formula stored in the delay formula storage unit to obtain a minimum delay condition. , A calculation unit for obtaining the insertion pitch of the inverter as (βR _out0 C _in0 / αR _int C _int ) ^1/2 , a register holding the calculation result of the calculation unit, and outputting the data held in the register. And an output unit.

As β, for example, a value in the range of 0.80 to 0.90 is used.

According to the first and second aspects of the present invention, since a delay minimizing condition for a long wiring is calculated using a delay equation that matches with an actual delay with sufficient accuracy, a highly accurate delay is calculated. Optimization can be realized.

According to a third aspect of the present invention, in a calculation method for calculating a delay amount of a wiring, a first term relating to an output resistance and an input capacitance of a gate, A second term relating to resistance and wiring capacitance, wherein a value β according to a semiconductor manufacturing process for a chip on which the wiring is formed is used as a coefficient of the first term, and a coefficient of the second term is used. Then, the delay amount of the wiring formed on the semiconductor chip is calculated using a delay equation using a value α in the range of 0.33 to 0.42.

A calculation device according to a fourth aspect of the present invention is a device for calculating a delay amount of a wiring between gates, wherein a delay expression for calculating the delay amount of the wiring is provided on the right side of the calculation expression of the delay amount. A first term relating to the output resistance and the input capacitance, and a second term relating to the wiring resistance and the wiring capacitance, wherein the coefficient of the first term depends on a semiconductor manufacturing process for a chip on which the wiring is formed. A delay expression storage unit that stores a delay expression using a value α in the range of 0.33 to 0.42 as a coefficient of the second term, an output resistance R _gout and an input capacitance C _{gin of the} gate. , A wiring resistance R _int and a wiring capacitance C per unit length of the wiring.
_int , an input for inputting the length L _{int of the} wiring, and an output resistance R _{gout of the} inverter input by the input.
And the input capacitance C _gin , the wiring resistance R _int and the wiring capacitance C _int per unit length of the wiring, and the length L of the wiring
a register that holds an _int , a calculation unit that inputs data held in the register, and applies a delay expression stored in the delay expression storage unit to obtain a delay amount of the wiring; It includes a register for holding a result, and an output unit for outputting data held in the register.

As β, for example, a value in the range of 0.80 to 0.90 is used.

In the third and fourth aspects of the present invention, since the delay amount of the wiring between gates is calculated using a delay equation that matches the actual delay with sufficient accuracy, a highly accurate delay calculation is performed. It becomes possible.

[0037]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, an embodiment of the present invention will be described in detail. Prior to that, the basic concept of the present invention will be described.

Now, consider a delay equation model such as the following equation in which the coefficients of each term in the Elmore and Bacogul delay equations are a, b, c, and d. _{T d = R gout (aC int} L int + bC gin) + R int L int (cC int L int + dC gin) ... (3)

Here, the coefficients a, b, c and d are given by a = b =
The case of d = 1 and c = 0.5 is Elmore's delay equation, and a
= B = d = 0.7, c = 0.4 is the Bacogul delay equation.

On the other hand, assuming that a ring oscillator in which odd-numbered n _rp inverters are connected in series in a loop with a length L _int interposed therebetween is formed, the delay T _d-1 per stage is , Using the delay model of (3) above,
It is calculated as follows:

[0041] _{T d-1 = (R out0} -inv / h rp) (aC int L int + bh rp C in0-inv) + R int L int (cC int L int + dh rp C in0-inv) ... (4)

Here, h _rp is the enlargement ratio of the inverter with respect to the minimum size inverter, and NM which constitutes the inverter
OS transistor gate width / gate length ratio (W _g / L
_g ) is almost synonymous. The minimum size inverter is an inverter including an NMOS transistor having a gate width / gate length ratio of 1 and a PMOS transistor having a gate width / gate length ratio set to have the same output resistance. R _{ou t0-inv} is the output resistance of the minimum size inverter, C _in0-inv is the input capacitance of the minimum size inverter.

[0043] Measurement of the oscillation frequency f _c of the ring oscillator, the delay T _d-1 per stage is calculated as follows.

T_d-1 = 1 / 2f_c n_rp  … (5)

R _{out0 -inv} and C _{in0 -inv} are determined almost constant depending on the type of the semiconductor manufacturing process. Therefore, at least four types of ring oscillators created by changing the wiring resistance per unit length, the wiring capacitance R _int , the C _int , or changing the wiring length L _int or the inverter expansion rate h _rp , have the oscillation frequencies of at least four types. Is measured, at least four types of the following equations independent of each other can be obtained from the equations (4) and (5).

[0046] _{A i a + B i b +} C i c + D i d = T i ( although, i = 1,2, ..., 4 or more) ... (6)

Here, the wiring resistance R per unit length_int 
Can change wiring width, wiring thickness, resistivity of wiring material, etc.
Can be changed. Wiring per unit length
Capacity C _int Is the wiring width, wiring thickness, wiring interval, interlayer film
Thickness, top and bottom wiring shape (top and bottom wiring is surface wiring, line wiring
Wiring, parallel wiring, orthogonal wiring, or the wiring
Line width, wiring pitch, etc.), ratio between layers
It can be changed by changing the dielectric constant or the like.

Therefore, the values of the coefficients a, b, c, and d can be obtained by solving the above quaternary linear simultaneous equations. By substituting the values into the equation (3), the delay amount between the gates can be derived. The following delay equation is obtained. The above is the premise of the present invention.

By the way, as described above, the four coefficients a,
If a delay model using b, c, and d is prepared, at least 4
It requires time and effort to form various types of ring oscillators and measure their respective oscillation frequencies, which is not very efficient. Therefore, the present inventor has repeatedly studied and found out that even a delay type model using a smaller number of coefficients matches the actual delay with sufficient accuracy as follows.

First, when the four coefficients a, b, c, and d are ordered according to the degree of influence of their values on delay,
It looks like this: (Effect of a)> (Effect of c)> (Effect of b)> (Effect of d) (7) That is, the influence of the coefficient a is the largest, the coefficient c is the next, and the coefficient b is the next. It is large and the influence of the coefficient d is the smallest.

Therefore, the present inventor sets the coefficient d having the least influence to the same value as the coefficient a, that is, by setting d = a in the above equation (3), the number of coefficients a, b, and c becomes 3 A single delay model was assumed. And R _int , C _int
The operation of measuring the oscillation frequencies of at least three types of ring oscillators created by changing the above, solving the ternary linear simultaneous equations, and obtaining the values of the coefficients a, b, and c was repeated for many samples. Note that L _int was 200 μm or more.

FIGS. 14 to 16 show the distribution of the values of the variables a, b, and c obtained for each sample, and the values of the variables on the horizontal axis.
The frequency is plotted on the vertical axis, and the normal distribution and the average value are shown together.

Next, the present inventor has determined that the average value a _av of the variable a in the distribution chart of FIG. 14 and the variable b in the distribution chart of FIG.
Note that the average value b _av is very similar with a _av = 0.8315 and b _av = 0.8418, and two coefficients (a
And c) the validity of the delay model. That is, in the above equation (3), it is determined whether or not a delay equation that matches with an actual delay with sufficient accuracy can be derived by the delay equation model where a = b = d.

First, the operation of measuring the oscillation frequency of at least two types of ring oscillators created by changing R _int , C _int, etc., solving the two-dimensional linear simultaneous equation, and obtaining the values of the coefficients a and c is described below. Was repeated for a number of samples. Note that L _int was 200 μm or more. 17 and 18 show the distribution of the values of the variables a and c obtained for each sample, the values of the variables on the horizontal axis, and the frequencies on the vertical axis. Average values are shown. As can be seen from FIGS. 17 and 18, each variable a,
The distribution of the value of c is calm and converges within a certain range.

Next, for some samples, the values of the variables a and c derived from the samples are substituted into the above equation (3) to generate a delay equation, and the delay calculated by the delay equation and the actual delay equation are calculated. We examined how much error there was with the delay.
19 to 21 are graphs showing the results.
In the figure, the solid line portions are the delays obtained by the delay equation, and the data plotted with black circles are the SPICE simulation results. In FIG. 19 based on the delay equation of a = 0.84 and b = 0.37, r = 9.999758e-01, a = 0.83, b = 0.
In FIG. 20 based on the delay equation of 38, r = 9.999636e-01, a = 0.
In FIG. 21 with the delay equation of 82, b = 0.40, r = 9.997181e-
A very good correlation coefficient of 01 was obtained, and it was confirmed that a delay equation that coincides with the actual delay with sufficient accuracy could be derived. In any case, 0.1 as a semiconductor manufacturing process.
Using the 8 μm generation, coefficients a and c were extracted with L _int = 2 mm and 4 mm. The gate width / gate length ratio (W _g / L _g ) of the NMOS transistor constituting the inverter was 5 in FIG. 19, 17 in FIG. 20, and 30 in FIG. In addition, in order to show the superiority of the present invention, the results obtained by the Elmore and Bacogul delay formulas are also shown in FIG.
9 to 21.

As described above, in the equation (3), a = b = d
As a result, even if a delay expression model using two coefficients a and c is used, a delay expression that matches the actual delay with sufficient accuracy can be derived. In view of this point, in an embodiment of the present invention to be described later, a delay equation used for calculating an inter-gate delay is derived using a delay equation model using two coefficients a and c.

Next, the concept of deriving the delay equation more simply will be described. FIG. 22 shows part of the experimental results obtained by repeating the work of measuring the oscillation frequencies of at least two types of ring oscillators, solving the binary simultaneous linear equations, and calculating the values of the coefficients a and c for a large number of samples. Is shown.
In FIG. 22, one row shows the experimental result of one sample, and the process is the type of the semiconductor manufacturing process, W _g
/ L _g is the gate width / gate length ratio of the NMOS transistor constituting the inverter, f _g is the number of gate fan-outs,
The correlation coefficient indicates the correlation coefficient with respect to the result of the SPICE simulation of the delay by the delay equation using the values of the coefficients a and c in the same bank. In the semiconductor manufacturing process,
0.18um improvement process is the same as 0.18um prototype process 0.18um
This is a process of the next generation, but a process in which the drive capability of the transistor is improved by making some improvements. Also,
23 and 24, the vertical axis represents the coefficient value, and the horizontal axis represents W _g / L.
taking _g, respectively, a diagram coefficients a, graph of the characteristic of the coefficient c in the experimental results in FIG. 22.

As can be seen from the experimental results, the value of the coefficient c does not depend much on the type of the semiconductor manufacturing process, and is substantially within the range of 0.33 to 0.42 (8). This means that even if the type of process is changed, the value of the coefficient c may be fixed to an arbitrary value (for example, an average value) within the above range.
If the value of the coefficient c is fixed, the value of the remaining coefficient a can be determined by forming at least one ring oscillator, and the delay equation can be derived more efficiently. Focusing on this point, another embodiment of the present invention described later uses a delay expression model in which a = b = d and the coefficient a is a fixed value in the delay expression model of the expression (3). A delay equation used for calculating the gate-to-gate delay is derived.

Referring to FIG. 22, the value of the coefficient a substantially converges in the following range when viewed in process units. 0.18um generation prototype process 0.83 ~ 0.87 Improvement process 0.80 ~ 0.85 0.13um generation prototype process 0.86 ~ 0.90… (9)

This means that once the coefficient a is extracted on the premise of a certain process, not only the coefficient c but also the coefficient a may be fixed unless the process is changed. On the other hand, if the process is improved even in the same generation, the coefficient a
Tend to shift in the smaller direction. That is,
The improvement process of the 0.18um generation is compared to the prototype process,
On average it has decreased by about 0.25. Therefore, in the improvement process of the 0.13 um generation, the value of the coefficient a is considered to decrease by substantially the same amount as in the prototype process, and to fall within the range of 0.83 to 0.88. However, since it is not possible to accurately predict how small the value actually becomes, when the process is changed, it is necessary to recalculate the value of the coefficient a according to the process after the change.

The above is the basic principle of the present invention.

The above equation (4) is fundamental as an equation for calculating the delay per stage of the ring oscillator.
Various corrections can be made as shown in the following (a) to (c).

(A) First, the following correction can be made in consideration of the parasitic capacitance in the input capacitance of the inverter. _{T d-para-1 = (} R out0-inv / h rp) (aC int L int + bh rp C in1-inv) + R int L int (cC int L int + dh rp C in2-inv) ... (10)

C_in1-inv And C_in2-inv Is the parasitic capacitance
Is the input capacity of the inverter when_in1-inv 
Is a term related to the output resistance of the inverter, C
_in2-invIs a term related to wiring resistance. Each is next
It is represented as C_in1-inv = C_in0-inv + 5C_frg0-inv + C_ds0-inv ... (11) C_in2-inv = C_in0-inv + 3C_frg0-inv  … (12)

Here, C _frg0-inv is the gate fringe capacitance of the minimum size inverter. The fringe capacitance is a coupling capacitance between the gate and the source or the drain, and indicates the sum of the fringe capacitances of the NMOS and the PMOS. C _ds0-inv is the drain-substrate capacitance of the minimum-size inverter, and indicates the sum of the drain-substrate capacitance of each of the NMOS and the PMOS.

(B) The following correction can be made in consideration of the gate fan-out. _{T d-fg-1 = (} R out0-inv / h rp) f g (aC int L int + bh rp C in0-inv) + R int L int (cC int L int + dh rp C in0-inv) ... (13)

Here, f _g is a gate fan-out. Since the equation (13) is a delay when f _g lines of the length L _int are connected to one inverter output, the ring oscillator also needs to be designed in such a manner. However, it is sufficient if f _g wirings and the inverter are connected only to the inverter output forming the main ring.
No additional wiring or inverters need to be connected to the branch inverter.

(C) Parasitic capacitance can be further considered in the delay equation in consideration of the gate fan-out in equation (13). _{T d-fg-para-1} = R out0-inv b (2C frg0-inv + C ds0-inv) + (R out0-inv / h rp) f g (aC int L int + bh rp C in2-inv) + R int _{L int (cC int L int +} dh rp C in2-inv) ... (14)

The first and second terms of the equation (14) are related to the output resistance of the inverter, and the third term is related to the input capacitance of the inverter.

It is to be noted that a delay equation as shown in the following equation, in which the coefficient of the first term related to the parasitic capacitance is set to another coefficient e, is also conceivable. And sufficient accuracy can be obtained. _{T d-fg-para2-1 = R} out0-inv e (2C frg0-inv + C ds0-inv) + (R out0-inv / h rp) f g (aC int L int + ah rp C in2-inv) + R int _{L int (cC int L int +} ah rp C in2-inv) ... (15)

Expressions (4), (10),
Any of (13) and (14) may be selected, but it is important that once the delay equation is determined, the measured data is analyzed based on the delay equation, and the coefficients a and c (when c is fixed, a) is determined.

Next, an embodiment of the present invention will be described in detail with reference to the drawings.

[First Embodiment] In the present embodiment,
In the above equation (3), the following delay equation model where a = b = d is used. _{T d = R gout (aC int} L int + aC gin) + R int L int (cC int L int + aC gin) ... (16)

By rearranging equation (16) for coefficients a and c, the following can be written. _{T d = a {R gout (} C int L int + C gin) + R int L int C gin} + cR int C int L int 2 ... (16 ') where the first term on the right is the output resistance and the input capacitance of the gate And the second term relates to the wiring resistance and the wiring capacitance.

As an equation for calculating the delay per one stage of the ring oscillator, the following equation where a = b = d in the above equation (4) is used. _{T d-1 = (R out0} -inv / h rp) (aC int L int + ah rp C in0-inv) + R int L int (cC int L int + ah rp C in0-inv) ... (17)

By rearranging equation (17) for coefficients a and c, the following can be written. _{T d-1 = a {(} R out0-inv / h rp) (C int L int + h rp C in0-inv) + R int L int h rp C in0-inv} + cR int C int L int 2 ... (17 ' )

Of course, instead of equation (17), equation (1)
Any of the following equations where a = b = d in (0), (13), and (14) may be used. _{T d-para-1 = (} R out0-inv / h rp) (aC int L int + ah rp C in1-inv) + R int L int (cC int L int + ah rp C in2-inv) ... (18) T d _{-fg-1 = (R out0-} inv / h rp) f g (aC int L int + ah rp C in0-inv) + R int L int (cC int L int + ah rp C in0-inv) ... (19) T d _{-fg-para-1 = R out0} -inv a (2C frg0-inv + C ds0-inv) + (R out0-inv / h rp) f g (aC int L int + ah rp C in2-inv) + R int L int _{(cC int L int + ah rp} C in2-inv) ... (20)

By rearranging the equations (18), (19), and (20) for the coefficients a and c, the following can be written. _{T d-para-1 = a} {(R out0-inv / h rp) (C int L int + h rp C in1-inv) + R int L int h rp C in2-inv)} + cR int C int L int 2 ... _{(18 ') T d-fg} -1 = a {(R out0-inv / h rp) f g (C int L int + h rp C in0-inv) + R int L int h rp C in0-inv)} + cR int ^{_{C int L int 2 ... (19}} ') T d-fg-para-1 = a {R out0-inv (2C frg0-inv + C ds0-inv + f g C in2-inv) + (R out0-inv / h rp _{) f g C int L int +} R int L int h rp C in2-inv)} + cR int C int L int 2 ... (20 ')

In the equation (17), R _out0-inv , C
_in0-inv is almost constant depending on the type of the semiconductor manufacturing process. Therefore, at least two types of ring oscillators created by changing R _int , C _int , or L _int or h _rp by changing the wiring width, the wiring film thickness, the interlayer film thickness, etc. If the frequency is measured, (1
From equations (6) and (17), at least two types of the following independent equations are obtained.

A _i a + C _i c = T _i (where i = 1, 2 or more) (21)

By solving the binary linear equations, the values of the coefficients a and c can be obtained. By substituting the values into the equation (16), a delay equation for deriving the delay amount between the gates can be obtained.

FIG. 1 shows a pattern of a ring oscillator used in the present embodiment. Since the coefficients are two, a and c,
At least two different ring oscillator patterns 1,
2 may be formed on a part of the LSI chip. The first ring oscillator pattern 1 is composed of an odd number of n _rp1 stages of inverters 101, 102,...
Wiring between inverters 110, 120, ..., 130, 140
The length 13 is L _int1 , and the wiring resistance 14 and the wiring capacitance 15 per unit length of the wiring between the inverters are R _int1 and C _int1 . The second ring oscillator pattern 2 has an odd number of n
_rp2 stage inverters 201, 202, ..., 203, 20
4 and wirings 210, 220,
, 230, 240 are L _int2 , wiring resistance 24 and wiring capacitance 25 per unit length of wiring between inverters.
_Are R _int2 and C _int2 .

The parameters for making the ring oscillator pattern different include the wiring length L _int between the inverters, the enlargement ratio h _{rp of} the inverter, and the output resistance R of the inverter.
_out0-inv, input capacitance C _in0-inv of the inverter, per unit length wiring resistance R _int, per unit length wiring capacitance C
_int , there are six. At least two ring oscillators having these values changed are prepared, and as shown schematically in FIG. 1, the oscilloscope 10 uses the oscilloscope 10 to set the period 11 of the first ring oscillator pattern 1 to _Tc1 or the oscillation frequency 1
A 2 f _c1 a (= 1 / T _c1) is measured to measure the _{f c2 (= 1 / T c2} ) also is a T _c2 or oscillating frequency 22 is a second cycle 21 of the ring oscillator pattern 2.

Although the example in which the ring oscillator is formed by using the inverter has been described above, a circuit having the same function as the ring oscillator may be used. For example, a ring oscillator is formed by a circuit in which a two-input one-output NAND is used instead of an inverter, and one input is always connected to a control terminal, and only when the control terminal is on, functions as an inverter. Is also good. In this case, a slight change occurs in the output resistance and the input capacitance of the circuit having the same function as the inverter, but they can be easily calculated.

However, the two ring oscillator patterns 1 and 2 need to be such patterns that the two-dimensional linear simultaneous equations can be linearly independent when arranged as shown in the equation (21). The condition that the two-dimensional linear simultaneous equations are linearly independent is that when the pattern is changed to obtain the two-dimensional linear simultaneous equations of the equation (21), A ₁ C ₂ −A ₂ C ₁ ≠ 0 (22) It should just be. Specifically, as a parameter, L
_{int, h rp, R out0-} i nv, C in0-inv, R int, C int
The pattern may be changed so that at least one of the six parameters has two values.

It is necessary to consider the number of stages of the ring oscillator. First, it must be odd. Otherwise, oscillation does not occur and the delay cannot be measured. On the other hand, if the number of stages is too small, the oscillation frequency becomes too high, and measurement becomes impossible.

The minimum number of stages necessary for the oscillation frequency of the ring oscillator to be measurable is assuming that the values of a and c are Bacogul's delay expressions, and that R _int , C _int
May be determined as follows using a value obtained from a desk calculation or the like. The maximum measurable frequency is f
_{If c-crit} , the smallest odd number should be selected from n _rp that satisfies the following equation (23). n _rp ≧ 1 / ( _{2fc −crit} T _d−1 ) = 1 / [ _{2fc− crit} ｛(R _out0−inv / h _rp ) (aC _int L _int + bh _rp C _in0−inv ) + R _int L _int ( _{cC int L int + dh rp C} in0-inv)}] ... (23) where, a = b = d = 0.7 , c = 0.4

In order to further ensure the measurement, the value may be determined as an odd value sufficiently larger than n _rp thus calculated. This is because the larger the value of n _rp , the smaller the oscillation frequency of the ring oscillator, and the easier it is to measure. However, as the value of n _rp increases, the pattern of the ring oscillator increases, and it is necessary to increase the area accordingly.

Next, in order to obtain a more accurate delay equation, the wiring resistance R _int and the wiring capacitance C per unit length are calculated.
It is also important to form a wiring pattern for evaluating _int on the same chip as the ring oscillator.
This is because the values of the wiring resistance and the wiring capacitance are easily affected by variations in processing dimensions. By forming the wiring pattern on the same chip as the ring oscillator and extracting the wiring resistance R _int and the wiring capacitance C _int from the pattern, it is possible to further enhance the accuracy of the delay expression extraction.

As a wiring pattern for measuring the wiring resistance R _int and the wiring capacitance C _int per unit length, first, a wiring cross-sectional shape evaluation pattern can be considered. The actual wiring shape can be known from the wiring cross-sectional shape evaluation pattern, and the values of R _int and C _int can be derived by manual calculation or simulation. In the method using the wiring cross-sectional shape evaluation pattern, the values of R _int and C _int are obtained indirectly, but the area occupied by the evaluation pattern can be kept small.

As a wiring pattern for measuring the wiring resistance R _int and the wiring capacitance C _int per unit length, in addition to the above, an evaluation pattern for measuring the actual wiring resistance and the wiring capacitance can be considered. However, there is a demerit that the wiring capacitance measurement pattern occupies a considerable area in order to obtain a wiring length that can be actually measured.

In order to obtain a more accurate delay equation, SP
It is also important to form a transistor characteristic measurement pattern for extracting ICE parameters on the same chip as the ring oscillator. Both the SPICE parameter extraction pattern and the wiring characteristic evaluation pattern may be formed on the same chip as the ring oscillator. FIG. 2 shows a plan view of such an LSI chip.

In the LSI chip of the example shown in FIG. 2, during the process of forming the actual semiconductor integrated circuit 53 on the chip, the ring oscillator pattern group 50 is simultaneously formed.
, A wiring characteristic evaluation pattern 51, and a SPICE parameter extraction pattern 52.

[Example of the First Embodiment] FIG. 3 shows an example of the ring oscillator pattern. These two ring oscillator patterns 61 and 62 differ only in the wiring length between the inverters, and have the same other configuration. That is, the wiring length L _inta between the inverters of the ring oscillator pattern 61 is 1.00E + 04 [um], and the wiring length L _intb between the inverters of the ring oscillator pattern 62 is 5.00.
E + 03 [um]. Also, as other specific numerical values,
For example, when the value shown in FIG. 4 is used, when the oscillation frequency is roughly estimated using, for example, a Bacogul delay equation, 27 MH
Since the maximum frequency measurable by the oscilloscope is about 200 MHz, any pattern can be measured because it is sufficiently smaller than 200 MHz. Therefore, the two ring oscillator patterns 61 and 6
2 is formed on the same LSI chip and its oscillation frequency is measured, at least two types of independent equations are obtained from the above equations (16) and (17), and the coefficients a and c can be obtained. .

An amplifier is used for measuring the oscillation frequency of a general ring oscillator. This is used to suppress the influence of the parasitic capacitance of the terminal pad. 1 and 3
In FIG. 5, the amplifier part is omitted for simplicity.
As shown in (2), an amplifier may be appropriately inserted for measurement.
In the present invention, the oscillation frequency (or oscillation cycle) of the ring oscillator is important, and the amplitude and the like are not measured. Therefore, little special is required for amplifier design. The enlargement ratio h _amp1 of the first inverter 81 in the amplifier is kept small so as not to affect the frequency measurement of the ring oscillator, and the second inverter 82, the third inverter 83, and the fourth Inverter 84 and its expansion rate _hamp2 , _hamp3 , _hamp4
May be gradually increased, and the operation may be completed when the inverter has a driving capability that can ignore the parasitic capacitance of the terminal pad 89. As an enlargement ratio of each inverter in the amplifier, for example, an enlargement ratio h _rp of the inverter in the ring oscillator
_{Let hamp1} = 10, _hamp2 = 30, _hamp3
= 90, _hamp4 = 270, measurement can be performed without any problem.

It is preferable that the output resistance of the NMOS transistor and the output resistance of the PMOS transistor are as close as possible in terms of the accuracy of extraction of the delay equation. However, if their values are different, the average value of the output resistances of both transistors may be used. For example, NMOS transistor: W _g / L _g = 30, R _out-n = 680 Ω (24) PMOS transistor: W _g / L _g = 70, R _out-p = 720 Ω (25) If _Rout0-inv = {(680 + 720) / 2} × 30 = 21000Ω (26), the calculation may proceed. However, in this case, the NMOS and PMOS of the inverter constituting the ring oscillator
Of the gate width / gate length ratio (W _g / L _g ) are all 3:
7 is assumed.

FIG. 6 shows an example of a wiring cross-sectional shape evaluation pattern group 55 formed on the same chip as the ring oscillator pattern group 50. The length 56 of each of the cross-sectional structure observation wirings 54 in the pattern group 55 may be long enough to produce a SEM observation sample, for example, about 3 mm.
As the cross-sectional structure observation wiring 54, the same types of wiring as those used in the ring oscillator pattern group 50 are formed, and a plurality of wirings are formed for each type just in case. The values of R _int and C _int can be easily derived from the actual wiring shape by calculation or simulator.

The wiring cross-sectional shape evaluation pattern group 55
Alternatively, after measuring the oscillation frequency of the ring oscillator, the wiring portion of the ring oscillator may be observed with an SEM, FIB, or the like. This method can more accurately grasp the wiring shape, and is convenient for extracting the delay expression. However, once the ring oscillator is broken, it cannot be measured again, so it is necessary to observe the measurement after measurement.

FIG. 7 shows an example of a wiring characteristic evaluation pattern group formed on the same chip as the ring oscillator pattern group 50. Here, a wiring resistance measuring pattern 57 having terminal pads at both ends and a wiring capacitance measuring pattern 5 are shown.
8 are formed. In addition, the high frequency CV
Known methods such as a measurement method and a QUASI-STATIC CV measurement method can be used.

In the above formula (17) and the like, R
_There are transistor parameters such as _out0-inv and _Cin0-inv , which are usually extracted from SPICE parameters and the like. Therefore, it is also effective to simultaneously form a transistor characteristic measurement pattern for extracting SPICE parameters on the same chip as the ring oscillator pattern.

As another embodiment, a method of extracting a delay equation for each wiring length region in order to increase the accuracy of the delay equation can be considered. FIG. 8 shows an example. In this example, the wiring length area is a short wiring length area 90 having a wiring length L _int-2 or less, an intermediate area 91 from the wiring length L _{int- 2} to the wiring length L _int-3 , and a wiring length L _int-3 or more. The long wiring length area 92 was divided into three parts, and a delay equation was calculated for each of the three parts. That is, for the short wiring length region 90, at least two ring oscillator patterns in which the wiring length between the inverters is L _{int -2} or less are formed, and coefficients a and c are extracted from their oscillation frequencies. Wiring length between inverters is L
_int-2 ~L _int-3 and the lowest two ring oscillators pattern formed by the coefficient a from the oscillation frequency, to extract c, the length of the wiring length between the inverter for wire length region 92 L _int-3 At least two ring oscillator patterns as described above were formed, and coefficients a and c were extracted from their oscillation frequencies. The delay characteristic 97 shown in FIG. 8 indicates a delay based on a delay expression determined by the coefficients a and c extracted in this manner. The delay characteristic 97 is for the case where the inverter enlargement rate is h _rp-a . When the delay equation is extracted for each of the three wiring length regions as described above, the number of ring oscillator patterns required for extraction increases to at least eight, but the accuracy of the model increases accordingly. It is needless to say that the number of divisions of the wiring length region is not limited to three.

In the above embodiment, the gate fan-out f _{g is set} to 1. However, in the present invention, the gate fan-out is set to 2
The above case is also applicable. FIG. 9 shows an example of a ring oscillator pattern when f _g is 2 or more. In the figure, reference numeral 500 denotes a gate fan-out f _g , 501 denotes a wiring length L _int of the main line of the ring oscillator loop, 502
Is the wiring length L _int of the branch line of the ring oscillator loop, 50
Numeral 3 indicates inverters connected to the branch wiring. When the gate fan-out is two or more, it is necessary to design so that the wiring length on the output side of the inverter is the same.

When f _g is 2 or more, there are two methods of extracting the delay equation: a method of extracting the delay equation while keeping f _g constant, and a method of extracting a delay equation that can be used in common even if f _g is different. There are two possibilities. In the former case, two ring oscillator patterns are required for each f _g . In the latter case, f _g is also treated as one of the parameters for making the two equations of equation (21) independent of each other. Therefore, f _g , L _int , h _rp , R
_{out0-inv, C in0-inv} , as least one parameter of the seven parameters R _int, C _int has two or more values, it can create a ring oscillator pattern.

[Second Embodiment] In the present embodiment,
In the above equation (16), the following delay equation model in which c is fixed to α is used. _{T d = R gout (aC int} L int + aC gin) + R int L int (αC int L int + aC gin) ... (27) where, alpha is any value within the range of 0.33 to 0.42.

By rearranging equation (27), the following can be written. T _d = a ｛R _gout (C _int L _int + C _gin ) + R _int L _int C _gin ｝ + αR _int C _int L _int ² (27 ′)

In addition, as an expression for calculating the delay per stage of the ring oscillator, the following expression in which c is the same value as α in the expression (27) in the expression (17) is used. _{T d-1 = (R out0} -inv / h rp) (aC int L int + ah rp C in0-inv) + R int L int (αC int L int + ah rp C in0-inv) ... (28)

By rearranging equation (28), the following can be written. _{T d-1 = a {(} R out0-inv / h rp) (C int L int + h rp C in0-inv) + R int L int h rp C in0-inv} + αR int C int L int 2 ... (28 ' )

Of course, instead of equation (28), equation (1)
8), (19), and (20), any of the expressions in which c has the same value as α in the expression (27) may be used.

In equation (28), R _out0-inv , C
_in0-inv is almost constant depending on the semiconductor manufacturing process. Therefore, if the oscillation frequency of one ring oscillator is measured, the following expression is obtained from Expressions (27) and (28).

A _i a = T _i (where i = 1) (29)

By solving this equation, the value of the coefficient a is obtained. By substituting the value into the equation (27), a delay equation for deriving the amount of delay between gates is obtained.

In this embodiment, since the value of the coefficient c is fixed, the number of ring oscillators formed on the LSI chip may be at least one. This point is different from the above-described first embodiment, and the other configurations can apply the configuration of the first embodiment and the configuration of the example.

[Application Example of the Present Invention] As described above, according to the present invention, the following delay equation is obtained as a delay equation used for calculating a gate-to-gate delay in the design of a semiconductor integrated circuit. _{T d = R gout (βC int} L int + βC gin) + R int L int (αC int L int + βC gin) ... (30) where, alpha is an optionally selected one value from a range of 0.33 to 0.42 is there. Is a certain value arbitrarily selected from the range of 0.80 to 0.90.

In the following, an application example of the delay equation thus determined will be described.

[Application Example 1] In this application example, the delay expression according to the present invention is applied to the calculation of the inverter insertion pitch under the minimum delay condition.

The inverter inserted for the purpose of reducing the delay in a long wiring length is inserted in series in the wiring in a pattern as shown in FIG. On the other hand, the ring oscillator pattern used in the present invention to derive the delay equation was a pattern as shown in FIG. These two patterns are almost the same except that they are looped in the ring oscillator. Therefore, when the delay expression according to the present invention is applied to the delay expression used for calculating the insertion pitch of the inverter required to minimize the wiring delay, highly accurate calculation can be performed. Hereinafter, a method of calculating the insertion pitch of the inverter under the minimum delay condition will be described.

The output resistance of the smallest inverter is represented by R
_out0, And input capacitance C_in0 And the wiring length is l _int , Wiring unit
The resistance and capacitance per length are R_int And C_int , In
The number of inserted barters is n_rpThen, insert the inverter
H (Wiring length between inverters L_{in t} ) Is l_int / N_rpNana
Therefore, the delay equation of Equation (30) according to the present invention is used.
For example, the wiring delay can be calculated as follows. T_d-rpt= N_rp[(R_out0/ H_rp) ｛ΒC_int (l_int/ N_rp) + Βh_rpC_in0 ｝ + R_int (l_int/ N_rp) ｛ΑC_int (l_int/ N_rp) + Βh_rpC_in0 ｝]… (31)

[0118] The value of l that minimizes T _{d-rpt in} equation (31)
_{When int} / n _rp is obtained, it becomes the insertion pitch of the inverter under the minimum delay condition, and is given by the following equation. l _int / n _rp = (βR _out0 C _in0 / αR _int C _int ) ^1/2 (32)

When h _{rp at} which T _d-rpt in the above equation (31) is minimized is obtained, it becomes the size of the inverter under the minimum delay condition, and is given by the following equation. h _rp = (R _out0 C _int / R _int C _in0 ) ^1/2 (33)

If the optimum insertion pitch is determined, the number of inverters to be inserted can be determined from the wiring length. Note that the minimum delay time is given by the following equation. T _d-rpt = a _{rp lint} (34) where a _rp is a delay coefficient and is given by the following equation. a _rp = 2 {β + (αβ) ^1/2 } (R _out0 R _int C _in0 C _int ) ^1/2 (35)

FIG. 11 shows the above-mentioned condition for obtaining the minimum delay condition.
Block of one embodiment of a device (minimum delay condition calculating device)
FIG. In this delay minimum condition calculating device, first,
Whether the input unit 601 is a design data file (not shown)
The wiring length l of the wiring for which the minimum delay condition is to be obtained.
_int , The output resistance R of the smallest inverter_out0, Same
Converter input capacity C_in0 , Resistance per unit length of wiring
R_int And capacity C_intAnd register 6
02 to 606. The delay-type storage unit 607 stores
The delay equation given by equation (31) is stored, and
The arithmetic unit 609 receives data from each of the registers 602 to 606.
Input and use the delay expression stored in the delay expression storage unit 607
To provide the minimum delay condition as described above.
Size h _rpAnd inverter insertion pitch l_int / N
_rpAnd the minimum delay value T_d-rpt Is calculated. This calculated
Inverter size h_rp, Inverter insertion pitch l
_int/ N_rp, The minimum delay value T_d-rpt Is register 6
After being stored in 10 to 612, shown by the output unit 613
Not output to a file or displayed on a display device
You.

When changing the values of α and β in equation (31) stored in the delay type storage unit 607, the operator sets the changed values of α and β in the delay type change unit 60.
8, the delay type changing unit 608 is
The values of α and β in the delay equation stored in 7 are changed as specified.

[Application Example 2] In this application example, a performance-oriented placement and routing (Performance-driven plac) is described.
The delay expression according to the present invention is applied to the calculation of the wiring delay of a net or a path required when performing element and routing.

In general, as shown in the flow chart of FIG. 12, in the design of an LSI, a layout design is performed after a functional design and a logical design, and then an analysis by SPICE and an AWE (Asymptomatic Waveform E) are performed.
The static timing analysis is performed by using a method such as “value”. If the specification is satisfied, the process proceeds to the mask production stage. If the specification is not satisfied, the process returns to the layout design stage and the design is performed again. In layout design, placement processing,
Schematic wiring processing and detailed wiring processing are performed. In performance-oriented placement and routing, timing analysis (timing-driven placement and timing-driven routing) is performed based on the results of higher-level processes in the placement and general routing processes, and routing is performed to discovered nets and paths with severe timing. This is a method of minimizing design regression by providing delay constraints. In order to realize this performance-oriented placement and routing, it is necessary to establish a performance-oriented placement and routing method and to provide a means for estimating wiring delays in nets and paths as accurately as possible. Various techniques have been proposed as performance-oriented placement techniques and performance-oriented wiring techniques. On the other hand, as a means for estimating the wiring delay, Elmore's delay formula is exclusively used. In this application example, a wiring delay of a net or a path required for performance-oriented placement and routing is calculated by a delay expression according to the present invention.

FIG. 13 shows an apparatus (delay calculating apparatus) for calculating wiring delays of nets and paths required for performance-oriented placement and routing.
It is a block diagram of one Example. The delay expression storage unit 707 stores the delay expression according to the present invention represented by the above expression (30). When changing the values of α and β in Expression (30) stored in the delay-type storage unit 707, the operator gives the changed values of α and β to the delay-type changing unit 708. For example, the delay type changing unit 708 changes the values of α and β in the delay type stored in the delay type storage unit 707 as specified.

An input unit 701 is a design data file (not shown).
From the file, etc., the wiring (net
, Path) wiring length L_int And output a signal to its wiring
Output resistance R of the side gate_gout, Input the signal from the wiring
Input capacitance C of the gate _gin Per unit length of wiring
Resistance R_int And capacity C_int Enter each
Are stored in the storage units 702 to 706. The calculation unit 709 calculates
Input data from registers 702 to 706
Using the delay equation stored in the unit 707, the delay of the wiring
T_d Is calculated. This calculated delay value T_d Is a register
After being stored in 710, not shown by the output unit 711
Output to file or display on display.

[0127]

[0128]

[0129]

[0130]

As described above , according to the first and second aspects of the present invention, it is possible to calculate the condition for minimizing the delay in a long wiring by using a delay equation that matches the actual delay with sufficient accuracy. And highly accurate delay optimization can be realized.

Further, according to the third and fourth aspects of the present invention, since the delay amount of the wiring between gates is calculated using the delay equation that matches the actual delay with sufficient accuracy, a highly accurate delay calculation is possible. Becomes

[Brief description of the drawings]

FIG. 1 is a diagram showing an example of a ring oscillator pattern used in the present invention.

FIG. 2 shows a ring oscillator pattern used in the present invention;
FIG. 4 is a plan view of an LSI chip on which a wiring characteristic evaluation pattern and a SPICE parameter extraction pattern are formed at the same time.

FIG. 3 is a diagram showing an example of a ring oscillator pattern used in the present invention.

FIG. 4 is a diagram showing an example of specifications of a ring oscillator pattern.

FIG. 5 is a diagram showing an embodiment of an amplifier formed on an LSI chip for measuring an oscillation frequency of a ring oscillator pattern.

FIG. 6 is a diagram showing one embodiment of a wiring structure observing pattern created on the same LSI chip as the ring oscillator pattern.

FIG. 7 is a diagram showing one embodiment of a wiring characteristic evaluation pattern created on the same LSI chip as the ring oscillator pattern.

FIG. 8 is a diagram illustrating an example of a delay graph when a wiring region is divided and a delay expression is extracted by applying the delay expression extraction method of the present invention.

FIG. 9 is a diagram showing an example of a ring oscillator pattern when the gate fan-out is two or more.

FIG. 10 is a diagram showing a wiring pattern in which an inverter is inserted for the purpose of reducing the delay in the wiring length.

FIG. 11 is a block diagram of an embodiment of a minimum delay condition calculating device.

FIG. 12 is a diagram showing an LSI design flow.

FIG. 13 is a block diagram of one embodiment of a delay calculation device.

FIG. 14 is a diagram showing a distribution of values of a variable a derived from a delay expression model having three types of coefficients (a, b, c).

FIG. 15 is a diagram showing a distribution of values of a variable b derived from a delay expression model having three types of coefficients (a, b, c).

FIG. 16 is a diagram showing a distribution of values of a variable c derived from a delay expression model having three types of coefficients (a, b, c).

FIG. 17 is a diagram illustrating a distribution of values of a variable a derived from a delay expression model having two types of coefficients (a, c).

FIG. 18 is a diagram showing a distribution of values of a variable c derived from a delay expression model having two types of coefficients (a, c).

FIG. 19 shows the difference between the actual delay and the delay calculated by the delay equation of variable a = 0.84 and variable c = 0.37 derived from the delay equation model with two types of coefficients (a, c). 7 is a graph showing whether there is an error.

FIG. 20 shows the difference between the actual delay and the delay calculated by the delay equation of variable a = 0.83 and variable c = 0.38 derived from the delay equation model having two types of coefficients (a, c). 7 is a graph showing whether there is an error.

FIG. 21 shows the difference between the actual delay and the delay calculated by the delay equation of variable a = 0.82 and variable c = 0.40 derived from the delay equation model with two types of coefficients (a, c). 7 is a graph showing whether there is an error.

FIG. 22 is a part of an experimental result obtained by measuring oscillation frequencies of at least two types of ring oscillators, solving a system of two-dimensional linear equations, and obtaining values of coefficients a and c for a large number of samples; FIG.

FIG. 23 is a graph showing the characteristics of the coefficient a in the experimental result of FIG. 22, with the value of the coefficient a on the vertical axis and W _g / L _g on the horizontal axis.

24 is a graph showing the characteristics of the coefficient c in the experimental results of FIG. 22, where the value of the coefficient c is plotted on the vertical axis and W _g / L _g is plotted on the horizontal axis.

FIG. 25 is a diagram illustrating an example of a circuit serving as a premise of the delay model.

FIG. 26 is a diagram illustrating a result of comparing a delay value obtained by SPICE simulation with a value calculated from an Elmore delay equation and a Bacogul delay equation for an actual semiconductor device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... 1st ring oscillator pattern 2 ... 2nd ring oscillator pattern 10 ... oscilloscope 11 ... Period of 1st ring oscillator; T_c1  12: oscillation frequency of the first ring oscillator; f_c1  13 ... between inverters in the first ring oscillator
Wiring length; L_int1  14: Distribution between inverters in the first ring oscillator
Wire resistance per unit of wire; R_int1  15: Distribution between inverters in the first ring oscillator
Wiring capacity per unit of wire; C_int1  16... Inverter in the first ring oscillator
Enlargement ratio for small size inverter; h_rp1 21: period of the second ring oscillator; T_c2  22: oscillation frequency of the second ring oscillator; f_c2  23 ... between inverters in the second ring oscillator
Wiring length; L_int2  24—Distribution between Inverters in Second Ring Oscillator
Wire resistance per unit of wire; R_int2  25: Distribution between inverters in the second ring oscillator
Wiring capacity per unit of wire; C_int2  26 ... The inverter in the second ring oscillator
Enlargement ratio for small size inverter; h_rp2 Reference Signs List 50 ring oscillator pattern group 51 wiring characteristic evaluation pattern 52 SPICE parameter extraction pattern 53 semiconductor integrated circuit 54 cross-sectional structure observation wiring 55 cross-sectional structure observation wiring pattern group 56 cross-sectional structure observation wiring length 57: Wiring resistance measuring pattern 58: Wiring capacitance measuring pattern 61: Wiring length is L_intaFirst phosphorus having parameters of
Oscillator pattern 62 Wiring length is L_intbSecond phosphorus having parameters of
Oscillator pattern 71: wiring resistance per unit length; R_int 72: wiring capacitance per unit length; C_int 73 ... wiring length; L_inta  74: Inverter expansion rate; h_rpa 75 ... wiring length; L_intb  80 ... Amplifier 81 ... Inverter in first stage 82 ... Inverter in second stage 83 ... Inverter in third stage 84 ... Inverter in fourth stage 89 ... Terminal pad 90 ... Short wiring length area 91 ... Intermediate area 92 ... Long wiring length Area 97: Inverter expansion rate is h_rp-aDelay characteristic in the case of 101... The first input of the first ring oscillator
Barter 102... Second input of the first ring oscillator
Barter 103: One from the last stage in the first ring oscillator
The previous inverter 104: the last stage input in the first ring oscillator
Barter 110: the first input of the first ring oscillator
Wiring leading to the output of the inverter 120... The second input of the first ring oscillator
Wiring leading to the output of the inverter 130... From the last stage in the first ring oscillator
Wiring 140 connected to the output of the previous inverter 140... The final stage of the first ring oscillator
Wiring connected to the output of the inverter 201... 1st input in the second ring oscillator
Barter 202... The second input of the second ring oscillator
Barter 203: one from the last stage in the second ring oscillator
Inverter 204 before the last stage of the second ring oscillator
Barter 210... The first input of the second ring oscillator
Wiring leading to the output of the inverter 220... The second input of the second ring oscillator
Wiring leading to the output of the inverter 230... From the last stage in the second ring oscillator
Wiring leading to the output of the previous inverter 240... The final stage of the second ring oscillator
Wiring connected to the output of the barter 500: gate fan-out; f_g Reference numeral 501: wiring length of the main line of the ring oscillator loop 502: wiring length of the branch line of the ring oscillator loop 503: inverter connected to the wiring of the branch line 601: input units 602 to 606, 610 to 612: register 607: delay type storage unit 608 ... Delay expression change unit 609 ... Calculation unit 613 ... Output unit 701 ... Input unit 702-706,710 ... Register 707 ... Delay expression storage unit 708 ... Delay expression change unit 709 ... Calculation unit 711 ... Output unit

Claims (8)

(57) [Claims] 1. A method of calculating an inverter insertion pitch when dividing a wiring by a plurality of inverters in order to minimize a wiring delay amount, wherein a delay amount is calculated as a delay expression for calculating the wiring delay amount. Has a first term relating to the output resistance and the input capacitance of the gate, and a second term relating to the wiring resistance and the wiring capacitance. Using the value β according to the semiconductor manufacturing process for the chip to be formed, using the delay equation using the value α in the range of 0.33 to 0.42 as the coefficient of the second term, the output resistance of the inverter of the minimum size And the input capacitance is R _out0 and C
_in0 , and when the wiring resistance and wiring capacitance per unit length of the wiring are R _int and C _int , the insertion pitch of the inverter that gives the minimum delay condition is (βR _out0 C _in0 / αR _int C _int ) ^1/2 A calculation method characterized by being obtained as 2. A calculation method according to claim 1, wherein the use of a value in the range of 0.80 to 0.90 as the beta. 3. An apparatus for calculating an insertion pitch of an inverter when the wiring is divided by a plurality of inverters in order to minimize a wiring delay amount, wherein the delay amount is calculated as a delay expression for calculating the wiring delay amount. Has a first term relating to the output resistance and the input capacitance of the gate, and a second term relating to the wiring resistance and the wiring capacitance. A delay type storage unit for storing a delay type using a value β according to a semiconductor manufacturing process for a formed chip and using a value α in a range of 0.33 to 0.42 as a coefficient of the second term; And an input unit for inputting the output resistance R _out0 and the input capacitance C _in0 of the inverter, the wiring resistance R _int and the wiring capacitance C _int per unit length of the wiring, and the length l _{int of the} wiring. Was A register for holding serial minimum size of the inverter of the output resistor R _out0 and the input capacitance C _in0, the wiring resistance per unit length of the wiring R _int and wiring capacitance C _int, the length l _int of the wiring, held in the register The input data is input, and the delay formula stored in the delay formula storage unit is applied, and the insertion pitch of the inverter that gives the minimum delay condition is (βR _out0 C _in0 / αR _int C _int ) ^1/2. A calculation device comprising: a calculation unit to be obtained; a register for holding a calculation result of the calculation unit; and an output unit for outputting data held in the register. 4. The computing device according to claim 3, wherein a value in the range of 0.80 to 0.90 is used as said β. 5. A delay expression for calculating a delay amount of a wiring,
The right side of the formula for calculating the amount of delay includes a first term relating to the output resistance and the input capacitance of the gate, and a second term relating to the wiring resistance and the wiring capacitance. The value β according to the semiconductor manufacturing process for the chip on which the wiring is formed is used, and the coefficient of the second term is set to 0.
Using a delay formula with a value α in the range of 33-0.42,
A calculation method for calculating a delay amount of a wiring formed on a semiconductor chip. 6. The calculation method according to claim 5, wherein a value in the range of 0.80 to 0.90 is used as said β. 7. An apparatus for calculating a delay amount of a wiring between gates, wherein a delay expression for calculating the delay amount of the wiring includes, on the right-hand side which is a calculation expression of the delay amount, a fourth expression relating to an output resistance and an input capacitance of the gate. 1 and a second term relating to wiring resistance and wiring capacitance, and using a value β according to a semiconductor manufacturing process for a chip on which the wiring is formed as a coefficient of the first term, A delay type storage unit for storing a delay type using a value α in the range of 0.33 to 0.42 as a coefficient of the second term; an output resistance R _gout and an input capacitance C _{gin of the} gate; An input unit for inputting a wiring resistance R _int and a wiring capacitance C _int , and a length L _{int of the} wiring; and an output resistance R of the inverter input by the input unit.
_gout and an input capacitance C _gin , a wiring resistance R _int and a wiring capacitance C _int per unit length of the wiring, a register holding the wiring length L _int , a register holding the wiring length L _int , and inputting the data held in the register, A calculating unit for applying the delay formula stored in the formula storing unit to obtain the amount of delay of the wiring, a register holding a calculation result of the calculating unit, and an output unit outputting data held in the register A computing device comprising: 8. The calculation device according to claim 7, wherein a value in the range of 0.80 to 0.90 is used as said β.