JP3353715B2 - Semiconductor memory device and method for repairing defective memory cell - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device suitable for a dynamic random access memory and a method for relieving a defective memory cell, and more particularly, to a semiconductor memory device which achieves a high-speed operation and a short design time, and a defect thereof. The present invention relates to a memory cell rescue method.

[0002]

2. Description of the Related Art A dynamic random access memory (DRAM) is used as a large-capacity semiconductor memory device. In a conventional DRAM, a word line and a bit line which are orthogonal to each other, and a plurality of memory cells arranged at a plurality of intersections thereof (hereinafter, referred to as normal memory cells due to a difference from a redundant memory cell described later) are provided. Is provided. Further, a conventional DRAM is provided with a redundant memory cell and a redundant word line connected to the redundant memory cell in order to improve the yield of a product, and when a defective memory cell which is a defective normal memory cell exists, A defective memory cell rescue circuit for selecting a redundant memory cell instead of a defective memory cell is connected to a redundant word line. The defective memory cell rescue circuit includes a defective memory cell non-selection circuit for canceling selection of a defective memory cell and a redundant memory cell selection circuit for selecting a redundant memory cell. Further, the defective memory cell rescue circuit is provided with a fuse or the like, and is connected to an identification circuit for identifying the defective memory cell by a program.

In the conventional semiconductor memory device configured as described above, when the existence of a defective memory cell is recognized by the identification circuit, when the defective memory cell is selected, the defect in the defective memory cell rescue circuit is reduced. The selection is canceled by the memory cell non-selection circuit, and the redundant memory cell is selected by the redundant memory cell selection circuit in place of the defective memory cell.

Therefore, even if a defective memory cell exists in the semiconductor memory device, the redundant memory cell operates instead, thereby improving the product yield.

[0005]

However, in a conventional semiconductor memory device having a defective memory cell rescue circuit, a defective memory cell non-selection circuit and a redundant memory cell selection circuit are provided in the defective memory cell rescue circuit. Therefore, the occupied area is large, and two operations of canceling the selection of the defective memory cell and selecting the redundant memory cell must be performed in order to rescue the defective memory cell. is there.

[0006] Recently, in applications where logic circuits are mixed, the speed of memory and the time required for design (TAT: turn
There is an increasing demand for a reduction in around time, but the conventional configuration requires a long design period due to the complexity of the circuit.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and it is possible to maintain the yield of products, increase the speed of operation, and reduce the time required for design (TAT). It is an object of the present invention to provide a semiconductor memory device and a method for relieving a defective memory thereof.

[0008]

SUMMARY OF THE INVENTION A semiconductor memory device according to the present invention receives a bit line, a plurality of memory cells and two redundant memory cells connected to the bit line, an address signal, and an address signal. An address decode circuit for selecting and operating one of the plurality of memory cells based on a signal, and operating the memory cell when the memory cell selected by the address decode circuit is defective have a, a redundant memory cell control circuit for operating the redundant memory cell while keeping the two redundant
One of the long memory cells has a gate connected to the bit line.
The output signal from the redundant memory cell control circuit is applied to
First field effect transistor, and the first field effect transistor
And a first capacitor connected to the transistor.
The other of the two redundant memory cells is connected to the bit line
Field-effect transistor connected to the gate and grounded
Connected to the second field effect transistor
A second capacitor; and
A connection point between the transistor and the first capacitor and the second connection point.
Connection between the field effect transistor and the second capacitor
The connection points are connected to each other .

In the present invention, the redundant memory cell is operated by the redundant memory cell control circuit while the defective memory cell is operating, and the sum of these output signals is output to the bit line. As a result, even when a defective memory cell is present, the defective memory cell is relieved to operate correctly. At this time, since information as to whether or not the memory cell is defective is not input to the address decode circuit, a circuit for the processing is unnecessary, and the redundant memory cell control circuit is used to cancel the selection of the defective memory cell. No circuit is required. Therefore, simplification of the circuit improves the degree of freedom in layout, and also improves the operation speed.

[0010]

[0011]

[0012] Incidentally, the first level shifter connected between said address decoding circuit and the memory cell, and a second level shifter connected between said redundant memory cell wherein the redundant memory cell control circuit, Can be provided.

A method of relieving a defective memory cell of a semiconductor memory device according to the present invention is directed to a method of repairing a bit line and a bit line connected to the bit line.
A plurality of memory cells and two redundant memory cells.
Wherein one of the two redundant memory cells has the bit
From the redundant memory cell control circuit to the gate connected to the line
First field effect transistor to which the output signal of
And a first field-effect transistor connected to the first field-effect transistor.
And a capacitor of the two redundant memory cells.
The other is connected to the bit line and has a gate grounded.
Two field-effect transistors and this second field-effect transistor.
A second capacitor connected to the transistor.
A first field-effect transistor and the first capacity;
Connection point of the second field-effect transistor and the
A semiconductor in which the connection point of the second capacitor is connected to each other
A method of relieving a defective memory cell of a storage device, the method comprising: receiving an address signal indicating an address of one memory cell selected and operated from the plurality of memory cells; Determining whether the memory cell is defective, and selecting and operating the two redundant memory cells and the memory cell determined to be defective when the memory cell is determined to be defective And the following.

[0014]

In the present invention, even if a memory cell is defective, the defective memory cell and the redundant memory cell are selected and operated without canceling the selection, so that the timing design can be easily performed and the operation can be easily performed. Can be speeded up.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor memory device according to an embodiment of the present invention will be specifically described below with reference to the accompanying drawings. FIG. 1 is a block diagram showing a semiconductor memory device according to a first reference example of the present invention.

[0017] The semiconductor memory device according to the present embodiment includes a plurality of normal memory cells and the word lines and a plurality of bit lines of the plurality of which are connected to these normal memory cells are arranged. FIG. 1 shows one of the normal memory cells 6, one word line 8 and one bit line 11
It is shown. The word line 8 is connected to an address decode circuit 7 for selecting a predetermined normal memory cell based on an address signal input from a plurality of normal memory cells. Note that a level shifter 9 is connected between the normal memory cell 6 and the address decode circuit 7. Further, an address latch circuit 10 for latching an address signal is connected to the address decode circuit 7.

Furthermore, in this reference example, two redundant memory cell 2 is provided with a connection to the same structure as the normal memory cells 6 to the bit line 11. Two redundant memory cells 2
Is connected to the redundant word line 3 at the gate of the field effect transistor. On the redundant word line 3, there is provided a defective memory cell rescue circuit 1 which has a built-in redundant memory cell selection circuit, determines whether the input address signal needs to be relieved, and selects the redundant memory cell 2. It is connected. A level shifter 4 is connected between the redundant memory cell 2 and the defective memory cell rescue circuit 1.
Further, the defective memory cell rescue circuit 1 is connected to an identification circuit 5 provided with a fuse or the like and for identifying the defective memory cell 2 by a program. A redundant memory cell control circuit is composed of the defective memory cell rescue circuit 1 and the identification circuit 5. The signal output from the redundant memory cell 2 is
It is relatively larger than the signal output from the normal memory cell 6 when the normal memory cell 6 is defective.

Next, the operation of the first reference <br/> embodiment configured as described above.

When an address signal is input to the address latch circuit 10, the address latch circuit 10 latches this address signal and outputs it to the address decode circuit 7 and the defective memory cell rescue circuit 1.

The address decode circuit 7 to which the address signal is input selects a normal memory cell based on only the address signal regardless of whether the normal memory cell is good or defective.

On the other hand, the defective memory cell rescue circuit 1 to which the address signal has been input determines whether or not the address signal needs to be relieved in accordance with a program in the identification circuit 5. When the defective memory cell rescue circuit 1 determines that the remedy is necessary, it selects the redundant memory cell 2 and
When it is determined that the repair is not necessary, the selection of the redundant memory cell 2 is not performed.

Therefore, when the defective memory cell rescue circuit 1 determines that the normal memory cell 6 needs to be rescued, the output signal of the redundant memory cell 2 and the output of the defective normal memory cell 6 are output to the bit line 11. The potential of the signal represented by the sum with the signal is output. As described above, the output signal of the redundant memory cell 2 is larger than the output signal of the defective normal memory cell 6. Therefore, the repair rate of the defective normal memory cell 6 is high.

[0024] Thus, in the present embodiment, the defective memory cell in relieving circuit 1, a defective memory cell non-selection circuit not is provided, the normal memory cell to be selected address decode circuit 7 is simplified Is not determined. However, this according to the reference example, the number of the redundant memory cell 2 as compared with the conventional semiconductor memory device is increased, since the redundant memory cell 2 normal memory cell 6 poor are simultaneously selected, a defective memory cell Relief is possible. Therefore,
The problem of timing adjustment which conventionally occurs because the determination of a defective memory cell is fed back to the address decode circuit to control the address decode circuit is solved. For this reason, the margin at the time of design, which has been required along with the timing adjustment, becomes unnecessary, and the operating frequency can be easily improved. Further, the area occupied by the address decode circuit 7 on the integrated circuit (IC) is reduced, and the degree of freedom in layout is improved.

[0025] Incidentally, in the first reference example, although one normal memory cell for every one two redundant memory cell 2 is provided, the number of redundant memory cells may be one. In this case, it is possible to improve the operating frequency while suppressing an increase in the area occupied by the memory cells on the IC, and it is possible to rescue defective memory cells although the rescue rate is reduced.

Next, a description will be given of a second exemplary embodiment of the present invention. In the present embodiment, thereby increasing the number of redundant memory cells without providing a level shifter. FIG. 2 is a block diagram showing a semiconductor memory device according to a second reference example of the present invention. Note that the first reference example and the same components shown in FIG. 1 in a second reference example shown in FIG. 2, a detailed description thereof will be omitted given the same reference numerals.

[0027] In this reference example, the bit line 11 is four redundant memory cells 2 are connected. And the first
The level shifter provided as the internal boost power supply in the reference example is not provided.

[0028] In a second reference example thus configured, the internal boosted power source (level shifter) is not provided, the load on the internal boosted power source is reduced.

If the internal boosted power supply is not provided, the amount of data that can be read from the normal memory cell 6 and the redundant memory cell 2 becomes about 1/2 on the potential side.
The present embodiment, since the redundant memory cell 2 of 2 times the number of the first reference example is provided, the read data amount is sufficiently compensated.

Next, a description will be given of the actual施例of the present invention.
In this embodiment, the capacity of the redundant memory cell is larger than that of the normal memory cell. Figure 3 is a block diagram showing a semiconductor memory device according to the actual施例of the present invention. Note that FIG.
To the same components as those of the first reference example shown in FIG. 1 in it indicates to real施例, detailed description thereof will be omitted given the same reference numerals.

In this embodiment, two redundant memory cells 2 are connected such that respective capacitors are connected in parallel. The redundant word line 3 is connected only to the gate of the transistor forming one of the redundant memory cells 2, and the gate of the transistor forming the other redundant memory cell 2 is grounded.

[0032] In the real施例that has been configured in this manner,
By selecting one redundant memory cell 2 connected to the redundant word line 3, the same effect as when two redundant memory cells 2 are selected can be obtained.

Therefore, in order to obtain the same effect as when two redundant memory cells 2 are selected, the redundant memory selected without increasing the load capacity on the redundant memory cell selection circuit in the defective memory cell rescue circuit 1 Since only the cell capacity is increased, the power consumption in the redundant memory cell selection circuit is reduced.

Note that the number of redundant memory cells is not particularly limited, and can be appropriately selected according to the degree of repairable defects.

[0035]

As described in detail above, according to the present invention,
Since information as to whether or not the memory cell is defective is not input to the address decode circuit, a circuit for the processing is unnecessary, and a circuit for canceling the selection of the defective memory cell is not required in the redundant memory cell control circuit. be able to. As a result, it is possible to simplify the configuration, improve the degree of freedom in layout, and improve the operation speed, while maintaining the product yield. Further, since the timing design can be easily performed, the time required for the design (TAT) can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a semiconductor memory device according to a first reference example of the present invention.

FIG. 2 is a block diagram showing a semiconductor memory device according to a second reference example of the present invention.

3 is a block diagram showing a semiconductor memory device according to the actual施例of the present invention.

[Explanation of symbols]

 1: defective memory cell rescue circuit 2: redundant memory cell 3: redundant word line 4, 9; level shifter 5; identification circuit 6; normal memory cell 7; address decode circuit 8; word line 10; address latch circuit 11;

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G11C 29/00 G11C 11/401 G11C 11/413

Claims (3)

(57) [Claims] 1. A bit line, a plurality of memory cells and two redundant memory cells connected to the bit line, and an address signal received from the plurality of memory cells based on the address signal. An address decode circuit for selecting and operating one memory cell, and a redundant memory cell for operating the redundant memory cell while operating the memory cell when the memory cell selected by the address decode circuit is defective possess a control circuit, wherein the 2
One of the redundant memory cells is connected to the bit line.
The output signal from the redundant memory cell control circuit is applied to the gate.
A first field effect transistor to be applied;
First capacitor connected to a field effect transistor
And the other of the two redundant memory cells is
Second field effect connected to bit line and gate grounded
Transistor and a second field effect transistor.
A second capacitor connected to the first electric field,
A connection point between the effect transistor and the first capacitor;
The second field effect transistor and the second capacitor
A semiconductor memory device, wherein the connection points of the capacitors are connected to each other . 2. A first level shifter connected between the memory cell and the address decode circuit, a second level shifter connected between the redundant memory cell and the redundant memory cell control circuit, 2. The semiconductor memory device according to claim 1, comprising: 3. A bit line and a bit line connected to the bit line.
A plurality of memory cells and two redundant memory cells.
And one of the two redundant memory cells is connected to the bit line
Connected to the gate from the redundant memory cell control circuit.
A first field effect transistor to which an output signal is applied;
A first key connected to the first field effect transistor
And the other of the two redundant memory cells
Is connected to the bit line and the gate is grounded.
A field effect transistor and the second field effect transistor
A second capacitor connected to the
1 field-effect transistor and the first capacitor
A connection point, the second field-effect transistor and the second
Storage where the connection points of the capacitors are connected to each other
A method for relieving a defective memory cell of a device, comprising: receiving an address signal indicating an address of one memory cell selected and operated from the plurality of memory cells; Determining whether or not the memory cell is defective; and selecting and operating the two redundant memory cells and the memory cell determined to be defective when the memory cell is determined to be defective. ,
A method for relieving a defective memory cell of a semiconductor memory device, comprising: