JP3352487B2 - Memory with redundant memory cells - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a redundant memory cell selection circuit for replacing a defective memory cell group in a memory cell group with a redundant memory cell group prepared in advance.

[0002]

2. Description of the Related Art Recently, as the capacity of semiconductor memory devices has increased, the integration and density of memory cell groups have been increasing. For this reason, the memory cell group may be defective in the manufacturing process. By replacing these defective memory cell groups with redundant memory cell groups prepared in advance by a redundant memory cell selection circuit, the device is remedied as a non-defective product. This is an indispensable technology for improving the device yield. Therefore, it is important to design a redundant memory cell selection circuit that has a number of redundant memory cell groups that can efficiently remedy a defective memory cell group in a manufacturing process, in order to improve device yield. Become.

Hereinafter, a redundant memory cell selection circuit according to a conventional example will be described with reference to FIGS. 17 and 18. FIG.

FIG. 17 shows a redundant memory cell selection circuit according to a conventional example. FIG. 18 shows a selection fuse circuit block FB100 in FIG. 17, and selection fuse circuit blocks FB101 to FB115 are selected. Is similar to

In FIG. 17 and FIG.
CB7 is a memory cell block, FB100 to FB115
Is a fuse circuit block for selection, RWL00, RWL0
1, RWL10, RWL11,..., RWL70, RWL
71 is a redundant word line group, A0 to A8, / A0 to //
A8 is an address signal, SPE0, SPE1, R00, R
01, R10, R11, ..., R70, R71, / RA,
N01 is a signal, F00 to F11 are fuses, VCC is a power supply voltage, VSS is a ground voltage, QN00 to QN14 are N-channel MOS transistors, and QP00 is a P-channel MOS transistor.

In a conventional example, a redundant memory cell selection circuit
Replacement of a defective memory cell group among a plurality of memory cell groups formed at intersections of word lines and bit lines formed in a lattice pattern with a redundant memory cell group connected to a redundant word line group and prepared in advance. Is what you do.

[0007] The redundant memory cell selection circuit has eight memory cell blocks MCB0 to MCB7 which are respectively selected by logic voltages of address signals A6 to A8.

For each memory cell block, 2
One redundant word line group is prepared. For example,
RWL20, RWL for the memory cell block MCB2
Two redundant word line groups of WL21 are provided. That is, a total of 16 redundant word line groups are prepared.

In order to select these redundant word line groups, sixteen selection fuse circuit blocks FB100 to FB are selected according to the sixteen redundant word line groups, respectively.
115 are provided. For example, when it is desired to use two redundant word line groups RWL20 and RWL21 of the memory cell block MCB2, the fuses corresponding to the addresses of the defective memory cell groups are cut off in the selection fuse circuit blocks FB104 and FB105, respectively. Normal word line groups are respectively replaced with redundant word line groups, and these redundant word line groups are used.

Hereinafter, the detailed circuit operation of the conventional redundant memory cell selection circuit will be described with reference to FIG. FIG. 18 shows a selection fuse circuit block FB100.
And the selection fuse circuit block FB101
To FB115 are selection fuse circuit blocks FB100
Is similar to

First, the signal / RA becomes a logic voltage "Low" (hereinafter referred to as L), the P-channel MOS transistor QP00 is turned on, and the signal N01 becomes the logic voltage "High".
(Hereinafter referred to as H). After that, the signal / RA becomes the logic voltage "H", and then the address signals A0 to A5, / A0 to / A5, which are all initially at the logic voltage "L".
Changes to the address of the selected defective memory cell group. Here, the address signals / A0 to / A5 are logic voltage signals that are the reverse of the address signals A0 to A5.

The address signals A0 to A5, / A0
~ / A5 are N-channel MOS transistors QN00 to QN00
The signals are input to the gates of QN11, respectively, and six half of the twelve N-channel MOS transistors N00 to QN11 are turned on.

At this time, among the fuses F00 to F11, six fuses corresponding to the address of the selected defective memory cell group are cut, and the memory cell block selection address of the memory cell block MCB0 is selected. In this case, the signal N01 becomes the logic voltage "H" and the signal R00 becomes the logic voltage "L". Then, the signal SPE0 becomes the logic voltage “H”, and the redundant word line group RWL00 is selected by the AND signal of the address signal corresponding to the memory cell block selection address of the memory cell block MCB0 and the signal SPE0.

As described above, in the redundant memory cell selection circuit according to the conventional example, since two redundant word line groups are prepared for each of the eight memory cell blocks,
2 × 8 = 16 selection fuse circuit blocks are required. Then, twelve fuses are required for one selection fuse circuit block, and the total number of fuses is 12 × 16 = 192.

[0015]

However, in the above-described conventional redundant memory cell selecting circuit, a redundant word line group and a selecting fuse circuit block required for each memory cell block are prepared. Therefore, since many redundant word line groups and fuse circuit blocks for selection are required, a large area is required in the layout, and the area of the entire device is increased, and the cost per device is increased. . Also,
By increasing the number of redundant word line groups, that is, the number of redundant memory cell groups, the probability that the redundant memory cell group itself is defective increases, and the defective memory cell group is replaced with the redundant memory cell group to rescue the device as a non-defective product. There is a problem that the remedy rate by the redundant memory cell group is reduced.

The present invention has been made in view of the above, and has as its object to provide an inexpensive and high-yield redundant memory cell selection circuit that suppresses an increase in chip area.

[0017]

Means for Solving the Problems To achieve the above object,
Therefore, according to the first aspect of the present invention, each of the memos has a predetermined number of units.
Memory cell group having recell and redundant memory cell
Memory that can be switched between groups
Therefore, each has a plurality of memory cell groups and a plurality of
Multiple memory cell blocks having redundant memory cell groups
And a redundant memory having a plurality of fuse circuit blocks.
A recell selection circuit;
Each of the blocks is connected to any one of the memory cell groups.
Of memory cell block to which one memory cell group belongs
A memory cell block selection address indicating an address;
Address in the memory cell block of the memory cell group
Fuse with the selected memory cell group selection address.
The redundant memory cell selection circuit
Address signal indicating the memory cell group to be accessed.
Depending on the signal, one of the fuse circuit blocks
The memory cell block selection address to be stored and
When the memory cell group selection address is selected, the block
Generate the internal selection signal and generate the
To which the memory cell group to be accessed belongs
Cell block designation address signal indicating recell block
And a redundant memory based on the selection signal in the block.
One of the cell groups was configured to be selected
It is characterized by the following.

Further, the invention of claim 2 is based on the memo of claim 1.
And the fuse circuit block includes a plurality of fuse circuit blocks.
One less than the total number of redundant memory cell groups
Is provided.

Further, the invention of claim 3 is the invention of claim 1 or
3. The memory of claim 2, wherein said fuse circuit block
Is what is in each of the above memory cell blocks.
Corresponding to one of the redundant memory cell group sets.
It is characterized by being provided.

Further, the invention of claim 4 is the invention of claim 1 or
3. The memory of claim 2, wherein said fuse circuit block
Is at least one of the memory cell blocks.
Any one of the above redundant memory cells within a lock
Feature additional fuses to select
Sign.

[0021] The invention of claim 5 is based on claim 1 or
3. The memory of claim 2, further comprising: connecting and disconnecting a fuse.
The cell block designation address signal
With an address translation circuit that translates
What is the memory cell block to which the memory cell group belongs?
The above redundant memory cells belonging to different memory cell blocks
Note that groups are configured to be selectable.
Sign.

[0022] Further , the invention of claim 6 is based on the memo of claim 5.
Wherein the address conversion circuit is configured to disconnect and connect a fuse.
The value of each bit of the address before and after the conversion
Address signal is changed by setting the presence or absence of
Characterized in that it is configured to conversion to so that.

[0023] The invention of claim 7 is based on claim 1 or
3. The memory of claim 2, further comprising:
Redundant memory cell block having substantially the same configuration as lock
Lock, the memory cell block and the redundant memory cell.
Memory block selection circuit for switching between memory blocks
It is characterized by having.

The invention according to claim 8 is based on the memo of claim 7.
And the connection of the fuse causes the memory cell
The memory cell switched by the block selection circuit
Equivalent potential of bit line and word line in block
It is characterized in that it is configured to be able to set the position.

[0025] Further , the invention of claim 9 provides the following.
A memory cell group having a unit number of memory cells,
It is configured to be able to switch between long memory cell groups.
Memory, each having a plurality of memory cell groups.
And multiple with multiple redundant memory cell groups
Memory cell block and fuse setting
Depending on the number of the redundant memory cell groups,
Fuse circuit block configured to select one
And the fuse circuit block locks the setting.
Fuse for canceling and the above cancellation was not made
Logic circuit that outputs a signal of a predetermined level when
It is further characterized by being provided.

Further, the invention of claim 10 is a
Number of memory cell groups and redundant memory cell groups
And memory cell blocks of multiple having a fuse circuit Bed
And the fuse circuit block includes a lock.
Of memory cell groups, one memory cell group
Memory cell group indicating the address in the memory cell block
The loop selection address and the one memory cell group are
Memory cell indicating the address of the memory cell block to which it belongs
Block selection address, and the fuse circuit
The total number of path blocks is
It is characterized in that it is smaller than the total number.

[0027]

According to the first or second aspect of the present invention, the fuel tank is provided.
Circuit block is a cell block designating address signal.
And the cell group designation address signal,
A select signal in a block indicating the selection of a memory cell group
Output, so that each redundant memory cell group
Do not make the fuse circuit block correspond 1: 1.
In addition, any of the redundant memory cell groups can be selected.
Wear. Therefore, it is larger than the total number of redundant memory cell groups.
By providing a small number of fuse circuit blocks, multiple
Redundant memory cell groups across memory cell blocks
Select multiple redundancy in one memory cell block
For example, a memory cell group can be selected. I
Therefore, the defective memory cell due to the redundant memory cell group is
Large lay without reducing the group's rescue rate
Total area of fuse circuit block that requires out area
Can be reduced, thus reducing the area of the entire device.
Can be smaller.

According to the third aspect of the present invention, the fuse circuit block
What is the redundancy memory cell group corresponding to the lock
Redundant memory cell group belonging to the same memory cell block.
You can also select the
With this arrangement, the circuit configuration can be simplified. So
Therefore, the degree of freedom in selecting a redundant memory cell group,
That is, the reduction in the repair rate of the defective memory cell group is suppressed to a small extent.
In addition, the circuit scale can be reduced.

According to the fourth aspect of the present invention, the small
Memory is provided by at least one fuse circuit block.
Multiple redundant memory cell groups in a cell block
You can select any of
Redundant memory cell groups without increasing the circuit scale
The degree of freedom in selecting memory cells to save defective memory cell groups.
Savings rate can be improved.

According to the fifth aspect of the present invention, the fuse circuit block
The lock is a memory cell group of one memory cell block.
Memory cell block other than that memory cell block.
Placed in the redundant memory cell group belonging to one of the locks.
It is possible to exchange. This allows redundant memory cells
Without reducing the freedom of relief
Number of redundant memory cell groups and fuse circuit block
The number of devices and the overall surface area of the device.
The product can be reduced. In addition, redundant memory cells
The remedy rate by the loop can be improved.

According to the sixth aspect of the present invention, one address
Address conversion by providing only one fuse per unit
It can be performed. That is, for example, the converted address
To set whether the value of each bit of the source is “0” or “1”
Requires two fuses for each bit
Address conversion with half the number of fuses
Can greatly increase the circuit size.
Without increasing the repair rate of defective memory cell groups.
Can be up.

According to the seventh aspect of the present invention, a memory having a low defect rate is provided.
Since the molycell block can be used selectively,
While greatly increasing the rescue rate, the fuse circuit
Reduced circuit size by keeping the number of locks low
The effect can be obtained.

According to the eighth aspect of the present invention, a redundant memory cell
The selection circuit is replaced with a second memory cell block.
The bit line and the word line of the first memory cell block
The same potential can be set. As a result, in the manufacturing process
Bit line and word line of memory cell block are short-circuited
If a defect occurs, make a note of the
Replace a recell block with every memory cell block
And the memory cell block in which
To make the potential of the bit line and word line in the
Power supply current abnormality can be relieved more.

According to the ninth aspect of the present invention, the fuse circuit block is provided.
The memory cell group selection address stored in the lock is
Cancellation is possible. As a result, the defective memory cell
Defective redundant memory cell group replaced with loop
Is stored in the fuse circuit block.
Memory cell group corresponding to the defective memory cell group
Selection address is canceled and another fuse circuit block is
Lock the memory cell of the defective memory cell group
By storing the group selection address,
Replace a defective memory cell group with another redundant memory cell group
Can be replaced by Therefore, the redundant memory cell
Can significantly improve the rescue rate of
And the output of the circuit canceled as described above.
Is set to a predetermined level,
It can be reliably prevented.

According to the tenth aspect, the first aspect is provided.
As described above, the redundant memory cell group
To reduce the repair rate of defective memory cell groups due to
Fuses that require a large layout area
Since the total area of road blocks can be reduced,
The area of the entire vise can be reduced.

[0036]

Embodiment (First Embodiment) Hereinafter, a redundant memory cell selection circuit according to a first embodiment of the present invention will be described with reference to FIGS.

FIG. 1 shows a redundant memory cell selection circuit according to the first embodiment, and FIG. 2 shows a selection fuse circuit block FB00 in FIG. 1. Selection fuse circuit blocks FB01 to FB07 are used for selection. This is similar to the fuse circuit block FB00.

In FIGS. 1 and 2, MCB0 to MCB
7 is a memory cell block, FB00 to FB07 are fuse circuit blocks for selection, RWL00, RWL01, RW
L10, RWL11,..., RWL70, RWL71 are redundant word line groups, A0 to A8, / A0 to / A8 are address signals, SPE0, SPE1, R00, R01, R
, R30, R31, / RA, N01 is a signal, F00 to F17 are fuses, VCC is a power supply voltage,
VSS is a ground voltage, QN00 to QN17 are N-channel MOS transistors, and QP00 is a P-channel MOS transistor.

In the first embodiment, the redundant memory cell selection circuit, as in the prior art, has a defective memory cell group among a plurality of memory cell groups formed at intersections of word lines and bit lines formed in a grid. The memory cell group is replaced with a redundant memory cell group which is connected to the redundant word line group and prepared in advance, and is relieved.

The redundant memory cell selection circuit includes eight memory cell blocks MCB0 to MCB7 (hereinafter, referred to as MCB when memory cell blocks are collectively referred to) selected by logic voltages of address signals A6 to A8. . For memory cell blocks MCB0 to MCB7, redundant word line groups RWL00 to RWL71 (hereinafter referred to as RWL when collectively referring to redundant word line groups) are prepared, and one memory cell block includes two redundant word lines. Have a group. For example, for the memory cell block MCB2, two redundant word line groups RW
L20 and RWL21 are provided. That is, as a whole, 16 redundant word line groups RWL are prepared. Then, 16 redundant word line groups RWL
Selection fuse circuit block F for selecting
B00 to FB07 are provided. For example, the first set of redundant word line groups R of the memory cell block MCB2
If it is desired to use WL20 and the second redundant word line group RWL21, select fuse circuit block F
In B00 and FB01, the fuses corresponding to the addresses of the defective memory cell group are cut, respectively. Thus, the normal word line groups are replaced with the redundant word line groups, respectively, and these redundant word line groups are used.

A first set of redundant word line groups RWL00, RWL1 included in one of the memory cell blocks MCB
0, RWL20,..., RWL60 or RWL70, the selection fuse circuit blocks FB00, FB00
One of B02, FB04, and FB06 is used. The second set of redundant word line groups RWL01, RWL11,
When using RWL21,..., RWL61 or RWL71, selecting fuse circuit blocks FB01, FB0
3, FB05 or FB07 is used.

Four selection fuse circuit blocks are prepared for eight first set of redundant word line groups, and four selection fuse circuit blocks are set for eight second set of redundant word line groups. Is prepared.

Usually, a defective memory cell group often occurs in a plurality of word line groups at one place (one memory cell block). It is unlikely that a plurality of word line groups become defective in each of all the memory cell blocks MCB. The number of defects in the word line group is at most eight in the entire device. For this reason, as in the conventional example, 8
Eight selection fuse circuit blocks are prepared for one first set of redundant word line groups, and eight selection fuse circuit blocks are prepared for eight second set of redundant word line groups, that is, There is no need to prepare 16 selection fuse circuit blocks, and the relief by the redundant memory cell group can be achieved only by preparing 8 selection fuse circuit blocks.

As described above, the number of redundant word line groups prepared for each memory cell block is two, which is the same as that of the conventional example, but one redundant word line group that can be used as a whole is one.
It is limited to eight instead of six. As a result, the number of selection fuse circuit blocks is reduced without lowering the rescue rate of the redundant memory cell group in the device.

Hereinafter, a detailed circuit operation of the redundant memory cell selection circuit according to the first embodiment will be described with reference to FIG. FIG. 2 shows a selection fuse circuit block FB00, and the selection fuse circuit blocks FB01 to FB01.
B07 is similar to the selection fuse circuit block FB00.

In FIG. 2, first, signal / RA attains logic voltage "L", and P-channel MOS transistor QP
00 turns on, and the signal N01 becomes the logic voltage “H”. Thereafter, the signal / RA becomes the logic voltage "H", and then the address signals A0 to A0, which are all initially at the logic voltage "L".
A8, / A0 to / A8 change to the address of the selected defective memory cell group. Here, the address signal /
A0 / A8 are logic voltage signals that are the reverse of the address signals A0-A8.

Address signals A0 to A8, / A0 to / A8
Are N-channel MOS transistors QN00 to QN17
, And 18 N-channel type M
Nine of the half of the OS transistors are turned on.

At this time, of the fuses F00 to F11, the six fuses corresponding to the address of the selected defective memory cell group are cut, and the memory cell block selection of the fuses F12 to F17 is performed. If the three fuses corresponding to the address are cut,
The signal N01 becomes the logic voltage "H", and the signal R00 becomes the logic voltage "L". Then, the signal SPE0 becomes a logic voltage "H", and a logical product signal of the signal SPE0 and an address signal corresponding to the memory cell block selection address generates a first set of redundancy of the memory cell block corresponding to the memory cell block selection address. A word line group is selected.

The difference between the first embodiment and the conventional example is that a fuse corresponding to a memory cell block selection address is added to a selection fuse circuit block.

As described above, in the redundant memory cell selection circuit according to the first embodiment, two redundant word line groups are prepared for each of the eight memory cell blocks. Four selection fuse circuit blocks are prepared for each of the two redundant word line groups. That is, 2 × 4 = 8 selection fuse circuit blocks are provided. One fuse circuit block for selection requires 18 fuses, and the total number of fuses is 18 × 8 = 144. This is reduced to 75% of the 192 lines in the conventional example.

A feature of the redundant memory cell selection circuit of the first embodiment is that the number of redundant word line groups is not reduced, that is, the number of redundant memory cell groups is not reduced. Therefore, it is possible to select any one of all the redundant memory cell groups with a smaller number of selection fuse circuit blocks than the number of prepared redundant memory cell groups without substantially lowering the remedy rate by the redundant memory cell groups. It becomes possible. Thus, the total area of the selection fuse circuit block can be reduced.

(Second Embodiment) Hereinafter, a redundant memory cell selection circuit according to a second embodiment of the present invention will be described with reference to FIGS.

FIG. 3 shows the redundant memory cell selection circuit according to the second embodiment, and FIG. 4 shows the selection fuse circuit block FB11 in FIG. 3, and the selection fuse circuit blocks FB13, FB15, FB17 are This is similar to the selection fuse circuit block FB11.

In FIGS. 3 and 4, MCB0 to MCB
7 is a memory cell block, FB00, FB02, FB0
4, FB06, FB11, FB13, FB15, FB1
7 is a fuse circuit block for selection, RWL00, RWL
01, RWL10, RWL11,..., RWL70, RW
L71 is a redundant word line group, A0 to A8, / A0 to
/ A8 is an address signal, SPE0, SPE1, R00,
R01, R10, R11, R20, R21, R30, R
31, R40, R50, R60, R70, AALL, /
RA, N01, N02, N20, N21, N22 are signals, F00 to F17, F20 are fuses, VCC is a power supply voltage, VSS is a ground voltage, QN00 to QN17, QN2.
0 is an N-channel MOS transistor, QP00, QP
Reference numeral 20 denotes a P-channel MOS transistor.

Selection fuse circuit blocks FB00, F
B02, FB04, and FB06 are the same as the fuse circuit blocks for selection of the redundant memory cell selection circuit according to the first embodiment shown in FIG.

In the second embodiment, as in the prior art, the redundant memory cell selection circuit is provided with a defective memory cell among a plurality of memory cell groups formed at intersections of word lines and bit lines arranged in a grid. The memory cell group is replaced with a redundant memory cell group connected to the redundant word line group and prepared in advance, and is relieved.

The redundant memory cell selection circuit includes eight memory cell blocks MCB0 to MCB7 selected by the logic voltages of the address signals A6 to A8. Two redundant word line groups are prepared for each memory cell block. For example, the memory cell block MCB
2, two redundant word line groups RWL20,
An RWL 21 is provided. That is, 1 as a whole
Six redundant word line groups RWL are prepared.
Then, in order to select 16 redundant word line groups RWL, eight selection fuse circuit blocks FB00, FB00,
FB02, FB04, FB06, FB11, FB13,
FB15 and FB17 are provided. For example, two redundant word line groups R of the memory cell block MCB2
When it is desired to use WL20 and RWL21, the fuses corresponding to the addresses of the defective memory cell groups are cut off in the selection fuse circuit blocks FB00 and FB11, whereby the normal word line groups are respectively replaced with the redundant word line groups. These redundant word line groups are used. A first set of redundant word line groups RWL00, RWL10, RWL20,..., RWL of any of the memory cell blocks MCB
60 or RWL 70, the selection fuse circuit blocks FB00, FB02, FB04, FB06,
One of FB11, FB13, FB15 and FB17 is used. Second set of redundant word line groups RWL0 included in any of memory cell blocks MCB
1, RWL11, RWL21,..., RWL61 or R
When the WL71 is used, one of the selection fuse circuit blocks FB11, FB13, FB15, and FB17 is used. All eight fuse circuit blocks for selection can be used to select one first set of redundant word line groups. To select one second set of redundant word line groups, specific four of the eight fuse circuit blocks for selection can be used.

As described in the first embodiment, usually, a defective memory cell group often occurs in a plurality of word line groups at one place. It is unlikely that a plurality of word line groups become defective in each of all the memory cell blocks MCB. Therefore, redundant word line group RW
Even if the total number of selection fuse circuit blocks is smaller than the total number of L, the repair rate by the redundant memory cell group does not decrease.

Further, in the second embodiment, compared with the first embodiment, all eight fuse circuit blocks for selection can be used for selecting each of the first set of redundant word line groups.

Hereinafter, a detailed circuit operation of the redundant memory cell selection circuit according to the second embodiment will be described with reference to FIG. FIG. 4 shows a selection fuse circuit block FB11.
And the fuse circuit block for selection FB13,
FB15 and FB17 are selection fuse circuit blocks FB
It is similar to 11.

In FIG. 4, first, signal / RA attains logic voltage "L", and P-channel MOS transistor QP
00 turns on, and the signal N01 becomes the logic voltage “H”. Thereafter, the signal / RA becomes the logic voltage "H", and then the address signals A0 to A0, which are all initially at the logic voltage "L".
A8, / A0 to / A8 change to the address of the selected defective memory cell group. Here, the address signal /
A0 / A8 are logic voltage signals that are the reverse of the address signals A0-A8.

Address signals A0 to A8, / A0 to / A8
Are N-channel MOS transistors QN00 to QN17
, And 18 N-channel type M
9 of the half of the OS transistors QN00 to QN17
Turns on.

At this time, among the fuses F00 to F11, the six fuses corresponding to the address of the selected defective memory cell group are cut, and the memory cell block selection among the fuses F12 to F17 is selected. If the three fuses corresponding to the address are cut,
The signal N01 becomes the logic voltage "H", and the signal N02 becomes the logic voltage "L".

The circuit for determining which of the first and second redundant word line groups is to be selected is:
First, the signal / RA becomes the logic voltage "L", the P-channel MOS transistor QP20 turns on, and the signal N20 becomes the logic voltage "H". Thereafter, the signal / RA becomes the logic voltage "H", and then the signal AALL which is initially the logic voltage "L" becomes the logic voltage "H". by this,
N-channel MOS transistor QN20 turns on.

At this time, if the fuse F20 is not blown, the signal N20 becomes the logic voltage "L". As a result, the signal N21 becomes the logic voltage “H”, and the signal N22
Becomes the logic voltage “L”, and the signal R01 becomes the logic voltage “L”.
On the other hand, the signal R40 becomes the logic voltage “H”. Therefore, the signal SPE0 becomes the logic voltage “H”, and this signal SPE0
A logical product signal of PE0 and an address signal corresponding to the memory cell block selection address generates the first memory cell block corresponding to the memory cell block selection address.
A set of redundant word line groups is selected.

If the fuse F20 has been blown, the signal N20 remains at the logic voltage "H" and the signal N21
Becomes the logic voltage “L”, and the signal N22 becomes the logic voltage “H”.
Becomes As a result, the signal R01 goes to the logic voltage "H", while the signal R40 goes to the logic voltage "L", and the signal SP
E1 becomes the logic voltage “H”. The AND signal of this signal SPE1 and the address signal corresponding to the memory cell block selection address selects the second set of redundant word line groups of the memory cell block corresponding to the memory cell block selection address.

As described above, in the redundant memory cell selection circuit according to the second embodiment, eight memory cell blocks MC
Two redundant word line groups are prepared for each of B. The redundant memory cell selecting circuit includes four selecting fuse circuit blocks capable of selecting only the first set of redundant word line groups and four selecting fuses capable of selecting any of the first set and the second set of redundant word line groups. And a circuit block. Eighteen fuses are required for one selection fuse circuit block from which only the first set of redundant word line groups can be selected. First set and second
19 fuses are required for one selecting fuse circuit block that can select either redundant word line group of the set. Therefore, the total number of fuses in the redundant memory cell selection circuit is 18 × 4 + 19 × 4 = 148. This is reduced to 77% of the 192 lines in the conventional example.

Here, in each memory cell block,
Assuming that the first redundant word line group to be used must be from the first set of redundant word line groups, the number of selection fuse circuit blocks that can select either the first set or the second set of redundant word line groups Can be less than or equal to the number of selection fuse circuit blocks that can select only the first set of redundant word line groups.

For example, the total number of selection fuse circuit blocks is 24, and the total number of redundant memory cell groups in one memory cell block is 4. When the third set of redundant memory cell groups is selected from among them, the first set and the second set of redundant memory cell groups have already been selected and used, so that the first set in one memory cell block is The number of selection fuse circuit blocks that can select any of the redundant memory cell groups up to the third set is the number of selection fuse circuits that can select any of the first to second redundant memory cell groups in one memory cell block. Less than half the number of blocks is sufficient.

Considering this, the number of selection fuse circuit blocks that can select any of the first to third redundant memory cell groups in one memory cell block is 24 × (4-3 + 1) / 4 = 12 or less is sufficient.

Generally speaking, the total number of selection fuse circuit blocks is L (L is a natural number), and the total number of redundant memory cell groups in one memory cell block is M (M
Is a natural number).
The number of selection fuse circuit blocks that can select any of the redundant memory cell groups from the set to the N-th set (N is a natural number from 2 to M) is not more than L × (M−N + 1) / M.

The feature of the redundant memory cell selection circuit according to the second embodiment is that the number of redundant memory cell groups is not reduced as in the first embodiment. This means that any one of the redundant memory cell groups can be selected by a smaller number of selection fuse circuit blocks than the number of prepared redundant memory cell groups without lowering. Therefore, the total area of the selection fuse circuit block can be reduced. Further, compared to the first embodiment, the first redundant word line group can be selected by using all of the eight fuse circuit blocks for selection, thereby increasing the degree of freedom of relief by the redundant memory cell group. Have been.

(Third Embodiment) A redundant memory cell selection circuit according to a third embodiment of the present invention will be described below with reference to FIGS.

FIG. 5 shows a redundant memory cell selection circuit according to the third embodiment. FIG. 6 shows a selection fuse circuit block FB20 in FIG. 5, and selection fuse circuit blocks FB21 to FB27 are used for selection. FIG. 7 shows an address conversion circuit block ATC61 in FIG. 5, which is the same as the fuse circuit block FB20, and the address conversion circuit blocks ATC71 and ATC81.
Are similar to those of the address conversion circuit block ATC61.

In FIG. 5, FIG. 6 and FIG.
MCB7 is a memory cell block, FB20 to FB27 are fuse circuit blocks for selection, RWL00, RWL1
0,..., RWL70 are redundant word line groups, ATC6
1, ATC71 and ATC81 are address conversion circuit blocks, A0 to A8, / A0 to / A8 are address signals, A6
R, A7R, A8R, / A6R, / A7R, / A8R are internal conversion address signals, SPE0, R00 to R07, I
NVA60 to INVA67, INVA70 to INVA7
7, INVA80-INVA87, INVA6A, IN
VA7A, INVA8A, / RA, AALL, N01,
N21 to N23 and N30 are signals, F00 to F20 are fuses, VCC is a power supply voltage, VSS is a ground voltage, QN and Q
N00 to QN20 are N-channel MOS transistors,
QP and QP00 to QP03 are P-channel MOS transistors.

In the third embodiment, the redundant memory cell selection circuit, as in the prior art, has a defective memory cell among a plurality of memory cell groups formed at intersections of word lines and bit lines arranged in a grid. The memory cell group is replaced with a redundant memory cell group connected to the redundant word line group and prepared in advance, and is relieved.

The redundant memory cell selection circuit includes memory cell blocks MCB0 to MCB7 selected by logic voltages of address signals A6 to A8. Each of memory cell blocks MCB0 to MCB7 has a normal memory cell group and a redundant memory cell group connected to a redundant word line group. Memory cell block M
Redundant word line group RWL for CB0-MCB7
00 to RWL 70 are provided. Therefore,
A total of eight redundant word line groups RWL are provided. Each of redundant word line groups RWL00 to RWL70 can be replaced with any defective memory cell group in any memory cell block. For example, when it is desired to replace a defective memory cell group in the memory cell block MCB0 with a redundant memory cell group connected to the redundant word line group RWL50 in the memory cell block MCB5, for example, FIG.
18 fuses F00 to F17 so that the address of the defective memory cell group in the memory cell block MCB0 is selected by the selection fuse circuit block FB20.
9 of the half are cut. In the memory cell block selection address of the memory cell block MCB0, the address signal A6 is "0", A7 is "0", and A8 is "0". In the selected address of the MCB 5, the address signal A6 is "1", A7 is "0", and A8 is "1". In order to switch the selection of the memory cell block from MCB0 to MCB5, A6 and A8 which are mutually different (logical voltages are opposite) address signals A6 to A8 among selection address signals A6 to A8 respectively corresponding to memory cell blocks MCB0 and MCB5. And the corresponding fuses F18 and F20 are cut.

Hereinafter, the circuit operation of the redundant memory cell selection circuit according to the third embodiment will be described. FIG. 6 shows a selection fuse circuit block FB20, and the selection fuse circuit blocks FB21 to FB27 are the same as the selection fuse circuit block FB20.

In FIG. 6, when signal / RA is set to logic voltage "L", P-channel MOS transistors QP00 to QP03 are turned on, and signals N01, N21 to NP are turned on.
23 becomes the logic voltage “H”. Thereafter, signal / RA attains logic voltage "H", and then address signals A0-A
An address signal selected from 8, / A0 to / A8 is output from, for example, an address buffer included in the device. Here, the address signals / A0 to / A8 are logic voltage signals that are the reverse of the address signals A0 to A8.

Address signals A0 to A8, / A0 to / A8
Are N-channel MOS transistors QN00 to QN17
, And 18 N-channel type M
9 of the half of the OS transistors QN00 to QN17
Only one turns on.

At this time, if all nine fuses corresponding to the selected address are blown, the signal N0
1 becomes the logic voltage "H", and the signal R00 is maintained at the state of the logic voltage "L".

Signal AALL is composed of address signals A0-A
8, / A0 to / A8 are determined and selected, and at the same time become a logic voltage "H". When the fuses F18 and F20 are cut, the signals N21 and N23 are cut off.
Becomes a logic voltage "H", and the signal N22 becomes a logic voltage "L".
Becomes Further, as described above, since the signal N01 is at the logic voltage “H”, the signals INVA60 and INVA80
Becomes a logic voltage "L", and the signal INVA70 becomes a logic voltage "H".

Then, a signal INVA60 of a logic voltage "L" is input to an address conversion circuit block ATC61 corresponding to the address signal A6 shown in FIG. 7, and the internal address signal A6R is a reverse logic signal of the address signal A6.
The internal address signal / A6R is a logical inverse of the address signal / A6. Similarly, address conversion circuit blocks ATC71, ATC corresponding to address signals A7, A8, respectively.
The signal INVA70 of the logic voltage "H" and the signal INVA80 of the logic voltage "L" are input to TC81, respectively. The internal address signal A7R becomes the same logic signal of the address signal A7, and the internal address signal / A7R is the address signal. / A7 and the internal address signal A
8R is a logical inverse of the address signal A8, and the internal address signal / A8R is a logical inverse of the address signal / A8.

Thus, memory cell block MC
The defective memory cell group of B0 can be replaced with a redundant memory cell group connected to the redundant word line group RWL50 of the memory cell block MCB5.

As described above, in the redundant memory cell selection circuit according to the third embodiment, eight selection fuse circuit blocks are prepared, and one fuse circuit block requires 21 fuses. , The total number of fuses is 2
1 × 8 = 168. This is reduced to 87.5% from 192 lines (12 lines × 16) in the conventional example.

The feature of the redundant memory cell selection circuit according to the third embodiment is that the total number of redundant word line groups and the number of selection fuse circuit blocks can be reduced, and the total area of the device can be reduced. This means that the number of rescuable memory cell groups in the memory cell block can be increased from two to eight in the related art, and the degree of freedom of the rescue by the redundant memory cell group can be increased.

(Fourth Embodiment) Hereinafter, a redundant memory cell selection circuit according to a fourth embodiment of the present invention will be described with reference to FIGS.

FIG. 8 shows a redundant memory cell selection circuit according to the fourth embodiment. FIG. 12 shows a selection fuse circuit block FB30 in FIG. 8, and selection fuse circuit blocks FB31 to FB37 are used for selection. This is similar to the fuse circuit block 30.

In FIGS. 8 and 12, MCB0 to MCB
B7 is a memory cell block, MCBR is a block dedicated to a redundant memory cell, FB30 to FB37 are fuse circuit blocks for selection, RWL00, RWL10,.
Denotes a redundant word line group, A0 to A8, / A0 to / A8
Is an address signal, SPE0 to SPE7, R30 to R3
7, / RA, N01 are signals, F00 to F17 are fuses, VCC is a power supply voltage, VSS is a ground voltage, QN00 to QN00.
QN17 is an N-channel MOS transistor, QP00
Is a P-channel type MOS transistor.

In the fourth embodiment, the redundant memory cell selection circuit preliminarily identifies a defective memory cell group among a plurality of memory cell groups formed at the intersections of word lines and bit lines arranged in a grid. This is replaced with a redundant memory cell group in the prepared redundant memory cell dedicated block MCBR and relieved.

The redundant memory cell selection circuit includes eight memory cell blocks MCB0 to MCB7 selected by the logic voltages of the address signals A6 to A8, and a redundant memory cell dedicated block MCBR.

Here, for example, the memory cell block MC
When it is desired to replace the defective memory cell group of B3 with the redundant word line group RWL00, 1 is selected so that the address of the defective memory cell group of the memory cell block MCB3 is selected in the selecting fuse circuit block.
Nine of half of the eight fuses F00 to F17 are cut.

Hereinafter, the circuit operation of the redundant memory cell selection circuit according to the fourth embodiment will be described. FIG. 12 shows a selection fuse circuit block FB30, and the selection fuse circuit blocks FB31 to FB37 are the same as the selection fuse circuit block 30.

In FIG. 12, first, signal / RA attains logic voltage "L", and P-channel MOS transistor Q
P00 turns on, and the signal N01 becomes the logic voltage “H”.
Thereafter, the signal / RA becomes the logic voltage "H", and the address signals A0 to A8 and / A0 to / A8 output the selected address. Here, address signals / A0 to / A
Numeral 8 is a logic voltage signal which is the reverse of the address signals A0 to A8.

Address signals A0 to A8, / A0 to / A8
Are N-channel MOS transistors QN00 to QN17
, And 18 N-channel type M
9 of the half of the OS transistors QN00 to QN17
One turns on.

At this time, if all nine fuses corresponding to the selected address are blown, the signal N0
1 becomes the logic voltage "H", and the signal R30 is held at the state of the logic voltage "L".

Thus, memory cell block MC
The defective memory cell group of B3 can be replaced with a redundant memory cell group connected to the redundant word line group RWL00 of the redundant memory cell dedicated block MCBR.

As described above, in the redundant memory cell selection circuit according to the fourth embodiment, eight selection fuse circuit blocks are prepared, and one selection fuse circuit block requires 18 fuses. , The total number of fuses is 1
8 × 8 = 144. 7 compared to 192 in the conventional example
Reduced to 5%.

The feature of the redundant memory cell selection circuit according to the fourth embodiment is that, similarly to the third embodiment, the number of redundant word line groups and the number of selection fuse circuit blocks are reduced as a whole. This means that the total area can be reduced, and the number of memory cell groups that can be rescued in each memory cell block can be increased from two to eight, thereby increasing the degree of freedom of rescue by the redundant memory cell groups.

Fifth Embodiment Hereinafter, a redundant memory cell selection circuit according to a fifth embodiment of the present invention will be described with reference to FIGS. 9, 13 and 14.

FIG. 9 shows a redundant memory cell selection circuit according to the fifth embodiment, FIG. 13 shows a selection fuse circuit block FB40 in FIG. 9, and FIG. 14 shows an address conversion circuit block ATC66 in FIG. And
The address conversion circuit blocks ATC76 and 86 are similar to the address conversion circuit block ATC66.

MCB0 to MCB8 are memory cell blocks, FB40 is a fuse circuit block for selection, and A0 to A
8, / A0 to / A8 are address signals, A6R, A7R,
A8R, / A6R, / A7R, / A8R are internal conversion address signals, AR, / AR, / RA, N01 are signals, F0
0 to F05 are fuses, VCC is a power supply voltage, VSS is a ground voltage, QN00 to QN05 are N-channel MOS transistors, QP00 is a P-channel MOS transistor, and ATC66, ATC76 and ATC86 are address conversion circuit blocks.

In the fifth embodiment, the redundant memory cell selection circuit includes nine memory cell blocks MCB0 to MCB8, and one of the nine memory cell blocks is used as a spare memory cell block, and a defective memory cell block is provided. Eight memory cell blocks are selected and used.

The memory cell block MCB is configured to be selected by the logic voltages of the address signals A6 to A8.

For example, when there is a defect in the memory cell block MCB3, the fuses F01, F03, and F04 in the selecting fuse circuit block FB40 are cut.

Hereinafter, the circuit operation of the redundant memory cell selection circuit according to the fifth embodiment will be described.

FIG. 13 shows a fuse circuit block FB for selection.
In FIG. 13, first, the signal / RA
Becomes the logic voltage "L", the P-channel MOS transistor QP00 turns on, and the signal N01 becomes the logic voltage "H". Thereafter, the signal / RA becomes the logic voltage "H",
Next, the address signals A6 to A8 and / A6 to / A8 output the selected memory cell block selection address.
Here, the address signals / A6 to / A8 are the address signals A
6 is a reverse logic voltage signal of A8.

When a memory cell block selection address corresponding to memory cell block MCB3 is selected, signal N
01 becomes the logic voltage “H”, and the signal AR is held at the state of the logic voltage “H”.

Thus, memory cell block MC
The memory cell block MCB8 is selected instead of B3, and the memory cell block can be replaced.

A feature of the redundant memory cell selection circuit according to the fifth embodiment is that a defective memory cell block can be replaced for each memory cell block.

(Sixth Embodiment) Hereinafter, a redundant memory cell selection circuit according to a sixth embodiment of the present invention will be described with reference to FIGS. 10, 13, and 14. FIG.

FIG. 10 shows a redundant memory cell selection circuit according to the sixth embodiment, FIG. 13 shows the selection fuse circuit block FB40 in FIG. 10, and FIG.
Shows an address conversion circuit block ATC66, and address conversion circuit blocks ATC76 and ATC8.
6 is the same as the address conversion circuit block ATC66. Here, the selection fuse circuit blocks FB100 to FB107 in FIG. 10 are the same as the selection fuse circuit blocks of the redundant memory cell selection circuit according to the conventional example shown in FIG.

In FIG. 10, FIG. 13 and FIG.
B0 to MCB8 are memory cell blocks, FB100 to FB
B107 and FB40 are fuse circuit blocks for selection.
WL00 to RWL08 are redundant word line groups;
A8, / A0 to / A8 are address signals, A6R, A7
R, A8R, / A6R, / A7R, / A8R are internal conversion address signals, AR, / AR, / RA, N01 are signals,
F00 to F05 are fuses, VCC is power supply voltage, VSS
Is ground voltage, QN00 to QN05 are N-channel MOS
The transistor QP00 is a P-channel MOS transistor, and ATC66, ATC76 and ATC86 are address conversion circuit blocks.

The redundant memory cell selection circuit according to the sixth embodiment is different from the fifth embodiment in that a redundant word line group is provided in each memory cell block.
It has nine memory cell blocks CB8, one of the nine memory cell blocks MCB0 to MCB8 is used as a spare memory cell block, and eight memory cell blocks with few defects are selected and used. A defective memory cell group in a memory cell block replaces a redundant memory cell group connected to a redundant word line group. The method of selecting the memory cell block is the fifth.
This is the same as the embodiment of the present invention. The replacement of the defective memory cell group in each memory cell block is the same as in the conventional example.

The features of the redundant memory cell selection circuit according to the sixth embodiment are that a defective memory cell block is replaced for each memory cell block, and a defective memory cell group is replaced with a redundant memory cell group in each memory cell block. That you can do it.

In the sixth embodiment, the same fuse circuit block for selection as in the prior art is used. However, the same fuse circuit block for selection as in the first embodiment is used. By doing so,
The number of selection fuse circuit blocks can be reduced, and the device area can be reduced. Seventh Embodiment Hereinafter, a redundant memory cell selection circuit according to a seventh embodiment of the present invention will be described with reference to FIG. 11, FIG. 12, FIG. 13 and FIG.

FIG. 11 shows a redundant memory cell selection circuit according to the seventh embodiment. FIG. 12 shows a selection fuse circuit block FB30 in FIG. 11, and selection fuse circuit blocks FB31 to FB37 are used for selection. FIG. 13 shows the selecting fuse circuit block FB40 in FIG. 11, FIG. 14 shows the address conversion circuit block ATC66 in FIG. 11, and FIG. 13 shows the address conversion circuit block A.
TC76 and ATC86 are address conversion circuit blocks AT
It is similar to C66.

In FIGS. 11, 12, 13 and 14, MCB0 to MCB8 are memory cell blocks, FB3
0 to FB37 and FB40 are selection fuse circuit blocks, A0 to A8, / A0 to / A8 are address signals, A6
R, A7R, A8R, / A6R, / A7R, / A8R are internal conversion address signals, SPEX, R30 to R37, A
R, / AR, ARX, / RA, N01 are signals, F00 to F00
F17 is a fuse, VCC is a power supply voltage, VSS is a ground voltage, QN00 to QN17 are N-channel MOS transistors, QP00 is a P-channel MOS transistor, A
TC66, ATC76 and ATC86 are address conversion circuit blocks.

The redundant memory cell selection circuit according to the seventh embodiment uses a memory cell group of a memory cell block not selected in the fifth embodiment as a redundant memory cell group.

The redundant memory cell selection circuit has MCB0 to MCB
CB8 is provided as nine memory cell blocks, one of the nine MCB0 to MCB8 is used as a spare memory cell block, and eight memory cell blocks are selectively used. For the defective memory cell group in the block, the memory cell group of the spare memory cell block is used as a redundant memory cell group. The method of selecting a memory cell block is the same as that of the fifth embodiment. The replacement of the defective memory cell group in each memory cell block is realized such that the address conversion circuit blocks ATC66 to ATC86 do not operate when an address stored in the selection fuse circuit blocks FB30 to FB37 is selected. ing.

The feature of the redundant memory cell selection circuit according to the seventh embodiment is that a defective memory cell block is replaced for each memory cell block and a defective memory cell group in each memory cell block is replaced in a spare memory cell block. Can be replaced with a memory cell group of

(Eighth Embodiment) Hereinafter, a redundant memory cell selection circuit according to an eighth embodiment of the present invention will be described with reference to FIG.

FIG. 15 shows each memory cell block of the redundant memory cell selection circuit according to the eighth embodiment.
The redundant memory cell selection circuit according to the eighth embodiment is shown in FIG.
Is the same as the redundant memory cell selection circuit according to the fifth embodiment shown in FIG.

In FIG. 15, V11 is a bit line precharge power supply, F110 is a fuse, BE is a bit line equalizing and precharge circuit, MC is a memory cell, SA
Is a sense amplifier circuit, C is a memory cell capacitor, Q
N and QNM are N-channel MOS transistors, QP is a P-channel MOS transistor, VBP, SBP, V
CP, SAP, and SAN are signals, WL1, WL2,.
L255, WL256 are word lines, BL1, BL2,
..., BL512, / BL1, / BL2, ..., / BL51
2 is a bit line.

In the eighth embodiment, the redundant memory cell selection circuit is capable of disconnecting the bit line precharge power supply node signal VBP transmission line from the bit line precharge power supply V11 by cutting the fuse F110. is there.

When the device is in the standby state, the bit line equalize and precharge signal SBP is at the logic voltage "H", and the bit lines BL1 to BL512, / BL
1 to / BL512 are respectively connected to the transmission lines of the precharge power supply node signal VBP of the bit lines, while the word lines WL1 to WL256 are respectively connected to the ground voltage VSS.

The feature of the redundant memory cell selection circuit according to the eighth embodiment is that such a defect occurs when a short circuit occurs between a bit line and a word line of a memory cell block in a manufacturing process. By not using the memory cell block and cutting the fuse F110 to separate the bit line precharge power supply node signal VBP transmission line from the bit line precharge power supply V11, the potentials of the bit line and the word line are equalized. By doing so, it is possible to recover from a power supply current defect.

Ninth Embodiment Hereinafter, a redundant memory cell selection circuit according to a ninth embodiment of the present invention will be described with reference to FIG.

FIG. 16 shows each selection fuse circuit block of the redundant memory cell selection circuit according to the ninth embodiment. The selection fuse circuit block has a function of canceling an address stored once. ing. The overall configuration of the redundant memory cell selection circuit according to the ninth embodiment is the same as that of the conventional redundant memory cell selection circuit shown in FIG. 17 except for a fuse circuit block for selection.

In FIG. 16, A0-A8, / A0- /
A8 is an address signal, F00 to F11, F120 are fuses, / RA, N121 to N123, R00, AALL
Is a signal, VCC is a power supply voltage, VSS is a ground voltage, QN0
0 to QN11 and QN121 are N-channel MOS transistors, and QP00 and QP121 are P-channel MOS transistors. The signal AALL includes address signals A0 to A0.
When A8 is determined, the signal becomes a logic voltage "H".

In the ninth embodiment, the method of storing the address of the defective memory cell group rescued by the redundant memory cell group is the same as that of the conventional example shown in FIG.
Of the 12 fuses F00 to F11 of the selection fuse circuit block shown in FIG.
Just cut the book. In order to cancel the address once stored by the selecting fuse circuit block, the fuse F120 may be cut.

The feature of the redundant memory cell selection circuit according to the ninth embodiment is that if a selection fuse circuit block having a function of canceling an address stored once is provided, it can be replaced with a defective memory cell group. When the redundant memory cell group is defective, the address of the defective memory cell group stored in the fuse circuit block for selection is canceled, and the address of the defective memory cell group is newly stored in another fuse circuit block for selection. Is stored, it is possible to replace the defective memory cell group with another redundant memory cell group, and the remedy rate by the redundant memory cell group can be greatly improved.

[0133]

As described above, claims 1 to 4, 1
0 according to the memory provided with the redundant memory cell according to the invention.
Less than the number of prepared redundant memory cell groups.
No redundant fuse circuit blocks for all redundancy
Select one of the memory cell groups
Relief rate by redundant memory cell group
Requires large layout area without compromising
The total area of the fuse circuit block for selection
Can reduce the overall area of the device
Wear.

The redundant memory cell selection according to the invention of claim 5
According to the circuit, the redundancy memory cell group
The entire redundant memory cell glue without reducing
And the number of selection fuse circuit blocks
To reduce the overall area of the device
Can be. Also, the relief rate by the redundant memory cell group
Can be improved.

A redundant memory cell according to claim 7 or 8
According to the selection circuit, the memory cell block with the defective part
Can be replaced for each memory cell block.

The redundant memory cell selection according to the ninth aspect of the present invention.
According to the circuit, is replaced with a defective memory cell group
If the redundant memory cell group is defective,
Good memory cell group to other redundant memory cell group
It is possible to replace it. Therefore, the redundant memory cell
The rescue rate by the group can be greatly improved
You.

As a result, according to the present invention, it is possible to provide an inexpensive and high-yield redundant memory cell selection circuit that suppresses an increase in chip area. As a result, a great effect that a cheaper semiconductor memory device can be supplied can be obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a redundant memory cell selection circuit according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a fuse circuit block for selection of a redundant memory cell selection circuit according to the first embodiment.

FIG. 3 is a block diagram showing a redundant memory cell selection circuit according to a second embodiment of the present invention.

FIG. 4 is a circuit diagram showing a fuse circuit block for selection of a redundant memory cell selection circuit according to the second embodiment.

FIG. 5 is a block diagram showing a redundant memory cell selection circuit according to a third embodiment of the present invention.

FIG. 6 is a circuit diagram showing a fuse circuit block for selection of a redundant memory cell selection circuit according to the third embodiment.

FIG. 7 is a circuit diagram showing an address conversion circuit block of a redundant memory cell selection circuit according to the third embodiment.

FIG. 8 is a block diagram showing a redundant memory cell selection circuit according to a fourth embodiment of the present invention.

FIG. 9 is a block diagram showing a redundant memory cell selection circuit according to a fifth embodiment of the present invention.

FIG. 10 is a block diagram showing a redundant memory cell selection circuit according to a sixth embodiment of the present invention.

FIG. 11 is a block diagram showing a redundant memory cell selection circuit according to a seventh embodiment of the present invention.

FIG. 12 is a circuit diagram showing a fuse circuit block for selection of a redundant memory cell selection circuit according to the fourth and seventh embodiments.

FIG. 13 is a circuit diagram showing a fuse circuit block for selection of a redundant memory cell selection circuit according to the fifth, sixth, and seventh embodiments.

FIG. 14 is a circuit diagram showing an address conversion circuit block of a redundant memory cell selection circuit according to the fifth, sixth, and seventh embodiments.

FIG. 15 is a circuit diagram showing a memory cell block of a redundant memory cell selection circuit according to an eighth embodiment of the present invention.

FIG. 16 is a circuit diagram showing a fuse circuit block for selection of a redundant memory cell selection circuit according to a ninth embodiment of the present invention.

FIG. 17 is a block diagram showing a redundant memory cell selection circuit according to a conventional example.

FIG. 18 is a circuit diagram showing a fuse circuit block for selection of the redundant memory cell selection circuit according to the conventional example.

[Explanation of symbols]

MCB0 to MCB8 Memory cell block MCBR Redundant memory cell dedicated block RWL00 to RWL71 Redundant word line group FB00 to FB40 Selection fuse circuit block ATC61 to ATC86 Address conversion circuit block A0 to A8, / A0 to / A8 Address signal F00 to F20, F110 , F120 Fuses QN, QNM, QN00 to QN20 N-channel type MO
S-transistor QP, QP00-QP03 P-channel MOS transistor QP20, QP121 P-channel MOS transistor

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-4-345998 (JP, A) JP-A-2-208898 (JP, A) JP-A-4-152565 (JP, A) JP-A-3-352 245400 (JP, A) JP-A-2-310898 (JP, A) JP-A-5-74191 (JP, A) JP-A-3-104097 (JP, A) JP-A-5-290598 (JP, A) (58) Field surveyed (Int. Cl. ⁷ , DB name) G11C 29/00 603

Claims (10)

(57) [Claims] 1. Each memory cell has a predetermined number of memory cells.
Memory cell group and redundant memory cell group
A memory configured to be able to switch between Each has multiple memory cell groups and multiple redundant
Multiple memory cell blocks having a memory cell group
When, Redundant memory cell selection having a plurality of fuse circuit blocks
And a selection circuit, Each of the plurality of fuse circuit blocks is connected to the memory
One of the memory cell groups in the cell group is
Memory cell indicating the address of the memory cell block to which it belongs
Block selection address and memo of the memory cell group
Select memory cell group indicating address in recell block
And the selected address are stored by connecting and disconnecting the fuse. The redundant memory cell selection circuit is configured to access the memory to be accessed.
The address signal indicating the memory cell group causes
The memory stored in any one of the fuse circuit blocks
Cell block selection address and memory cell group
Generates an in-block selection signal when the selected address is selected
And The memory cell to be accessed in the address signal
Cell block indicating the memory cell block to which the
Block designation address signal and the above-mentioned block selection signal.
One of the redundant memory cell groups is selected based on
A memory characterized by being configured to be operated. 2. The memory of claim 1, wherein: The fuse circuit block has a plurality of redundant memory blocks.
Less than the total number of Morisel groups
A memory characterized by the above. 3. The memory according to claim 1 or claim 2.
hand, The fuse circuit blocks are respectively connected to the respective memories.
In cell block Any one of the redundant memory cells
That is provided in correspondence with the group of
Memory. 4. The memory according to claim 1 or claim 2.
hand, At least one of the fuse circuit blocks
One is any one in each of the above memory cell blocks.
For selecting the above redundant memory cell group
A memory further comprising a memory. 5. The memory according to claim 1 or claim 2.
hand, Furthermore, depending on the setting by connecting and disconnecting the fuse, the above cell
Address conversion circuit that converts block designation address signals
With The memory to which the memory cell group to be switched belongs
Belongs to a memory cell block different from the cell block
The redundant memory cell group is configured to be selectable.
A memory characterized by being stored. 6. The memory of claim 5, wherein: The address conversion circuit is changed by disconnection of the fuse.
The value of each bit of the address before and after the change
To convert the address signal
A memory characterized by being configured. 7. The memory according to claim 1 or claim 2.
hand, Further, the configuration is substantially the same as that of the memory cell block.
A redundant memory cell block having The memory cell block and the redundant memory cell block
Memory cell block selection circuit
And a memory. 8. The memory of claim 7, wherein: Select the memory cell block by connecting / disconnecting the fuse
The above-mentioned memory cell block switched by the circuit
Bit line and word line potentials Set
The memory characterized by being comprised so that. 9. Each memory cell has a predetermined number of memory cells.
Memory cell groups and redundant memory cell groups
A memory configured to be switchable, Each has multiple memory cell groups and multiple redundancy
Multiple memory cell blocks with long memory cell groups
And Depending on the setting by connecting and disconnecting fuses, the redundant
Configured to select one of the molycell groups
And a fuse circuit block, The above fuse circuit block, A fuse to cancel the above settings, When the above cancellation is made, a signal of a predetermined level
Characterized by further comprising a logic circuit for outputting
Mori. 10. A plurality of memory cell groups each comprising:
Plurality of memory cells having redundant memory cell groups
Blocks and And a fuse circuit block, The fuse circuit block includes a plurality of memory cell groups.
Memory cell block of one memory cell group in the loop
Memory cell group selection address indicating address in lock
Memory cell to which the one memory cell group belongs.
Memory cell block select address indicating block address
And the total number of the fuse circuit blocks.
Is less than the total number of the redundant memory cell groups.
A memory characterized by the above.