JP3351254B2 - Load control system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of connecting a plurality of terminals individually assigned addresses to a central controller via a signal line composed of a pair of lines, and the central controller controls the address of each terminal. The present invention relates to a load control system for controlling a load connected to a terminal device in a building management system, for example, by transmitting control data by time division multiplexing by designating the same.

[0002]

2. Description of the Related Art Conventionally, in a building called a so-called intelligent building, a load control system by remote monitoring for centrally managing the operation state of each load device in a power / power receiving / distributing system, a lighting / air conditioning system, etc. is used. Have been. For example, in the general load control system shown in FIG. 6, one central control unit A and individually assigned terminals B1, B2,... Bn are a pair of lines such as a coaxial cable and a twisted pair line. Are connected via a signal line L composed of

FIG. 7 shows a time division multiplex transmission signal transmitted from the central control unit A to each terminal via a signal line L. The time division multiplex transmission signal Vs includes, in one frame, a start pulse signal ST indicating the start of signal transmission, an address data signal AD for calling a terminal device Bi (i = 1, 2,... N) to be communicated, The control data signal CD for controlling the operation of the terminal Bi and the return standby signal WD for setting the return period of the signal from each terminal Bi are included at least by the CPU 1 built in the central controller A. Generated. The time division multiplex transmission signal Vs is, for example, a bipolar (± 24 V) voltage signal, and has a low impedance signal output circuit by pulse width modulation in which a long voltage pulse is “1” and a short voltage pulse is “0”. More output.

In each terminal Bi, a rectifier and a smoothing capacitor are connected between signal lines L to obtain an operating power supply.
When the address data of the time-division multiplex transmission signal Vs input via the signal line L matches the own address data, the control data signal CD is taken in, and the return of the time-division multiplex transmission signal Vs is waited. By synchronizing with the signal WD, by short-circuiting the signal lines L on the terminal device Bi side via a resistor having a predetermined resistance value, the long current pulse is "1" and the short current pulse is "0". Is returned as a reply signal Vi, which is a serial data signal of a plurality of bits indicating a current mode.

[0005] In the above remote monitoring and control system, the central control unit A normally supplies, for example, an address signal AD with the address signal AD.
The time division multiplex transmission signal Vs is output by changing each terminal Bi so as to be periodically polled and accessed. When each terminal Bi receives the start pulse ST by this access, it checks the address data signal AD with its own address, and only one terminal Bi whose address coincides takes in the subsequent control data signal CD and loads the terminal Bi. A control operation for controlling the device and a return operation of a monitoring data signal based on the monitoring input content from the load device are performed.

FIG. 8 shows a CPU of a conventional central control unit A.
Peripheral circuit configuration. The central controller A has a CPU 1 for generating and processing the time-division multiplexed transmission signal Vs, and a reset IC 2 having a watchdog timer for automatically resetting the CPU when an abnormality occurs in the system. It has. The CPU 1 has a built-in frame signal generation circuit 1a, and when it is determined that the time division multiplex transmission signal Vs is normal, a pulse signal synchronized with the frame signal is output from the output port P1 and input to the reset IC2. Is done. That is, as shown in FIG. 7, a pulse signal as a frame synchronization signal is output one pulse at a time in synchronization with one frame of the time division multiplex transmission signal, and the normal operation of the remote monitoring and control system is confirmed. The abnormality is recovered by the self-reset by the output from the reset IC 2 corresponding to the watchdog timer which is the monitoring means, and the central controller A and each terminal Bi are recovered.
The transmission and reception of the time-division multiplex transmission signal Vs is resumed.

[0007]

By the way, the above-mentioned central control unit A can appropriately cope with the occurrence of a system abnormality by self-reset. Maintenance for pursuit is often based on the intuition and experience of the site adjustment worker.
For example, the monitoring data of the communication circuit when the frequency of occurrence of the abnormality is high is collected, the relation with the occurrence of the self-reset is examined, and measures are taken in the operation program. As a result, a great deal of time and effort is required for the maintenance of the program for coping with the occurrence of the abnormality.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a load control system capable of investigating a cause of an abnormality in a short time in maintenance of the load control system by remote monitoring. To provide.

[0009]

According to a first aspect of the present invention, there is provided a load control system comprising: a plurality of terminals to which addresses are individually assigned via a signal line composed of a pair of lines; The central control unit is connected to the central control unit, and the central control unit specifies the address of each terminal by the CPU to transmit the control data in a time-division multiplex manner so that the load connected to the terminal is displayed on the screen of the liquid crystal touch panel device. In a load control system for displaying and controlling a control state on a means, the central control device includes an abnormal operation detecting means for detecting an abnormal operation when the CPU operates, and an abnormal storage means for storing a detection result by the abnormal operation detecting means. the provided, transition information storage means for CPU program constantly updates and stores the transition information of a task status of each program task, and, in the transition information storage means It includes an abnormality information storing means for storing the transfer information as abnormality information, der which sequentially updates the abnormality information on the content of the transition information when it detects that there is an abnormal operation by said abnormality storage means at start
The abnormality information storage means is provided with at least the abnormality information.
Are also used as ring buffers for sequentially updating and storing the two . Thus, when the startup is restarted due to the abnormal operation, the transition information in the abnormal operation is sequentially updated as the abnormal information and stored in the abnormal information storage means. Then, at least two pieces of the abnormality information are sequentially updated.
The ring buffer stores and stores new abnormal information.
The information can be referred to while comparing the information.

[0010]

According to a second aspect of the present invention, in addition to the transition information of the first aspect , the step transition information storage means constantly updates and stores transition information of processing steps for each program task. It has to have. As a result, the transition information of the processing step for each program task is sequentially updated and stored.

A load control system according to a third aspect of the present invention includes, in addition to the CPU according to the first or second aspect , a display control means capable of displaying the contents of the abnormality information. Thereby, the stored abnormality information can be appropriately displayed by the display control means.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a load control system according to the present invention will be described below with reference to FIGS. FIG. 1 shows a CPU of a central control unit used in a load control system.
3 is a configuration diagram of a peripheral circuit of FIG. FIG. 2 is a schematic flowchart of a program of a CPU of the central control device shown in FIG.
(A) is a schematic flowchart at the time of startup, and (b) is a schematic flowchart at the time of storage in a ring buffer. FIG.
3 is an explanatory diagram of a transition information table as a storage table of a CPU of the central control device shown in FIG. FIG.
It is explanatory drawing of an example of the step information of each task of CPU of the central control apparatus shown in FIG. FIG. 5 is an example of display of abnormality information of the touch panel device of the central control device shown in FIG.

This load control system is formed by one central control unit A and terminals B1, B2,... Bn to which addresses are individually assigned, as in the conventional example.

The central control unit A transmits the time division multiplex transmission signal V
and a reset I having a watchdog timer for automatically resetting the CPU 1 when an abnormality occurs in the system or the like.
C2 and a flip-flop IC3 corresponding to abnormality storage means for storing a watchdog abnormality result which is a detection result of an abnormal operation by the reset IC2. The power of the RAM 4, which is a storage means of the CPU 1, is backed up by a backup battery 6 together with a clock IC 5 and a flip-flop IC 3 that output clock data and the like to the RAM 4. Also, this CPU 1
Includes a liquid crystal touch panel device having a key matrix circuit for performing touch input and a display device such as a liquid crystal display device as a display control device, not shown.

The power supply voltage of the CPU 1 is monitored by the reset IC 2. Therefore, this reset IC2
Is a power reset operation for detecting that the power supply voltage to the CPU 1 has reached a predetermined voltage value and performing a reset output to the CPU, and a watchdog output from the CPU 1 which is constantly input, and this input continues for a predetermined time. CP by not having
An operation corresponding to abnormal operation detecting means for detecting an abnormal operation during the operation of U is performed. Also, this reset IC 2
At the time of performing the reset output to U1, a pulse signal notifying the occurrence of the reset is output to the flip-flop IC3. The notification of the occurrence of the reset is made by the fact that the flip-flop IC3 is backed up by the power supply.
The data is held regardless of the power on / off state of the PU1.

The operation of the above-described device will be described below. First, after the power reset operation by the reset IC 2, if the time division multiplex transmission signal Vs is normally transmitted from the CPU 1, a pulse signal synchronized with the frame signal is output from the output port P 1 and the reset IC 2
, And the CPU 1 continues normal operation.

Next, after the power reset operation, C
When the time division multiplex transmission signal Vs is not normally transmitted from the PU1, the watchdog output from the CPU1 is not input to the reset IC2, and the reset signal is directed to the reset input R of the CPU1 by the watchdog abnormality detection operation of the reset IC2. Is output. At the same time, reset IC
2 outputs a pulse signal to the flip-flop IC3 that the watchdog abnormality has occurred. Note that this signal output result does not disappear even when the power is cut off because the power supply of the flip-flop IC3 is backed up by the backup battery 6. When the CPU 1 restarts in this state, a signal output from the flip-flop IC3 to a predetermined input port (P2) of the CPU 1 is detected, and the CPU 1 detects that a watchdog abnormality has occurred.

Then, in the ring buffer set in the RAM 4, for example, as shown in FIG. 3, the transition information of the task state of each program task is constantly updated together with the abnormality occurrence number D1 and the time data D2 at the time of activation by the clock IC5. The transition information D3 is stored as information on the number of times that the watchdog reset occurrence number stored separately is incremented by one. In this transition information, step transition information by step transition information storage means for constantly updating and storing transition information of processing steps of each program task in the program of the CPU 1 is also stored. Note that the ring buffer is a data buffer used for sequentially storing a predetermined number of data stored based on a predetermined format. After the predetermined storage area is full, the ring buffer is sequentially older. Data is overwritten by new data and erased.

The step transition information indicates, for example, an intra-task update number D31, which is sequentially updated when a predetermined task process is completed, as shown in FIG. 4, and indicates whether the task is stopped, waiting, executable, interrupted, and being executed. It includes a first state flag D32 and a second state flag D33 indicating whether to wait for time, wait for an event, or wait for release of a shared resource as a wait factor.

After updating the abnormality information stored in the ring buffer, a predetermined output port (P
From 3), a signal for erasing a signal output indicating that a watchdog error has occurred is output to the flip-flop IC3, and the operation shifts to a normal operation.

The task state transition information and task step transition information of each program task described above are displayed on a screen of a liquid crystal touch panel device as display means, for example, as shown in FIG.
Is appropriately displayed by an operation of a touch panel controlled by a key matrix as a display control means, and is used when analyzing a cause of a watchdog reset in maintenance of a load control system. By referring to the detailed abnormality information, the cause of the abnormality can be investigated in a short time.

Hereinafter, based on the procedure of the flowchart shown in FIG. 2, when the flip-flop IC3 detects that there is an abnormal operation at the time of startup, the abnormal information stored in the ring buffer is stored in the transition information storing means. The flow of the process of sequentially updating the contents will be described.

First, when the CPU is started, the input port (P
It is detected from the signal input of 2) that a watchdog abnormality has occurred (step 1). Then, 1 is added to the separately stored count data of the watchdog reset (abnormality) count (step 2). Next, the transition information of each program task is constantly updated and the abnormality information stored in the transition information storage unit is read, and the oldest information of the abnormality information stored in the ring buffer is updated to the read information and stored. (Step 3). Then
A signal for erasing the storage of the abnormal operation from the flip-flop IC3 is output to a predetermined output port (step 4). In the update of the abnormality information in step 3 described above, first, the data of the number of occurrences of the abnormality calculated in step 2 is stored in the memory address where the oldest information among the abnormality information stored in the ring buffer is stored ( Step 31).
Next, the clock data from the clock IC 4 is stored in a predetermined address of the ring buffer (step 32). Then, the step transition information storage means for constantly updating and storing the transition information of the processing step for each program task reads out the updated data of the update number in the task as step transition information and stores it at a predetermined address of the ring buffer. (Step 33). Next, the first state flag D3 which constantly updates and stores the transition information of the processing step for each program task by the step transition information storage means.
2. The data of the second state flag D33 is read as step transition information and stored in a predetermined address of the ring buffer (step 34). Steps 33 and 34
Is stored for all tasks (step 35).

According to the load control system described above,
When restarting due to an abnormal operation, the transition information in the abnormal operation is sequentially updated as the abnormal information and stored in the abnormal information storage means, so by referring to this abnormal information in the maintenance of the load control system, The cause of the occurrence of the abnormality can be investigated in a short time. In addition, since a plurality of new pieces of abnormality information can be simultaneously referred to while comparing them, the transition leading to the occurrence of the abnormality can be easily referred to, and the cause can be investigated in a shorter time. Further, since the transition information of the processing step for each program task is sequentially updated and stored, the cause can be investigated in a shorter time by analyzing the cause of the abnormality in detail. In addition, the abnormality information stored in the ring buffer can be appropriately displayed on the screen of the liquid crystal touch panel device by operating the touch panel controlled by the key matrix. It can be easily referred without using equipment.

[0026]

According to the load control system of the present invention, when the startup is restarted due to the abnormal operation, the transition information in the abnormal operation is sequentially updated as the abnormal information and stored in the abnormal information storage means. In maintenance of the load control system, the cause of the occurrence of the abnormality can be investigated in a short time by referring to the abnormality information.

In addition, since a plurality of new pieces of abnormality information can be simultaneously referred to while comparing them, a transition leading to the occurrence of an abnormality can be easily referred to, and the cause can be investigated in a shorter time.

Further, the load control system according to claim 2, wherein, in addition to the effect of those according to claim 1, since a thing of transition information of the processing steps for each program tasks are stored is sequentially updated, fine abnormal The cause can be investigated in a shorter time by analyzing the cause.

In the load control system according to the third aspect , in addition to the effects of the first or second aspect , since the stored abnormality information can be appropriately displayed by the display control means, the abnormality information is read out. Can be easily referenced without using any special equipment.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a peripheral circuit of a CPU of a central control device used in a load control system according to an embodiment of the present invention.

FIG. 2 is a schematic flowchart of a program of a CPU of the central control device shown in FIG. 1, (a) is a schematic flowchart at the time of startup, and (b) is a schematic flowchart at the time of storage in a ring buffer.

FIG. 3 is an explanatory diagram of a transition information table as a storage table of a CPU of the central control device shown in FIG.

4 is an explanatory diagram of an example of step information of each task of a CPU of the central control device shown in FIG.

FIG. 5 is an example of display of abnormality information of the touch panel device of the central control device shown in FIG. 1;

FIG. 6 is a configuration diagram of a load control system.

FIG. 7 is an explanatory diagram of a transmission signal of the load control system.

FIG. 8 is a configuration diagram of a peripheral circuit of a CPU of a conventional central control device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 CPU 2 Reset IC (abnormal operation detection means) 3 Flip-flop IC (abnormal storage means)

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H04L 12/28 H04L 12/40-12/46

Claims (3)

(57) [Claims] 1. A plurality of terminals to which addresses are individually assigned are connected to a central controller via a pair of signal lines, and the central controller specifies an address of each terminal by a CPU. The load connected to the terminal is controlled by time-division multiplex transmission of control data and the touch panel
In a load control system for displaying and controlling a control state on a display unit which is a screen of a mobile device, the central control unit includes an abnormal operation detection unit for detecting an abnormal operation when the CPU operates, and a detection by the abnormal operation detection unit. comprising an abnormality storing means for storing the result, transition information storage means for CPU program constantly updates and stores the transition information of a task status of each program tasks, and abnormal for storing transition information of this transition information storage means as the abnormality information An information storage means for sequentially updating the abnormality information to the content of the transition information when detecting that an abnormal operation has been performed by the abnormality storage means at startup.
The abnormality information storage means, at least two of the abnormality information
A load control system characterized by using a ring buffer for sequentially updating and storing 2. The program according to claim 1, wherein the transition information is for each program task.
Step that constantly updates and stores the transition information of the processing steps
The load control system according to claim 1, wherein the load control system has step transition information stored in a step transition information storage unit . 3. The CPU according to claim 2, wherein the CPU stores the content of the abnormality information.
3. The load control system according to claim 1, further comprising a display control unit capable of displaying .