JP3346327B2 - Scanning circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] The present invention relates to, for example, p-Si
The present invention relates to a scanning circuit which is formed integrally with a liquid crystal display panel using a TFT or the like and drives the liquid crystal display panel.

[0002]

2. Description of the Related Art In recent years, a scanning circuit integrally formed with a liquid crystal display panel by using a p-Si TFT or the like has been required to operate at a higher speed with a higher definition of a display section. In order to meet this demand, for example, as disclosed in Japanese Patent Application Laid-Open No. Hei 7-134277, it has been proposed to configure a signal transfer portion with a transfer gate to enable high-speed operation. FIG. 7 is a circuit diagram showing a configuration of a scanning circuit according to the above-described conventional technique. FIG. 8 is a timing chart for explaining the operation of the scanning circuit. At timing T1 shown in FIG. 8, the transfer unit 101-2 is turned on, but at this time, the holding unit 102-2 is turned off.
Therefore, when the clock A = C and B = D and the left shift start pulse is input from the STL, the holding unit 1
02-2 through the transfer unit 101-3 and the holding unit 102-
3 is transferred to the “H” level signal. However,
When the clock skew of the external input signal increases, for example, when the clock is input at the timing shown in FIG. 8, the transfer unit turns on before the holding unit.

As described above, when a clock skew occurs as shown in FIG.
The "L" level signal is transferred to -1 and the scanning circuit malfunctions. The scanning circuit shown in FIG. 7 can be bidirectional by changing the combination of signals input to the holding unit 102 and the transfer unit 101, but requires four external input signals, and In consideration of the operation margin for the cue, it is necessary to match the skew of these input signals, so that it is difficult to create an external signal source.

In general, the above scanning circuit generates a gate pulse for switching a TFT in a pixel portion formed on a glass substrate, but usually has a significantly larger physical size than an IC circuit using silicon single crystal. Have. This reaches several cm to several tens of cm, and the capacity of the clock wiring increases. For this reason, skew occurs because the clock is delayed on the glass substrate, and skew easily occurs in a buffer circuit of an external circuit for driving this clock.

Therefore, for example, Japanese Patent Application Laid-Open No. 2-232710
Has proposed a circuit that considers the operation for clock skew. FIG. 9 is a circuit diagram showing a configuration of the conventional scanning circuit. In this circuit, a clock skew adjustment circuit 80 in a previous stage for inputting an external input signal to a scanning circuit
In step 1, the clock skew of the external input signal is adjusted, and then the signal is supplied by the clock distribution circuit 802.

[0006]

However, in the prior art (Japanese Patent Laid-Open No. 232710/1990), a high driving capability is required in order to supply a signal to each input of the scanning circuit after adjusting the phase at the preceding stage of the scanning circuit. Must have an output buffer. Generally, mobility such as p-Si formed integrally with a liquid crystal panel or the like is lower than that of crystalline Si. Therefore, it is difficult to integrally form a buffer having a high driving ability with the liquid crystal panel, and it is difficult to input a phase-adjusted signal to the scanning circuit before the scanning circuit.

The present invention has been made in view of the above circumstances, and has as its object to provide a scanning circuit that can prevent a malfunction when a clock skew occurs in an external input signal.

[0008]

In order to solve the above-mentioned problems, according to the first aspect of the present invention, a holding portion which is formed integrally with a liquid crystal display panel and holds a signal is held by the holding portion. A transfer unit that transfers a signal to the next stage; and a plurality of circuits including an output buffer that outputs a signal held in the holding unit. The transfer unit in the plurality of circuits is sequentially turned on according to a start pulse. and then, the scanning circuit sequentially transfers the signal held by the holding portion to the next stage by the transfer unit, based on the 2-phase clock signal input from the external circuit to the holding portion, the front <br / > detection means for detecting a timing at which the holding portion is fully on, by the detection means, it is detected that the front of the holding portion is turned fully on, and held in the holding portion of the front When the signal is valid, and control means for outputting a signal to activate the transfer of the current stage, the transfer unit, the signal to be active from the control means input
When the signal is input, the holding signal held in the holding unit is transferred to the next stage.

Further, according to the invention described in claim 2, according to claim 1,
The scanning circuit according to claim 1, further comprising transfer direction control means for controlling a transfer direction of a signal held in the holding unit, wherein the control means is configured to be active based on a transfer direction determined by the transfer direction control means. The transfer unit to be used is determined.

[0010] According to the third aspect of the present invention, the first aspect is provided.
In the above-described scanning circuit, the control unit activates the transfer unit and activates a transfer unit in a stage two stages before.

Further, according to the invention described in claim 4, according to claim 1,
In the above-described scanning circuit, the detection unit and the control unit are configured by a logic circuit formed integrally with the liquid crystal display panel.

According to the present invention, the detecting means detects a timing at which the holding section is completely turned on based on a signal input to the holding section from an external circuit. The control unit activates a predetermined transfer unit when it is detected that the holding unit is completely turned on and the signal held in the holding unit becomes valid. The activated transfer unit transfers the holding signal held in the holding unit to the next stage. Therefore, the transfer unit is always turned on after the holding unit, and even if the clock skew of the external signal becomes large, it is possible to prevent the scanning circuit from malfunctioning.

[0013]

Embodiments of the present invention will be described below with reference to the drawings. A. Configuration of Embodiment FIGS. 1 and 2 are block diagrams showing a configuration of a scanning circuit according to an embodiment of the present invention. In the figure, 101
(1) to 101 (k-1) are transfer units, 102 (0) to 1
02 (k) is a holding unit, 103 (0) to 103 (k) are output buffers, 104 (0) to 104 (k) are valid timing detection circuits, and 105 (0) to 105 (k) are transfer units /
Signal generation circuits, 106 (0) to 106 (k) and 107
(0) to 107 (k) are switches. As shown in FIG. 1, the main scanning circuit has 0,..., 2n-1, 2n, 2n +
The output buffer 103, the transfer units 101 (1) to 101 (k-1),
Holding units 102 (0) to 102 (k), valid timing detection circuits 104 (0) to 104 (k), transfer unit / signal generation circuits 105 (0) to 105 (k), switch 106
(0) to 106 (k) and 107 (0) to 107 (k). Note that n, m, and k are integers.

The transfer direction is determined by the switch 106 (0).
To 106 (k) and 107 (0) to 107 (k) are determined by a transfer direction control signal S1 for on / off control. The transfer direction control signal S1 is a DC voltage, and the switches 106 (0) to 106 (k) are switched by the transfer direction control signal S1 and the inverted transfer direction control signal S2.
107 (0) to 107 (k) are turned on and off. The scanning circuit shown in FIG. 1 can transfer signals in both directions, and switches 106 (0) to 106 (k), 107
The signal transfer direction is determined by the on / off states of (0) to 107 (k). For example, when transferring a signal in the downward direction shown in FIG.
(K) is turned on, and the switches 106 (0) to 106 (106) are turned on.
(K) is turned off. To transfer a signal upward, the switches 106 (0) to 106 (k) are turned on, and the switches 107 (0) to 107 (k) are turned off.

The holding units 102 (0) to 102 (k) include:
Signals A and B are supplied from external circuits, respectively. The signals A and B are 180 degrees out of phase. The holding units 102 (0) to 102 (k) of each bit are turned on / off by the signals A and B. Holder 102 (0) to 102 (k)
Input side is a buffer 103 (0) for output.
Ｋ (k) output terminals, and the output side is
Buffers 103 (0) to 103 (k) for signal output
Of the transfer units 101 (1) to 101 (k-
1) and the next-stage transfer section / signal generation circuit 105 (0) to
105 (k).

Effective timing detection circuits 104 (0) to 104 (1)
04 (k) detects the timing at which the holding units 102 (0) to 102 (k) are completely turned on according to the external signals A and B, respectively, and outputs a pulse. Outputs of the valid timing detection circuits 104 (0) to 104 (k) are input to transfer units / signal generation circuits 105 (0) to 105 (k), respectively. Further, the transfer units / signal generation circuits 105 (0) to 105 (0) to
5 (k), the valid timing detection circuit 104
In addition to the outputs of (0) to 104 (k), the current stage transfer unit 1
01 (1) to 101 (k−1), that is, “H”
Signals 108 (0) to 10 which are level signals
8 (k) and the transfer unit / signal generation circuit 105 in the next stage
(2) to 105 (k + 2) outputs are input.

Transfer unit / signal generation circuit 105 (0) -10
5 (k) are transfer units 101 (1) to 101 (k-
Output of 1) and valid timing detection circuits 104 (0) to 104 (1)
04 (k) is at the “H” level,
Successive transfer units / signal generation circuits (2) to 105 (k +
When the output of 2) is at the "H" level, an "H" level signal is output. As shown in FIG. 1, when a signal is transferred in the downward direction, this output signal is output from the switches 107 (0) to 107 (0).
(K), the transfer units 101 (1) to 101 (k) at the next stage
-1) and the transfer unit / signal generation circuit 105 (0) to
105 (k−2) and the next transfer unit 101
The on / off control of (1) to 101 (k-1) and the transfer unit / signal generation circuits (0) to 105 (k-2) two stages before are controlled.

The transfer units 101 (1) to 101 shown in FIG.
(K-1) and the holding units 102 (0) to 102 (k) are constituted by transfer gates or clocked inverters. Also, the valid timing detection circuit 104
(0) to 104 (k) are the holding units 102 when the external input signal A is at the “H” level and the external input signal B is at the “L” level.
When turning on (0) -102 (k), FIG.
As shown in (a) and (b), the inverters 201a and A
ND gate 202a or inverter 201b and A
ND gate 202b. Further, the transfer unit / signal generation circuit 105 (0) to 105 (k)
Is, as shown in FIGS. 3A and 3B, AND gate 2
03a and OR gate 204a or AND gate 2
03b and an OR gate 204b.

The effective timing detection circuit 104
(0) to 104 (k) and transfer unit / signal generation circuit 10
5 (0) to 105 (k) correspond to the inverter 301a and the three-input AND gate 30 as shown in FIGS.
2a and OR gate 303a or inverter 3
01b, a three-input AND gate 302b and an OR gate 303b.

B. Operation of Embodiment Next, the operation of this embodiment will be described in detail with reference to the timing chart shown in FIG. First, the operation of the scanning circuit shown in FIG. 1 when a signal is transferred in a downward direction will be described. When the external input signal A is at “L” level and the external input signal B is at “H” level, the holding unit 102 (2n−1)
Are turned on, and when the external input signal A is at the “H” level and the external input signal B is at the “L” level, the holding unit 102 (2
n) is turned on. Further, as shown in the timing chart of FIG. 5, the external input signals A and B have clock skew.

To transfer a signal in the downward direction, the switches 107 (0) to 107 (107) are controlled by transfer direction control signals S1 and S2.
(K) is turned on and switches 106 (0) to 106 (k)
Is off. When the signal 108 (2n-1) goes to the "H" level through the holding unit 102 (2n-1),
From the output 110 (2n-1), an "H" level pulse is output at the timing shown in FIG. The valid timing detection circuit 104 (2n-1) is connected to the holding unit 102 (2n-
A pulse is output at the timing when 1) is completely turned on. That is, when the external input signal A is at "L" and the external input signal B is at "H", a pulse of "H" level is output. This output signal is transmitted to the transfer unit / signal generation circuit 105 (2
n-1).

The transfer unit / signal generation circuit 105 (2n
-1) The other input is a signal 108 having the same potential as the current stage output.
(2n-1) and the transfer unit / signal generation circuit 105 (2n +
1) are supplied. The transfer unit / signal generation circuit 105 (2n-1)
(2n-1) and signal 108 (2n-1) are both "H".
Level and the transfer unit / signal generation circuit 10
When 5 (2n + 1) is at the “H” level, the “H” level is output. This output pulse is transmitted to the next transfer unit 101 (2
m), an “H” level pulse is input to the transfer unit 101 (2m).

The next-stage transfer section 101 (2m) is turned on when a pulse at the "H" level is input. At this time, since the holding unit 102 (2n-1) is also on, the output of the buffer of the holding unit 102 (2n-1) for transfer passes through the transfer unit 101 (2m), and the buffer 103
(2n). Therefore, at this time, 2n-1
The signal of the bit is transferred to the 2nth bit. This transfer is repeated up to 2n + 1 bits. The transfer unit / signal generation circuit 105 (2n-1)
Even when (2n + 1) is at the "H" level, an "H" level pulse is output.
05 (2n + 1) is at the “H” level,
An “H” level pulse is input to 1 (2 m). Until this pulse is input, the signal 108 (2n) is “H”.
Level, but the transfer unit / signal generation circuit 105
When the (2n + 1) pulse is input, the level changes from “H” level to “L” level. By repeating this transfer sequentially, it operates as a scanning circuit.

On the other hand, when transmitting signals upward,
The switches 106 (0) to (k) are turned on and the switches 107 (0) to (k) are turned off by the transfer direction control signal S2 obtained by inverting the level of the transfer direction control signal S1.
An “H” level signal 108 (2n) is transmitted from the transfer unit 101 (2m + 1) shown in FIG. A signal is output from the valid timing detection circuit 104 (2n) at the same timing as when the data is transferred in the downward direction, and is input to the transfer unit / signal generation circuit 105 (2n). The transfer unit / signal generation circuit 105 (2n) also receives the signal 108 (2n). When both the signal 108 (2n) and the valid timing detection circuit 104 (2n) are at “H” level,
An "H" level signal is output. The output of the transfer unit / signal generation circuit 105 (2n) is also supplied to the transfer unit (2m) through the switch 106 (2n). At this timing, the signal of the 2nth bit is transferred to the 2n-1th bit.
This transfer is sequentially repeated in the upward direction.

According to the above-described embodiment, the holding section 102
Since the transfer unit 101 does not turn on earlier, even if the clock skew of the external input signals A and B increases, an effect is obtained that the scanning circuit does not malfunction.

C. Another Embodiment Next, another embodiment of the present invention will be described. In the other embodiment, the basic configuration is the same as that of the above-described embodiment, but a scanning circuit in which the transfer direction may be unidirectional is provided. Here, FIG. 6 is a block diagram showing a configuration of a scanning circuit according to the other embodiment. In the figure, the transfer direction is downward. In the scanning circuit of FIG. 1 capable of bidirectional transfer, the output of the transfer unit / signal generation circuit 105 (2n) is transferred through the switch 106 (2n-1) to the transfer unit 101.
(2m), and connected to the transfer unit (2m + 1) through the switch 107 (2n-1). In the case of unidirectional signal transfer only, as shown in FIG.
The output of the signal generation circuit 105 (2n) is transmitted to the transfer unit (2m +
It is supplied directly to 1). The timing and operation of the scanning circuit shown in FIG. 6 are the same as in the case of the downward transfer in the above-described embodiment.

As described above, when the transfer direction of the signal may be a single direction, the operation margin for the clock skew of the external signal is increased and the signal of the external input signal can be further reduced. Can be created.

[0028]

As described above, according to the present invention,
Input to the holding unit from an external circuit by the detection unit
Based on the two-phase clock signal, the timing at which the holding unit at the preceding stage is completely turned on is detected, and the control unit detects
When it is detected that the previous- stage holding unit is completely turned on and the signal held in the previous- stage holding unit becomes valid, the current-stage transfer unit is activated, and the transfer unit activates the holding unit. Is transferred to the next stage, the transfer unit is always turned on after the holding unit, and even if the clock skew of the external signal increases, the scanning circuit may malfunction. Can be prevented. Furthermore, according to the present invention, since the signal to be input to the next-stage transfer unit is generated inside the scanning circuit, there is an advantage that an external input signal to the transfer unit is not required. In addition, since it is not necessary to reduce the clock skew of the signal input to the holding unit, there is an advantage that an external signal can be easily created.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a scanning circuit according to an embodiment of the present invention.

FIG. 2 is a block diagram illustrating a configuration of a scanning circuit according to the present embodiment.

FIG. 3 is an effective timing detection circuit according to the embodiment;
FIG. 3 is a circuit diagram illustrating a configuration example of a transfer unit / signal generation circuit.

FIG. 4 is an effective timing detection circuit according to the embodiment;
FIG. 9 is a circuit diagram illustrating another configuration example of the transfer unit / signal generation circuit.

FIG. 5 is a timing chart for explaining the operation of the scanning circuit according to the present embodiment.

FIG. 6 is a block diagram showing a configuration of a scanning circuit according to another embodiment of the present invention.

FIG. 7 is a circuit diagram showing a configuration of a scanning circuit according to a conventional technique.

FIG. 8 is a timing chart for explaining the operation of the scanning circuit according to the related art.

FIG. 9 is a circuit diagram showing a configuration of another scanning circuit according to the related art.

[Explanation of symbols]

 Reference Signs List 101 transfer unit 102 holding unit 103 buffer (output buffer) 104 effective timing detection circuit (detection unit) 105 transfer unit / signal generation circuit (control unit) 106 switch (control unit) 107 switch (control unit) 201a, 201b inverter (logic) Circuit) 202a, 202b AND gate (logic circuit) 203a, 203b AND gate (logic circuit) 204a, 204b OR gate (logic circuit) 301a, 301b Inverter (logic circuit) 302a, 302b 3-input AND gate (logic circuit) 303a, 303b OR gate (logic circuit)

──────────────────────────────────────────────────続 き Continued on the front page (58) Fields surveyed (Int. Cl. ⁷ , DB name) G09G 3/00-3/38 G02F 1/133 G11C 19/00

Claims (4)

(57) [Claims] 1. A holding unit that is formed integrally with a liquid crystal display panel and holds a signal, a transfer unit that transfers a signal held by the holding unit to a next stage, and outputs a signal held by the holding unit. It has a multi-stage circuit composed of output buffers,
A scanning circuit that sequentially turns on the transfer units in the plurality of stages according to a start pulse and sequentially transfers signals held in the holding unit to the next stage by the transfer unit; based on the two-phase clock signal <br/> No. to be, detection means for detecting a timing at which the front of the holding portion is fully on, by the detection means, preceding the holding portion is fully on Control means for outputting a signal for activating the transfer unit of the current stage when the signal held in the holding unit of the preceding stage becomes valid, and the transfer unit includes the control unit More active signal
When a scanning signal is input, the holding signal held in the holding unit is transferred to the next stage. 2. A transfer direction control unit for controlling a transfer direction of a signal held in the holding unit, wherein the control unit is activated based on a transfer direction determined by the transfer direction control unit. 2. The scanning circuit according to claim 1, wherein a transfer unit is determined. 3. The scanning circuit according to claim 1, wherein the control unit activates the transfer unit and activates a transfer unit at a stage immediately before the transfer unit. 4. The scanning circuit according to claim 1, wherein said detection means and said control means are constituted by a logic circuit integrally formed on said liquid crystal display panel.