JP3345396B2 - Interleave address generation device and interleave address generation method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an interleave address generation device and an interleave address generation method, and more particularly to an interleave address generation device and an interleave address generation method suitable for use in a communication terminal device or a base station device.

[0002]

2. Description of the Related Art Conventionally, as an interleave address generation device and an interleave address generation method, there is one described in Japanese Patent Application Laid-Open No. 7-212250.

[0003] Currently, a global standardization of the third generation communication system is being promoted, and a standardization plan regarding interleaving has been proposed. GF interleaving is one of the interleaving methods currently being studied.

[0004] This GF interleave has the number of rows N =
This is one of block interleaving that performs processing on a two-dimensional array having 2 ^r and the number of columns M = 2 ^c . GF interleaving
Bit exchange is performed in a different order (hereinafter, referred to as column exchange) on a bit sequence of length M divided for each row from the first row to the Nth row, and row exchange is performed in the order by the bit inversion method. , The interleaved address pattern is generated by reading each column from the first row of the first column to the Nth row of the Mth column from the first row of the first column. .

An example in which a column conversion pattern πi (j) is calculated to generate an interleave address pattern in the two-dimensional matrix of the block size will be described.

FIG. 14 is a block diagram showing a configuration of a conventional column switching device used for GF interleaving.

In FIG. 14, a memory 11 outputs a vector α ⁱ⁰ corresponding to an input row number i (0 ≦ i <N) to an exclusive OR calculator 13. The memory 12 outputs the vector α ^j corresponding to the input column number to j (0 ≦ j <M) to the exclusive OR calculator 13. The exclusive OR calculator 13 calculates the exclusive OR of α ⁱ⁰ and α ^j, and outputs the calculation result β to the memory 14.

The memory 14 stores an i-th memory based on the calculation result β.
Output the column conversion pattern π _i (j) for the row. π _i (j)
Is obtained from the following equation (1).

The conversion in the memory 11, the memory 12, and the memory 14 is performed using a conversion table shown in FIG.

FIG. 15 is a diagram showing a conversion table used for GF interleaving. In FIG. 15, the conversion table is a table in which the number of exponents of the Galois field is associated with the vector expression of the Galois field using a polynomial basis.

The vector expression is expressed in the memory 11 and the memory 1
2 and the vector input in the memory 14. Exponent number of exponent expression lo
g _α β is a value input from the memory 11 and the memory 12 and a value output from the memory 14.

Here, the column conversion pattern of the i-th row is obtained by the following operation. By obtaining the parameter i0 corresponding to the row number i in the memory 11, the parameter
A vector α ⁱ⁰ corresponding to ⁱ⁰ is output. The exclusive OR calculator 13 calculates the exclusive OR of α ⁱ⁰ and α ^j output from the memories 11 and 12, and the memory 14 outputs log _α β corresponding to the calculation result β.

By fixing the address value i of the memory 11 and incrementing the address value j of the memory 12 from 0, a column conversion pattern πi (j) for the i-th row is generated.

Next, an example of interleave address generation will be described. FIG. 16 is a diagram showing a process of generating an interleave address.

An example in which an interleave address pattern having a size of 30 is created on an 8 × 4 two-dimensional array will be described below.

First, the interleave address generating device stores an interleave address pattern in which addresses 0 to 7 are rearranged in the memory in the column direction (i = 0, j
= 0 to 7).

Similarly, the interleave address generation device stores the interleave address pattern obtained by rearranging the addresses 0 to 7 in different rearrangement manners from the next row on the memory (i = 1 to 3, j = 0 to 7). Respectively. The stored result is shown in FIG. 16A.

Next, the interleave address generation device performs a line-by-line replacement process. Specifically, the row of i = 1 and the row of i = 2 are interchanged. FIG. 16 shows the result of the replacement.
Shown in B.

Next, the interleave address generation device adds an offset address to the stored value on a row-by-row basis. Specifically, a value obtained by multiplying the value of i by the number of column components is added. For example, a value 16 obtained by multiplying the value 2 of i by the number 8 of components is added to the value of the second column. A value 8 obtained by multiplying the value 1 of i by the number 8 of the component is added to the value in the third column. A value 24 obtained by multiplying the value 3 of i by the number 8 of the component is added to the value of the fourth column. FIG. 16C shows the addition result.

Next, the interleave address generator fetches addresses from the memory in the column direction and outputs only addresses smaller than the size of the interleave address pattern to be created. Specifically, in FIG. 16C, the value 7 stored at i = 0 and j = 0 is output, and then i =
2, the value 20 stored at j = 0, the value 14 stored at i = 1, j = 0, the value 29 stored at i = 3, j = 0 are output. Then, the value 3 stored at i = 0, j = 1 is output, and then the value 22, i = 1, stored at i = 2, j = 1.
The value stored in j = 1, i = 3, and the value stored in j = 1 are output. Similarly, the interleave address generation device extracts the values stored in the memory in the column direction and outputs the values as an interleave address pattern. FIG. 16D shows the output interleave address pattern.

[0021]

However, in the conventional interleave address generation method, the interleave address pattern generated in a predetermined unit is developed in the memory, and then the interleaving process of the rows and the addition of the offset address are performed. There is a problem that a large memory space and a long processing time are required to generate a rib address pattern.

An object of the present invention is to provide an interleave address generation device and an interleave address generation method for generating an interleave address pattern in a small memory space and a short processing time.

[0023]

According to the present invention, there is provided an interleaved address generating apparatus for generating data represented by a matrix two-dimensional array.
In the block interleaving method that rearranges
A counter that outputs the row and column numbers of the two-dimensional array,
Bit inverting means for inverting the bit of the line number;
Address corresponding to the row number and column number reversed
Column conversion means for outputting a value as a column conversion value;
Bit offset of the inverted row number to address offset
Shift register means for outputting a
Adding means for adding the offset value and the column exchange value
And compares the sum with the interleave size to determine
The added value within the turbulent size is output as the address value.
And a means for comparing the size of each other .

In the interleave address generating apparatus according to the present invention, the block interleave method may include
Is the number of rows N and the number of columns M, N
Go to the column, and from the initial value 0 to 1
For the matrix of the incremented numbers, the first
A different column exchange is performed for each row from the row to the Nth row.
Line exchange with a predetermined random pattern
Each column from the first row of the first column
By reading down to the Mth column and the Nth row
The read-out address signal is used as the read address signal.
It adopts a configuration that is a turive system .

In the interleave address generating apparatus according to the present invention, the column exchange means may be configured to execute the conversion based on the bit number of the inverted bit.
First storage means for storing a unique constant value for each row;
Second storage means for storing a unique constant number for each column;
Performs an exclusive OR operation on the stored row numbers and column numbers
Exclusive-OR operation means, and calculating the exclusive-OR operation result.
And a third storage means for storing as an address value .

[0026]

According to these configurations, the row number and the column number are individually output and the numbers are individually converted, so that the row rearranging process and the column rearranging process can be performed in parallel. Therefore, an interleaved address pattern can be generated with a small memory space and a short processing time.

The interleave address generating apparatus of the present invention temporarily stores the bit-inverted row number,
The storage cell array output to the shift register means is
The configuration provided for them is adopted.

According to this configuration, the memory cell array is used.
By delaying the output timing of the address offset value, the output timing of the adding means can be matched, so that even if the generation speed of the address offset value and the generation speed of the column exchange pattern are different, it is possible to generate the interleaved address pattern. it can.

[0030]

[0031]

[0032]

[0033]

[0034]

[0035]

[0036]

[0037]

[0038]

[0039]

[0040]

[0041]

[0042]

[0043]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The gist of the present invention is that, in the generation of an interleave address, a row rearranging process and a column rearranging process are performed in parallel, and the row rearranging process, the column rearranging process, and the offset are performed. This is to create an interleaved address by continuously performing address addition processing.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(Embodiment 1) The interleave address generation device of Embodiment 1 performs a row rearrangement process and a column rearrangement process in parallel.

FIG. 1 is a block diagram showing a configuration of an interleaved address generation device according to Embodiment 1 of the present invention.

The interleave address generator 100 shown in FIG. 1 includes a counter control unit 101 and a bit inversion unit 1
02, a column conversion unit 103, a shift register 104,
It is mainly composed of an adder 105 and a magnitude comparison unit 106.

Further, the column conversion unit 103 includes a memory 110
, A memory 111, a memory 113, and an exclusive OR operator 112.

In FIG. 1, the counter control unit 101
The row number i (0 ≦ i <2 ² ) of the two-dimensional array is replaced with the bit inversion unit 1
02, and outputs the column number j (0 ≦ j <2 ³ ) of the two-dimensional array to the memory 111.

For example, the counter control unit 101 has 2 ² ×
When outputting an address of 2 ³ two-dimensional array, the row number i
= 0, column number j = 0, and then row number i = 1 and column number j = 0. Thereafter, row number i = 2 and column number j = 0 are output, and row number i = 3 and column number j = 0 are output.

Next, a row number i = 0 and a column number j = 1 are output. In this way, every time the value of the row number i exceeds the maximum value 3, the value of the column number j is increased, i = 0 is set and output,
Output up to the combination of row number i = 3 and column number j = 7.

The bit inversion section 102 is a counter control section 1
01 is bit-inverted in a binary number state, and the row number i ′ obtained by bit inversion is stored in the memory 11.
0 is output to the shift register 104. Specifically, the bit inverting unit 102 exchanges the upper digit and the lower digit of the binary-coded row number. That is, the values of the most significant digit and the least significant digit are exchanged, and the second most significant digit and the second least significant digit are exchanged. Hereinafter, similarly, the upper digit and the lower digit are interchanged.

The memory 110 stores a value obtained by substituting a different i0 into α ⁱ⁰ in each row, obtains i0 corresponding to the input i ′, and outputs α ⁱ⁰ corresponding to ⁱ⁰ to the exclusive OR calculator 112. I do.

The memory 111 stores a different j in each row as α ^j (0
≦ j <M), and outputs α ^j corresponding to the input ^j to the exclusive OR calculator 112.

The exclusive OR operation unit 112 includes the memory 11
The exclusive OR of α ⁱ⁰ output from 0 and α ^j output from the memory 111 is calculated, and the calculation result is stored in the memory 1
13 is output.

The memory 113 stores the exclusive OR operation unit 11
2 is stored, and the column exchange pattern corresponding to the input calculation result is added to the adder 10.
5 is output.

The shift register 104 includes a bit inversion unit 1
The output value from the bit number 02 is bit-shifted and output to the adder 105 as an address offset value.

The adder 105 adds the output from the shift register 104 and the output from the column conversion unit 103, and outputs the addition result to the magnitude comparison unit 106.

The magnitude comparison unit 106 compares the addition result output from the adder 105 with the interleave size, and outputs the addition result within the interleave size as an address value.

Next, data processing in the interleave address generation device of the present embodiment will be described.

In the following description, the interleave size L
= 30, N (= 2 ^r ) × M (= 2 ^c ) block size r
= 2, C = 3, the primitive polynomial of degree 3 represented by the Galois field GF (23) is x ³ + x + 1, and the root of the primitive polynomial is α
An example will be described. In addition, all elements on the Galois field GF (23) can be represented by powers of α.

FIG. 2 is a diagram showing an example of the data structure in the exclusive OR operation of this embodiment.

The memory 110 stores a parameter i0 corresponding to the row number i and a 3-bit vector α ^{i0 in association} with each other, and outputs a 3-bit vector α ⁱ⁰ corresponding to the input ⁱ⁰ .

The memory 111 stores the parameter j corresponding to the row number i and α ^{j in association} with each other, and outputs a 3-bit vector α ^j corresponding to the input ^j .

The exclusive OR operation of the vector α ⁱ⁰ and the vector α ^j is performed in the exclusive OR operation unit 112, and the operation result β is output to the memory 113.

In memory 113, column replacement data corresponding to operation result β is output.

Next, data processing of the interleave address generation device according to the present embodiment will be described. FIG.
FIG. 3 is a diagram showing an example of creating an interleaved address.

In FIG. 3, i and j indicate a row number and a column number output from the counter control unit 101, and i ′
Indicates a row number output from the bit inversion unit 102.
Α ⁱ⁰ and α ^j are the memory 110 and the memory 111
And α ⁱ⁰ + α ^j are represented by
The calculation result in the exclusive OR calculator 112 is shown. l
og _α α ⁱ⁰ + α ^j indicates data output from the memory 113, and the offset addition result indicates the result of adding the offset address output from the shift register 104 in the adder 105. The data processing is performed for each row from the upper row.

First, in the counter control unit 101,
The row number i = 0 and the column number j = 0 are output. Line number i
Is output after the bits of the row number in the binary number state are exchanged between the upper and lower bits in the bit inverting unit 102. The row number i = 0 is “00” when represented by a 2-bit binary number,
When the upper bit and the lower bit are exchanged, it becomes “00”, and the row number i ′ = 0 is output.

In memory 110, α ⁱ⁰ corresponding to row number i ′ is output. When the row number i ′ = 0 is input, α ⁱ⁰ = (1, 0, 0) is output.

In memory 111, α ^j corresponding to row number ^j is output. When the line number j = 0 is input,
α ^j = (1, 0, 0) is output.

The exclusive OR calculator 112 calculates the exclusive OR of α ⁱ⁰ output from the memory 110 and α ^j output from the memory 111. α ⁱ⁰ = (1,
0,0) and α ^j = (1,0,0), α ⁱ⁰ + α ^j =
(0,0,0) is output.

In the memory 113, an exclusive OR operation is performed.
Calculation result α output from the unit 112 ⁱ⁰+ Α^jCorresponding to
Column replacement data log_α(Αⁱ⁰+ Α^j) Is output
You. αⁱ⁰+ Α^j= (0, 0, 0), column replacement data
4 is output as data.

In adder 105, a value obtained by multiplying the total number of column numbers j by i ′ is added to the column replacement data, and the addition result is output. Column replacement data is 4, i ′ = 0,
When the number of the column number j is 8, 7 is output as the interlib address.

After the interleave address for i = 1 and j = 0 is output, the counter control unit 101
The row number i = 1 and the column number j = 0 are output, the same processing as described above is performed, and 20 is output as the interlib address.

Hereinafter, processing when i = 2 and j = 0, i =
3, the processing when j = 0 is performed. When i = 3 and i exceeds the maximum value, j is incremented, the value is reset to i = 0, and then the process for i = 0 and j = 1 is performed.

[0077] sequential address in the column direction with respect to this way, the interleave address generation apparatus, by i is controlled to i each exceeds the maximum value is reset, 2 ² La 2 ³ two-dimensional array Is output. Further, since the interleave address generation device uses the output i ′ from the bit inversion unit 102 as a read address value for the memory 110, the interleave address generation device can simultaneously perform row exchange in the two-dimensional array.

As described above, according to the interleave address generating apparatus of the first embodiment, the row number and the column number are individually output and the numbers are individually converted, whereby the row rearranging process and the column rearranging are performed. Since the replacement process can be performed in parallel, an interleaved address pattern can be generated with a small memory space and a short processing time.

In the above description, the size of the interlibrary address pattern is 30 and the block size is 2 ² 2 ³
Is described, the change of the memory data to be stored and the number of shifts of the shift register 104 are set to c bits, so that N (2 ^r ) × M (2 ^c ) Block interleaving can be performed.

(Embodiment 2) FIG. 4 is a block diagram showing an example of the configuration of an interleaved address generation device according to Embodiment 2. However, the same components as those in FIG. 1 are denoted by the same reference numerals as those in FIG. 1, and the detailed description is omitted.

The interleave address generator 1 shown in FIG.
50 is different from FIG. 1 in that it has a storage cell array 151 and adds an offset address in accordance with the output timing from the memory 113.

In FIG. 4, the storage cell array 151
After temporarily storing the row number i ′ output from the bit inversion unit 102, the row number i ′ is output to the shift register 104.

For example, the storage cell array 151 converts the output value i ′ from the bit inversion section 102 into the column conversion section 10.
In order to match the output from the shift register 104 with the output from the shift register 104, the shift register 104 is constituted by a two-stage memory cell array.

The output value i ′ from the bit inverting unit 102 is temporarily stored in the storage cell array 151, sequentially output in accordance with the addition timing in the adder 105, input to the shift register 104, and shifted by 3 bits. The value is output as the address offset value for the i'th line.

As described above, according to the interleave address generating apparatus of the second embodiment, the row number and the column number are individually output and the numbers are individually converted, whereby the row rearranging process and the column rearranging are performed. Since the replacement process can be performed in parallel, an interleaved address pattern can be generated with a small memory space and a short processing time.

Further, according to the interleave address generating device of the second embodiment, the output timing of the adder can be adjusted by delaying the output timing of the offset address value using the temporary storage circuit, so that the offset address can be adjusted. Even when the generation speed of the value and the generation speed of the column exchange pattern are different, the interleave address pattern can be generated.

(Embodiment 3) FIG. 5 is a block diagram showing an example of the configuration of an interleaved address generating apparatus 200 according to Embodiment 3.

In FIG. 5, the counter control unit 201
The row number i of the two-dimensional array is output to the memory 202, and the column number j of the two-dimensional array is output to the memory 203.

The memory 202 stores N (i) corresponding to the input i and outputs N (i) corresponding to i output from the counter control unit 201 to the multiplier 204.

The memory 203 stores M (j) corresponding to the input j and outputs M (j) corresponding to j output from the counter control unit 201 to the adder 205.

Multiplier 204 multiplies N (i) output from memory 202 by the number of columns M, and outputs the multiplication result to adder 20.
5 is output.

The adder 205 adds the multiplication result output from the multiplier 204 to M (j) output from the memory 203, and outputs the addition result to the magnitude comparison unit 206.

If the addition result output from adder 205 is smaller than the requested interleave address size, magnitude comparison section 206 outputs the addition result as an interleave address, and the addition result is equal to or larger than the requested interleave address size. In the case of, the addition result is not output.

Next, the conversion operation of the memory 202 will be described. FIG. 6 is a diagram illustrating an example of a table stored in the memory 202.

In FIG. 6, N (i) is an output corresponding to the input i, i and N (i) correspond one-to-one, and N (i) corresponding to different i has different values from each other. Take.

When i = 0 is input to the memory 202,
N (i) = 2 is output. When i = 1 is input, the memory 202 outputs N (i) = 3. When i = 2 is input, the memory 202 outputs N (i) = 0. When i = 3 is input, the memory 202 outputs N (i) = 1.

Next, the conversion operation of the memory 203 will be described. FIG. 7 is a diagram illustrating an example of a table stored in the memory 203.

In FIG. 7, M (j) is an output corresponding to the input j, j and M (j) correspond one-to-one, and M (j) corresponding to different j has different values from each other. Take.

When j = 0 is input to the memory 203,
M (j) = 3 is output. When j = 1 is input, the memory 202 outputs M (j) = 6. When j = 2 is input, the memory 202 outputs M (j) = 4. When j = 3 is input, the memory 202 outputs M (j) = 2. Similarly, when i = 4 to 7, M (j) corresponding to j is output according to the table of FIG.

Next, an example of interleave address generation will be described.

FIG. 8 is a diagram showing an example of interleave address generation. FIG. 8A is a diagram illustrating an example of a row number i and a column number j output from the counter control unit 201.

When outputting a 2 ² × 2 ³ two-dimensional array address, the counter control unit 201 outputs a row number i = 0 and a column number j = 0, and then outputs a row number i = 1 and a column number i = 1. Number j = 0
Is output. Thereafter, row number i = 2 and column number j = 0 are output, and row number i = 3 and column number j = 0 are output.

Next, a row number i = 0 and a column number j = 1 are output. In this way, every time the value of the row number i exceeds the maximum value 3, the value of the column number j is increased, and i = 0 is set and output.
Output up to the combination of row number i = 3 and column number j = 7.

FIG. 8B is a diagram showing an example of converted row numbers and column numbers. The row number i output from the counter control unit 201 is converted into N (i) according to the table in FIG. 6, and the column number j is converted into M according to the conversion table in FIG.
(J).

For example, when the row number i = 0 and the column number j = 0 are output from the counter control unit 201, the memory 202
Output N (i) = 2 from the memory 203
(J) = 3 is output.

FIG. 8C is a diagram showing an example of the addition result output from adder 205. In the adder 205, N
A value obtained by adding M (j) to the result of multiplying (i) by the number of columns is output.

For example, when N (i) = 2 and M (j) = 3, a value 19 obtained by multiplying the number of columns 8 by N (i) and adding M (j) is output.

In the size comparison section 206, a value smaller than the requested interleave address size is output as the interleave address from the addition results in FIG. 8C.

FIG. 8D shows an interleave address device 2
It is a figure showing an example of an interleave address outputted from 00.

For example, when the size of the requested interleave address is 30, an addition result whose value is 29 or less is output as an interleave address, and a value whose addition result is 30 or more is not output.

As described above, according to the interleave address generating apparatus of the third embodiment, the row rearranging process and the column rearranging process are performed in parallel, and the row rearranging process and the column rearranging process are performed. By continuously performing the offset address addition processing, an interleaved address pattern can be generated with a small memory space and a short processing time.

Further, according to the interleave address generation device of the third embodiment, compared to the first or second embodiment, the same column exchange pattern is used for each row, so that an interleave address can be generated with a simple configuration. can do.

(Embodiment 4) FIG.9 is a block diagram showing a configuration of an interleaving apparatus according to Embodiment 4 of the present invention.

In FIG. 9, interleave address generating device 301 stores an interleave address pattern in memory 302 in accordance with an input instruction for inputting data to the memory.
Output to The interleave address generation device 3
Reference numeral 01 mainly includes the interleaved address generation device according to the first, second, or third embodiment.

The address counter 303 outputs the data to the memory 302 in order from the top address of the memory in accordance with the data output instruction for outputting data.

The memory 302 sequentially stores data at the addresses output from the interleave address generator 301, and after storing predetermined data, sequentially outputs the data at the addresses output from the address counter 303.

As described above, according to the interleave device of the present embodiment, the information sequence is generated using the interleave address pattern generated by the interleave address generation device of the first, second, or third embodiment. , It is possible to perform high-speed interleave processing with a small amount of memory.

In the interleave device of the fourth embodiment, data is stored in the memory at the address output from interleave address generator 301, and data is read from the memory at the address output from address counter 303. Alternatively, the data may be stored in the memory at the address output from the address counter 303, and the data may be read from the memory at the address output from the interleave address generator 301 to rearrange the data.

(Embodiment 5) FIG.10 is a block diagram showing a configuration of a turbo encoding apparatus according to Embodiment 5 of the present invention.

In FIG. 10, turbo coding apparatus 400
Is a recursive convolutional encoder 401 and an interleaver 40
2 and a recursive convolutional encoder 403.

The recursive convolutional encoder 401 encodes the input information sequence with a convolutional code, and outputs the encoded information sequence to the outside.

Interleaver 402 is configured by the interleaver of the fourth embodiment, performs an interleave process on an input information sequence, and outputs the interleaved information sequence to recursive convolutional encoder 403.

Recursive convolutional encoder 403 encodes the information sequence output from interleaver 402 with a convolutional code, and outputs the encoded information sequence to the outside.

Next, the operation of turbo coding apparatus 400 will be described.

The input information sequence is subjected to convolutional encoding in a recursive convolutional encoder 401, and the encoded information sequence is output.

The input information sequence is subjected to data rearrangement in interleaver 402, and the rearranged information sequence is subjected to convolutional coding in recursive convolutional encoder 403, and is coded. An information sequence is output.

In other words, the information sequence to be coded includes an output of the information sequence itself, an output from a recursive convolutional encoder 401 for encoding the convolutional code using the information sequence as an input, and an information sequence as an input. Before inputting the data to the recursive convolutional encoder 403, the data is written to the memory once, and the data is rearranged by the interleaver 402, and the rearranged data is input to encode the convolutional code. Three bits combined with the output from the convolutional encoder 403 are output as a code sequence for one bit of the information sequence.

By the above operation, turbo encoding device 40
At 0, the input information sequence, the convolutionally coded information sequence, and the information sequence on which the data is rearranged and convolutionally coded are output in response to the input of the information sequence.

As described above, according to the turbo coding apparatus of the present embodiment, the processing can be performed at high speed by rearranging the information sequence in the interleave apparatus of the fourth embodiment. You can improve your ability.

For example, in turbo encoding apparatus 400 according to the fifth embodiment, by using the interleave apparatus according to the fourth embodiment of the GF interleave system for interleaver 402, decoding of a code sequence on the reception side is possible. And a turbo coding apparatus 400 having an improved error correction capability.
Can be realized.

Further, according to the turbo coding apparatus of the present embodiment, the interleaving apparatus of Embodiment 4 rearranges the information sequence, thereby quickly generating an interleave address with a small memory and performing interleaving. Therefore, turbo coding can be performed with a small memory.

(Embodiment 6) FIG.11 is a block diagram showing a configuration of a turbo decoding apparatus according to Embodiment 6 of the present invention.

In FIG. 11, turbo decoding device 500
Is a soft output decoder 501, an interleaver 502,
It mainly comprises a soft output decoder 503 and a deinterleaver 504.

The soft output decoder 501 decodes the input code sequence and outputs it to the interleaver 502.

The interleaver 502 has the soft output decoder 5
The code sequence output from 01 is rearranged and output to the soft output decoder 503.

The soft output decoder 503 includes the interleaver 5
02 is decoded and output to the deinterleaver 504.

Deinterleaver 504 rearranges the code sequence output from soft output decoder 503 and outputs the obtained code sequence to soft output decoder 501 and the outside.

Next, the operation of turbo decoding apparatus 500 will be described.

In the first operation, a code sequence convolutionally coded by the turbo coding device of the fifth embodiment or the like is decoded in soft output decoder 501, and the obtained soft decision output is output to interleaver 502. Is done.

The soft-decision output output from soft-output decoder 501 is reordered in interleaver 502 in data sequence, and output to soft-output decoder 503.

The data sequence output from interleaver 502 is decoded together with the information sequence received by soft output decoder 503, and the obtained soft decision output is output to deinterleaver 504.

The soft decision output output from soft output decoder 503 is subjected to data rearrangement in deinterleaver 504, and the rearranged data sequence is output to soft output decoder 501 and the outside.

The data sequence output from deinterleaver 504 is output to soft output decoder 501 and used as reliability information in the second and subsequent turbo decoding processes.

In the operation of the turbo decoding process after the second time,
A convolutionally coded code sequence is output to a soft output decoder 501.
In, decoding is performed using the data sequence output from the deinterleaver 504 as reliability information, and the obtained soft decision output is output to the interleaver 502.

As described above, according to the turbo decoding apparatus of the present embodiment, high-speed processing can be performed by rearranging information sequences in the interleave apparatus of the fourth embodiment. You can improve your ability.

For example, in the turbo decoding apparatus 500 according to the sixth embodiment, the interleaver 502 and the deinterleaver 504 use the interleave apparatus according to the fourth embodiment, so that the turbo 500 can be realized.

Further, according to the turbo decoding apparatus of the present embodiment, since the information sequence is rearranged by the interleave apparatus of the fourth embodiment, the memory required for processing can be reduced. Can perform turbo coding.

(Embodiment 7) FIG.12 is a block diagram showing a configuration of a communication terminal apparatus according to Embodiment 7 of the present invention.

Referring to FIG. 12, communication terminal apparatus 600 includes:
An antenna 601, a receiving unit 602, a transmitting unit 603,
Demodulation section 604, modulation section 605, decoding processing section 606
, An encoding processing unit 607, and an audio codec unit 608
, A data input / output unit 609, a speaker 610, and a microphone 611.

The decoding processing section 606 comprises a deinterleave section 614, a rate matching section 615, and an error correction decoding section 616.

The coding processing section 607 includes an error correction coding section 617, a rate matching section 618, and an interleave section 619.

Here, error correction coding section 617 is configured using interleaving apparatus of Embodiment 4 or turbo coding apparatus 400 of Embodiment 5.

Further, error correction decoding section 616 is configured using non-speech data using interleave apparatus according to the fourth embodiment or turbo decoding apparatus 500 according to the sixth embodiment.

Further, deinterleave section 614 and interleave section 619 are configured using the interleave apparatus of the fourth embodiment.

The antenna 601 transmits and receives a signal. Receiving section 602 performs wireless processing on a signal received from antenna 601 and outputs the received signal after wireless processing to demodulation section 604. The transmitting section 603 performs radio processing on the transmission signal output from the modulation section 605, and
Send to 1.

Demodulation section 604 demodulates the received signal output from reception section 602 using despreading section 612 and outputs the demodulated signal to deinterleave section 614. Modulation unit 60
5 modulates the transmission signal output from interleaving section 619 using spreading section 613 and outputs the result to transmitting section 603.

The de-interleave section 614 includes the demodulation section 60
4 performs a data rearrangement process on the demodulated signal output from the demodulator 4 and outputs the rearranged data to the rate matching unit 61.
5 is output.

Rate matching section 615 adjusts the length of the data output from deinterleave section 614 to a length that allows error correction processing, and outputs the adjusted data to error correction decoding section 616. I do.

An error correction decoding section 616 performs error correction on the data output from the rate matching section 615,
The data after the error correction is output to audio codec section 608.

[0160] Error correction coding section 617 performs error correction coding on the transmission data output from voice codec section 608, and outputs the result to rate matching section 618.

[0161] Rate matching section 618 adjusts the transmission data output from error correction coding section 617 to a length required for interleaving processing, and sets interleave section 619.
Output to

[0162] Interleaving section 619 performs rearrangement processing on the transmission data output from rate matching section 618, and outputs the result to modulation section 605.

The audio codec 608 includes a microphone 611
Is encoded and output to the error correction encoding unit 617 as transmission data. Further, audio codec section 608 decodes the received data output from error correction decoding section 616, and outputs the decoded audio data to speaker 610.

Microphone 611 outputs the input voice to voice codec section 608 as voice data. The speaker 610 outputs audio data output from the audio codec unit 608 as audio.

Next, the operation of communication terminal apparatus 600 at the time of transmission will be described. When transmitting voice, the voice is analog-to-digital converted (hereinafter, referred to as “AD conversion”) into a voice signal by the microphone 611, output to the voice codec unit 608, coded by the voice codec unit 608, and encoded by the error correction coding unit. At 617, the data is convolutionally coded and output to the rate matching unit 618 as transmission data.

When transmitting non-speech data, the non-speech data is subjected to turbo coding and convolutional coding in accordance with the data transfer rate in error correction coding section 617 via data input / output section 609, The data is output to rate matching section 618 as transmission data.

The transmission data is sent to the rate matching unit 618.
Is adjusted to the length required for interleaving,
The interleaving unit 619 rearranges the data,
Digital modulation and digital-to-analog conversion (hereinafter referred to as DA conversion) are performed in a modulation unit 605, wirelessly processed in a transmission unit 603, and transmitted via an antenna 601.

Next, the operation of communication terminal apparatus 600 at the time of reception will be described.

The received signal is received via an antenna 601 and subjected to radio processing and AD conversion in a receiving section 602.
The signal is digitally demodulated in demodulation section 604 and output to deinterleave section 614 as received data.

The received data is supplied to a deinterleave section 614.
And the rate matching unit 615
Is adjusted to a length that allows error correction, and is output to the error correction decoding unit 616.

When the received data is an audio signal, the received data is Viterbi-decoded by error correction decoding section 616, and is subjected to audio decoding and D decoding by audio codec section 608.
The signal is A-converted and output as a sound from the speaker 610.

When the received data is a non-speech signal, error correction decoding section 616 performs turbo decoding according to the data transfer rate, and outputs the data via data input / output section 609 to the outside.

As described above, according to the communication terminal apparatus of the present embodiment, the turbo code using the interleave apparatus of the fourth embodiment as the error correction coding apparatus and the error correction decoding apparatus for non-voice data. By using a decoding device and a turbo decoding device, a lower Bi
Transmission and reception can be performed with high transmission quality communication characteristics of t to Error Rate.

Further, the configuration of the interleaver included in the turbo code and decoding can be performed at a high speed, and is constituted by an interleaver having a reduced memory amount.
It is possible to obtain communication terminal apparatus 600 in which interleaving is performed at high speed and the amount of memory is reduced.

Although the present embodiment describes an example in which the present invention is applied to CDMA communication, the communication method is not limited to this, and spreading section 613 in modulation section 605 and despreading section in demodulation section 604 are used. By replacing 612 with a modulation and demodulation device corresponding to the communication system, it can be applied to other communication systems.

(Embodiment 8) FIG.13 is a block diagram showing a configuration of a base station apparatus according to Embodiment 8 of the present invention.

Base station apparatus 700 shown in FIG. 13 includes antenna 701, receiving section 702, transmitting section 703, demodulating section 704, modulating section 705, decoding processing section 706, and encoding processing section 707. , And a data input / output unit 708.

The decoding processing section 706 comprises a deinterleave section 709, a rate matching section 710 and an error correction decoding section 711.

The coding processing section 707 includes an error correction coding section 712, a rate matching section 713, and an interleave section 714.

Here, error correction coding section 712 is provided for interleaved address generating apparatus 100 or 200 according to the first embodiment, or turbo coding apparatus 400 according to the fourth embodiment.
It is configured using

The error correction decoding section 711 is configured using the interleave device according to the fourth embodiment or the turbo decoding device 500 according to the fifth embodiment for non-voice data.

The deinterleave section 709 and the interleave section 714 are configured using the interleave device of the fourth embodiment.

An antenna 701 performs transmission and reception of a signal. A reception section 702 performs radio processing on a reception signal from the antenna 701 and outputs the reception signal to a demodulation section 704. Transmission section 703 performs radio processing on the transmission signal output from modulation section 705 and outputs the result to antenna 701.

Demodulation section 704 demodulates the received signal output from reception section 702 using despreading section 715 and outputs the demodulated signal to deinterleave section 709.
Modulates the transmission signal output from interleaving section 714 using spreading section 716 and outputs the result to transmitting section 703.

The de-interleave section 709 includes a demodulation section 70
4 is rearranged for the demodulated signal output from the fourth demodulation signal, and the rearranged data is processed by the rate matching unit 71.
Output to 0.

Rate matching section 710 adjusts the length of the data output from deinterleave section 709 to a length that allows error correction processing, and outputs the adjusted data to error correction decoding section 711. I do.

The error correction decoding section 711 decodes and error corrects the data output from the rate matching section 710, and outputs the data after error correction to the data input / output section 708.
Output to

Error correction coding section 712 performs error correction coding on the transmission data output from data input / output section 708 and outputs the result to rate matching section 713.

[0189] Rate matching section 713 adjusts the transmission data output from error correction coding section 712 to a length required for the interleave processing, and sets interleave section 714.
Output to

[0190] Interleaving section 714 performs rearrangement processing on the transmission data output from rate matching section 713 and outputs the result to modulation section 705.

Data input / output section 708 outputs data to be transmitted to error correction encoding section 712, and outputs received data output from error correction decoding section 711 to the outside.

Next, the operation at the time of transmission of base station apparatus 700 will be described.

Transmission data is turbo-coded and convolutionally coded according to the data transfer speed or type in error correction coding section 712 via data input / output section 708 and output to rate matching section 713 as transmission data. Is done.

The transmission data is sent to the rate matching unit 713
Is adjusted to the length required for interleaving,
The rearrangement processing is performed in the interleave section 714,
Digital modulation and DA conversion are performed in the modulation unit 705, wirelessly processed in the transmission unit 703, and transmitted via the antenna 701.

Next, the operation of base station apparatus 700 at the time of reception will be described. The received signal is received via an antenna 701, subjected to radio processing and AD conversion in a receiving section 702, digitally demodulated in a demodulating section 704, and output to a deinterleave section 709 as received data.

The received data is supplied to a deinterleave section 709.
And the rate matching unit 710
Is adjusted to a length that allows error correction, and is output to the error correction decoding unit 711.

The received data is turbo-decoded in error correction decoding section 711 according to the data transfer rate.
The data is output to the outside via the data input / output unit 708.

As described above, according to the base station apparatus of the present embodiment, the error correcting coding apparatus and the error correcting decoding apparatus are provided with the turbo coding apparatus and the turbo coding apparatus using the interleave address generating apparatus of the first embodiment. By using the decoding device, transmission and reception can be performed with lower bit to error rate and higher transmission quality communication characteristics.

For example, base station apparatus 700 according to the eighth embodiment
According to the above, the error correction encoding unit 712 is provided with the turbo encoding device 400 of the fifth embodiment, and the error correction decoding unit 71
By using the turbo decoding apparatus 500 according to the sixth embodiment for the first aspect, it is possible to obtain the base station apparatus 700 having lower BER and higher transmission quality communication characteristics for non-voice communication.

Further, the configuration of the interleaver included in the turbo code and the decoding is capable of high-speed processing, and is configured by an interleave device with a reduced amount of memory. An apparatus 700 can be obtained.

Although the present embodiment describes an example applied to CDMA communication, the communication method is not limited to this, and spreading section 716 in modulation section 705 and despreading section in demodulation section 704 are used. By replacing 715 with a modulator and a demodulator corresponding to each communication system, it can be applied to other communication systems.

[0202]

As described above, according to the interleave address generation apparatus and the interleave address generation method of the present invention, an interleave address pattern can be generated in a small memory space and a short processing time.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an interleave address generation device according to a first embodiment of the present invention.

FIG. 2 is a diagram showing an example of a data configuration in an exclusive OR operation according to the embodiment.

FIG. 3 is a diagram showing an example of creating an interleaved address;

FIG. 4 is a block diagram showing a configuration example of an interleave address generation device according to a second embodiment;

FIG. 5 is a block diagram showing a configuration example of an interleave address generation device according to a third embodiment;

FIG. 6 shows an example of a table stored in a memory.

FIG. 7 illustrates an example of a table stored in a memory.

FIG. 8 is a diagram showing an example of interleave address generation.

FIG. 9 is a block diagram showing a configuration of an interleaving apparatus according to Embodiment 4 of the present invention.

FIG. 10 is a block diagram showing a configuration of a turbo encoding device according to Embodiment 5 of the present invention.

FIG. 11 is a block diagram showing a configuration of a turbo decoding device according to Embodiment 6 of the present invention.

FIG. 12 is a block diagram showing a configuration of a communication terminal device according to Embodiment 7 of the present invention.

FIG. 13 is a block diagram showing a configuration of a base station apparatus according to Embodiment 8 of the present invention.

FIG. 14 is a block diagram showing a configuration of a conventional column switching device used for GF interleaving.

FIG. 15 is a diagram showing a conversion table used for GF interleaving;

FIG. 16 is a diagram showing a process of generating an interleaved address.

[Explanation of symbols]

100, 150, 200, 301 Interleave address generation device 101, 201 Counter control unit 102 Bit inversion unit 103 Column conversion unit 104 Shift register 105, 205 Adder 106, 206 Size comparison unit 110, 111, 113, 202, 203, 302 Memory 112 Exclusive OR operation unit 151 Storage cell array 204 Multiplier 303 Address counter

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-8-279766 (JP, A) JP-A-2001-267934 (JP, A) JP3257984 (JP, B2) Table 9-511377 (JP, A) (58) Fields surveyed (Int. Cl. ⁷ , DB name) H03M 13/00 H04L 1/00

Claims (10)

(57) [Claims] 1. An arrangement of data represented by a matrix two-dimensional array
Dimensions in Block Interleaving with Interchange
A counter that outputs the row number and column number of the array;
Bit inverting means for inverting a bit of a signal;
The row number and the address value corresponding to the column number
Column conversion means for outputting as a conversion value;
Bit number of the row number
Shift register means for outputting the address
Adding means for adding the set value and the column exchange value;
Compare the sum with the interleave size and
Output the added value within the size as an address value.
An interleave address generation device , comprising: a small comparison unit . 2. The apparatus according to claim 1 , wherein said bit inverting means comprises a counter.
The upper and lower bits based on the output row number.
2. The interleave address generation device according to claim 1, wherein the interleaving address generation is performed. 3. A temporary storage of the bit number of the inverted bit.
Then, the storage cell output to the shift register means is output.
The interleave address generation device according to claim 1 , further comprising a ray . 4. The block interleaving method according to claim 1, wherein
If the lock size is the number of rows N and the number of columns M, 1 in the first row
Go from column to column N, initial value up to column N, row M
Into a matrix with numbers incremented by 0 from 1
On the other hand, different columns for each row from the first row to the Nth row
Perform the exchange and execute the line according to the predetermined random pattern.
From the first row of the first column,
Read the columns from top to bottom until the Mth column and the Nth row
The values obtained sequentially are
Claims that are interleaved
The interleave address generation device according to any one of claims 1 to 3 . 5. The apparatus according to claim 1, wherein said column exchange means comprises a bit-inverted row.
First storage for storing a unique constant value for each row based on a number
Means and second storage means for storing a unique constant value for each column
And the exclusive OR of the stored row number and column number
Exclusive OR operation means for performing an operation, and the exclusive OR operation
And third storage means for storing the calculation result as an address value.
5. The interleave address generation device according to claim 1, further comprising: 6. The interleaving method according to claim 1 , wherein recursive convolution coding means for performing convolutional coding of the information sequence and interleaving processing of the information sequence.
An interleaver having a slave address generator.
A turbo encoding device comprising: 7. The soft-decision output decoding means for decoding a code sequence, and an interleave process for the output of the soft-decision output decoding means according to any one of claims 1 to 5.
An interleaver having a leave address generating device;
The interleaver mixes the order of the input data
A soft decision output decoding means for decoding the code sequence, the i for deinterleaving an output of the soft-decision output decoding means
Deinterleave with interleaved address generator
Turbo decoding apparatus characterized by comprising a bar. 8. The method for decoding a demodulated received signal.
A decoding processing device having the turbo decoding device according to claim 7,
The turbo encoding apparatus according to claim 6, which encodes a transmission signal.
And an encoding processing device having
Communication terminal apparatus that. 9. A method for decoding a demodulated received signal.
A decoding processing device having the turbo decoding device according to claim 7,
The turbo encoding apparatus according to claim 6, which encodes a transmission signal.
And an encoding processing device having
That base station apparatus. 10. An arrangement of data represented by a matrix two-dimensional array.
Second order in block interleaving method
The row number and column number of the original array are counted and output.
And invert the row number and the column number.
The corresponding address value is used as the column conversion value, and the inverted row number is used.
The address offset value by shifting the
The offset value and the column exchange value, and
Is compared to the interleave size
An interleaved address generating method for generating the added value in the address as an address value .