JP3342397B2 - Constant current circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a constant current circuit using a current mirror circuit, and more particularly to a circuit suitable for stabilizing a voltage supplied to a word line in a nonvolatile memory device.

[0002]

2. Description of the Related Art The construction of a constant current circuit using a current mirror circuit has been conventionally performed, and generally has a circuit configuration as shown in FIG. That is, the P-channel MOSFET 51 whose source is connected to the power supply voltage Vcc
A drain and a gate of the PchMOSFET (hereinafter referred to as PchMOSFET) are connected, and a resistor 52 is connected between the drain and the ground. P whose source is connected to the power supply voltage Vcc
The gate of the chMOSFET 53 is a PchMOSFET
Connected to the gate of the first current mirror circuit 5
00 is configured. An N-channel MOSFET (hereinafter referred to as N-channel MOSFET) is provided between the drain of the Pch MOSFET 53 and the ground.
54, and its drain is connected to the gate. In addition, NchMOSFE
An NchMOS whose source is grounded is connected to the gate of T54.
The gate of the FET 55 is connected to form a second current mirror circuit 501.

If the current amplification factors of the Pch MOSFETs 51 and 53 and the Nch MOSFETs 54 and 55 are β1, β2, β3 and β4, respectively, the first current mirror circuit 500 is configured.
The currents IA and IB flowing through the FETs 51 and 53 are IB
= IA · β2 / β1. Further, since the second current mirror circuit 501 is configured, the NchMOS
The currents IB and IE flowing through the FETs 54 and 55 are IE
= IB · β4 / β3. Therefore, the current IE is IE
= IA · β2 · β4 / β1 · β3, and becomes a constant current proportional to the reference current IA.

In the circuit shown in FIG. 5, NchMOSFE
A resistor 56 is connected between the drain of T55 and the power supply voltage Vcc.
E, a reference voltage Vref of a constant voltage is supplied from a connection point between the drain of the Nch MOSFET 55 and the resistor 56.
Is obtained.

[0005]

In the above-described conventional circuit, if the power supply voltage Vcc is always stable at a constant voltage, the reference current IA becomes a constant value.
E is a constant current. Then, the reference voltage Vref
Also has a constant voltage. However, when the power supply voltage Vcc fluctuates, for example, increases, the reference current IA increases, so that the output current IE increases, and the reference voltage Vref also increases. Conversely, when Vcc decreases, the reference current IA decreases, so that the output current I
E decreases, and the reference voltage Vref also decreases. That is, there is a problem that the output current IE fluctuates according to the fluctuation of the power supply voltage, and therefore, the reference voltage Vref also fluctuates.

[0006]

According to the present invention, there is provided a first transistor of one conductivity type having a drain and a gate connected, a first and a second resistor connected in series with the first transistor, and a gate connected to the first transistor. A second transistor of one conductivity type connected to the gate of the first transistor; a third transistor of opposite conductivity type having a drain and a gate connected to the drain of the second transistor; and a gate connected to the gate of the third transistor A fourth transistor of the opposite conductivity type connected;
A fifth transistor of an opposite conductivity type, which is connected in parallel with the third transistor and has a gate connected to a voltage dividing point of the first and second resistors.

In the present invention, the current amplification factors of the second and fifth transistors are set to be substantially the same.

[0008]

FIG. 1 is a circuit diagram showing an embodiment of the present invention. A PchMOSFET 1 having a source connected to a power supply voltage Vcc has a drain and a gate connected, and a resistor between the drain and the ground. A series resistor consisting of a resistor 2 and a resistor 3 is connected. The gate of the PchMOSFET 4 whose source is connected to the power supply voltage Vcc is a PchMOS
The first current mirror circuit 100 is connected to the gate of the FET1. An Nch MOSFET 5 is connected between the drain of the Pch MOSFET 4 and the ground,
Its drain is connected to the gate. Also, Nch
The gate of the MOSFET 5 has an Nc source grounded.
The gate of the hMOSFET 6 is connected to form a second current mirror circuit 101.

Further, the NchMOSFET 5 is connected in parallel with another NchMOSFET 8 by connecting the drain to the drain and grounding the source, and the gate of the NchMOSFET 8 has a voltage dividing point of the resistors 2 and 3. A is connected. Here, the drain of the NchMOSFET 6 and the power supply voltage Vc
The resistor 7 is connected between the reference voltage Vre and the reference voltage Vre of a constant voltage from the connection point between the drain of the NchMOSFET 6 and the resistor 7 using a constant current flowing through the NchMOSFET6.
This is a configuration for obtaining f.

The current gain β2 of the PchMOSFET 4 and the current gain β5 of the NchMOSFET 8 are set to be substantially the same, and such setting is realized by adjusting the transistor size.
Specifically, the current amplification factor β is β = kWW / L (where
k: constant, W: channel width, L: channel length), and the value of k differs between Pch and Nch.
By adjusting W and L of the SFETs 4 and 8, the current gain β can be made the same.

The operation of the present embodiment will be described below with reference to the voltage Vcc-current i characteristic diagram of FIG. First, Pch
Since the first current mirror circuit 100 is configured by the MOSFETs 1 and 4, if the current amplification factors of the MOSFETs 1 and 4 are β1 and β2, respectively,
The currents i0 and i1 flowing through 4 are i1 = i0 · β2 / β1
Becomes Therefore, when the power supply voltage Vcc gradually rises from 0 V and the current i0 increases, the current i1 also gradually increases with the increase as shown in FIG.

On the other hand, the current i1 is
And 8, the flow is expressed as i1 = i2 + i3. As described above, since the divided voltage VA at the voltage dividing point A of the resistors 2 and 3 is applied to the gate of the Nch MOSFET 8, the divided voltage VA increases with the rise of the power supply voltage Vcc and the threshold voltage Vt of the FET. Until the current exceeds i, the current i2 does not flow as shown in FIG. 3, and only the current i3 flows. That is, in this state, the currents i1 and i3 have the same value. However, as the power supply voltage Vcc further increases, when the divided voltage VA exceeds the threshold value Vt of the FET, a current i2 starts to flow, and the current value gradually increases as shown in FIG. For this reason, the rate of increase of the current i3 decreases.

Here, in the present embodiment, PchM
Current amplification factor β2 of OSFET 4 and Nch MOSFET 8
Are set to be substantially the same. Therefore, the rate of increase of the current i with the increase of the power supply voltage Vcc, that is, the slopes of the currents i1 and i2 in FIG. Accordingly, the difference between the current i1 and the current i2 is constant, and the current i3 indicating this difference has a substantially constant value regardless of the rise in the power supply voltage Vcc as shown in FIG.

The current i4 flowing through the Pch MOSFET 6
Since the second current mirror circuit 101 is configured, if the current gains of the Nch MOSFETs 5 and 6 are β3 and β4, i4 = i3 · β4 / β3.
Then, as described above, after the divided voltage VA exceeds the threshold value Vt, the current i3 becomes constant, so that the output current i4 also becomes constant. Then, in this circuit configuration, the reference voltage Vref is also a constant voltage.

As described above, even if the power supply voltage Vcc fluctuates, a constant current can be obtained as the output current i4. Also,
A constant voltage can be obtained as the reference voltage Vref. In the embodiment described above, the first current mirror circuit 100 is configured by a Pch MOSFET, and the second current mirror circuit 101 is configured by an Nch MOSFET. Conversely, the first current mirror circuit is configured by an Nch MOSFET.
SFET, and the second current mirror circuit is Pch
It is also possible to use a MOSFET, and an example of this circuit is shown in FIG.

In FIG. 2, reference numeral 200 denotes an NchMOSFE.
Reference numeral 201 denotes a first current mirror circuit formed by T21 and T24, and reference numeral 201 denotes a second current mirror circuit formed by Pch MOSFETs 25 and 26. And PchMO
When a Pch MOSFET 28 is connected in parallel to the SFET 25 and the divided voltage VA of the resistors 22 and 23 is applied to the gate of the Pch MOSFET 28, a constant current can be obtained as the output current i4 as in FIG. Can also obtain a constant voltage.

Next, an example in which the present invention is applied to a nonvolatile memory device will be described. FIG. 4 is a block diagram showing a schematic configuration of the nonvolatile memory device. Reference numeral 31 denotes a nonvolatile memory cell including a control gate 310, a floating gate 311, a drain 312, and a source 313. The control gate 310, the drain 312, and the source 313 are connected to a word line 32, a bit line 33, and a source line 34, respectively, and the bit line 33 is connected to a sense amplifier (not shown). A high voltage is applied to the source line 34 at the time of writing.

The word line 32 is connected to a reference voltage Vref via a MOSFET 36 as a switching element constituting a row selection circuit 35.
A desired row is selected by applying a row selection signal from the row decoder 37 to the gate of the OSFET 36. In such a configuration, when the reference voltage Vref applied to the word line fluctuates, the voltage supplied to the control gate 310 of the nonvolatile memory cell 31 changes, and a malfunction occurs during writing and reading. However, in the circuit configuration shown in FIGS. 1 and 2, even if the power supply voltage Vcc fluctuates, the output reference voltage Vref does not fluctuate.
When ref is applied to the word line 32, a constant voltage is always supplied to the control gate 310 of the nonvolatile memory cell 31, so that a malfunction does not occur at the time of writing and reading.

[0019]

According to the present invention, it is possible to realize a constant current circuit that reliably outputs a constant current without being affected by fluctuations in the power supply voltage. When this constant current circuit is applied to a non-volatile memory device, malfunctions at the time of writing and reading can be prevented.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention.

FIG. 2 is a circuit diagram showing another embodiment of the present invention.

FIG. 3 is a voltage-current characteristic diagram for explaining the operation of the embodiment.

FIG. 4 is a block diagram illustrating a schematic configuration of a nonvolatile memory device.

FIG. 5 is a circuit diagram showing a configuration of a conventional example.

[Explanation of symbols]

1,4,25,26,28,51,53 PchMOS
FET 5,6,8,21,24,54,55 NchMOSF
ET 2,3,7,22,23,27,52,56 Resistance 100,200,500 First current mirror circuit 101,201,501 Second current mirror circuit 31 Non-volatile memory cell 32 Word line 35 Row selection Circuit 37 Row Decoder

──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G05F 3/26 H03F 3/343

Claims (2)

(57) [Claims] 1. A first transistor of one conductivity type having a drain and a gate connected to each other, first and second resistors connected in series with the first transistor, and a gate connected to a gate of the first transistor. A second transistor of one conductivity type, a third transistor of opposite conductivity type having a drain and a gate connected to the drain of the second transistor, and a second transistor of opposite conductivity type having a gate connected to the gate of the third transistor. 4 transistors and the drain is the second transistor.
A fifth transistor of the opposite conductivity type connected to the drain of the transistor and connected in parallel with the third transistor and having a gate connected to a voltage dividing point of the first and second resistors. Current circuit. 2. The constant current circuit according to claim 1, wherein the current amplification factors of the second and fifth transistors are set to be substantially the same.