JP3342338B2 - Manufacturing method of nonvolatile semiconductor memory device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a nonvolatile semiconductor memory device, and more particularly, to a method for manufacturing a nonvolatile semiconductor memory device having a floating gate and a control gate such as a flash memory.

[0002]

2. Description of the Related Art FIG. 19 is a sectional view showing an example of a conventional nonvolatile semiconductor memory device (flash memory). A source region 96 and a drain region 101 are formed on the surface layer of the semiconductor substrate 91 so as to be separated from each other. A floating gate 93 is formed on the substrate 91 on both sides of the source region 96 via an insulating film 92. The semiconductor substrate 9 between the source region 96 and the drain region 101
1 is provided with a control gate 98 via an insulating film 97.
Is formed. An end of the control gate 98 on the source region 96 side is arranged above the floating gate 93.

The source region 96 and the control gate 98 both extend in one direction (perpendicular to the plane of the drawing), and a plurality of drain regions 1 are provided on both sides of the source region 96.
01 and a plurality of floating gates 93 are arranged along the one direction. Then, the control gate 98 functions as a word line of the semiconductor memory device.

On the semiconductor substrate 91, an interlayer insulating film 123 is formed so as to cover the floating gate 93 and the control gate 98, and a wiring 125 is formed on the interlayer insulating film 123. The wiring 1
25, a contact hole 124 is formed in the interlayer insulating film 123, and the drain region 10 is formed through the contact hole 124.
1 and functions as a bit line of the semiconductor memory device.

[0005]

However, the above-mentioned conventional nonvolatile semiconductor memory device has the following problems. In other words, conventionally, when the mask is misaligned when forming the contact hole 124 in the interlayer insulating film 123, the control gate 98 and the metal wiring 125 may be short-circuited as shown in FIG. In order to avoid such a problem, conventionally, the drain region 1
It is necessary to make the space between the two control gates 98 on both sides of 01 sufficiently large. Thus, high integration of the semiconductor memory device is hindered.

Further, in the conventional nonvolatile semiconductor memory device, the source region 96 extending in one direction is also used as a wiring for connecting between the memory cells. It is formed by diffusion and has a relatively large resistance value. For this reason, the voltage drop in the source region 96 is large, and if the width of the source region 96 is narrowed in response to recent high integration, the operation margin is reduced due to the voltage drop in the source region 96.

[0007]

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned drawbacks, and as shown in FIG. 1, a floating gate 3 formed on a semiconductor substrate 1 and a control gate 8 formed on a control gate 8. By forming the first conductive cover film 17 a, even if the mask is misaligned when the contact hole 34 is formed in the interlayer insulating film 33 to connect the metal wiring 35 and the drain region 11, A short circuit between the wiring 35 and the control gate 8 is reliably prevented.

Further, the resistance of the source region is reduced by connecting the source region 6 and the second conductive cover film 17b through contact holes 32 formed at predetermined intervals in the insulating films 2, 12a. I do. In the manufacturing method according to the embodiment of the present invention, the floating gate 3 is formed on the semiconductor substrate 1 with the gate insulating film 2 interposed therebetween, and the insulating film 7 covering the periphery of the floating gate 3 is formed. next,
A conductive film 8a and an insulating film 9 are formed on the entire surface, and the insulating film 9 and the conductive film 8a are patterned to form a control gate 8 on which the insulating film 9 is laminated. Subsequently, an impurity is introduced into the surface layer of the substrate at one end of the floating gate 3 and the control gate 8 to form a source region 6 and a drain region 11, and an insulating film 12a is formed on the entire surface. The insulating film 12a is etched through the photoresist film formed in step (1) to expose the drain region 11 and the sidewall insulating film 12 is formed on the sidewall of the control gate 8. Next, after forming the first and second conductive cover films 17a and 17b on at least the insulating film 9 or the insulating film 12a from the source / drain regions 6 and 11, an interlayer insulating film 33 is formed on the entire surface. Forming a metal wiring 35 electrically connected to the conductive cover film 17a through a contact hole 34 reaching the first conductive cover film 17a from the surface of the interlayer insulating film 33. is there.

In a manufacturing method according to another embodiment of the present invention, a floating gate 53 is formed by laminating an insulating film 54 of a predetermined thickness on a semiconductor substrate 51 with a gate insulating film 52 interposed therebetween.
To form Next, an insulating film 57 covering the periphery of the insulating film 54 and the floating gate 53 is formed, a conductive film 58a and an insulating film 59 are formed on the entire surface, and then patterned via a photoresist film 60 to form the insulating film 59.
Are formed to form a control gate 58. Subsequently, source / drain regions 56 and 61 are formed so as to be adjacent to one end of the floating gate 53 or the control gate 58, and an insulating film 62a is formed on the entire surface. The insulating films 57 and 62a on the gates 56 and 61 are removed, and a side wall insulating film 62 covering at least side walls of the floating gate 53 and the control gate 58 is formed. Next, after a conductive film 65 is formed on the entire surface, patterning is performed via a photoresist film to form first and second layers on at least the insulating film 57, the insulating film 59, and the sidewall insulating film 62 from above the source / drain regions 56, 61. The second conductive cover films 67a and 67b are formed. Then, after forming an interlayer insulating film 83 on the entire surface, a contact hole 84 is formed in the interlayer insulating film 83 so as to make contact with the first conductive cover film 67a. This is to form a metal wiring 85 that contacts the cover film 67a.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a nonvolatile semiconductor memory device according to an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a cross-sectional view showing a nonvolatile semiconductor memory device (flash memory) according to one embodiment of the present invention.
FIG. 2 is a top view of the same. In FIG. 2, the illustration of the interlayer insulating film 33 and the metal wiring 35 is omitted.

The surface of the semiconductor substrate 1 has one direction (hereinafter referred to as Y
A plurality of source regions 6 extending in the same direction are formed parallel to each other. On the surface layer of the substrate 1 on both sides of each source region 6, a plurality of drain regions 11 are formed along the source region 6.
Are arranged. Source region 6 and each drain region 11
The floating gate 3 and the control gate 8 are formed above the semiconductor substrate 1 with the gate insulating film 2 and the insulating film 7 interposed therebetween. The control gate 8
Floating gate 3 from above floating gate 3
Extends to the side.

A memory cell is constituted by a source region 6, a drain region 11, a floating gate 3 and a control gate 8 arranged in a direction perpendicular to the one direction (hereinafter, referred to as an X direction). In this case, two memory cells are formed with the source region 6 interposed therebetween.
Is a part forming one memory cell and also a part forming the other memory cell. A field oxide film 31 is formed between the memory cells arranged in the Y direction, as shown in FIG. Further, as shown in FIG. 2, the control gate 8 also extends in the Y direction.
That is, the control gates 8 of the plurality of memory cells are formed continuously. The control gate 8 functions as a word line of the nonvolatile semiconductor memory device.

As shown in FIG. 1, the periphery of the floating gate 3 is covered with an insulating film 7 and the like, and the periphery of the control gate 8 is covered with an insulating film 9, an insulating film 12a, a side wall insulating film 12, and the like. . Also, each drain region 11
A first conductive cover film 17a is formed thereon,
The conductive cover film 17a extends to above the insulating film 9 on the control gate 8. The source region 6 is located above the source region 6 via the insulating films 7 and 12a.
Is formed along the second conductive cover film 17b. The conductive cover film 17b is formed of the floating gate 3
Alternatively, it extends to above the control gate 8.

Further, the conductive cover film (17b) is
As shown in FIG. 2, at regular intervals (for example, every 16 memory cells) along the Y direction, it is electrically connected to the source region 6 via the contact holes 32 provided in the insulating films 7, 12a. ing. Thereby, the resistance value in the source region 6 is reduced, so that the problem that the operation margin caused by the voltage drop in the source region 46 is reduced conventionally is alleviated.

The floating gate 3, the control gate 8, the first conductive cover film 17a and the second
The conductive cover film 17b is covered with an interlayer insulating film 33. On the interlayer insulating film 33, a metal wiring 35 is formed in a predetermined pattern. The metal wiring 35 has a contact hole 34 selectively formed in the interlayer insulating film 33 and a first
Is electrically connected to the drain region 11 through the conductive cover film 17a. The metal wiring 35 functions as a bit line of the nonvolatile semiconductor memory device.

3 to 10 are sectional views showing a method of manufacturing the above-mentioned nonvolatile semiconductor memory device in the order of steps. First,
As shown in FIG. 3, a field oxide film 31 is formed in a predetermined region of the semiconductor substrate 1 (see FIG. 2), and a gate insulating film 2 is formed on a surface layer other than the field oxide film 31 to a thickness of about 100 °. I do. Then, a polysilicon film is formed on the insulating film 2 to a thickness of about 1500 °, is doped with phosphorus, and is made conductive. Then, the polysilicon film is patterned by a known photolithography method to form a floating gate 3.

Next, as shown in FIG. 4, the surface of the substrate 1 is oxidized to form an insulating film 7 having a thickness of about 300 ° so as to cover the floating gate 3. Subsequently, for example, a polysilicon film and WS
Then, a conductive film 8a having a two-layer structure including the ix film is formed.
The conductive layer 8a is formed by first forming a polysilicon film to a thickness of about 1000.degree. And then doping the polysilicon film with phosphorus using POCl3 as a diffusion source, and then forming a WSix film (tungsten silicide film) on the polysilicon film. ) To a thickness of approximately 1200 °. Then, after an insulating film 9 having a thickness of about 2500 ° is formed on the conductive film 8a, a photoresist film 10 is formed on the insulating film 9, and a portion of the photoresist film 10 where a source / drain region is to be formed is formed. Opening 10 in corresponding position
a is formed.

Next, as shown in FIG. 5, the insulating film 9 and the conductive film 8a are etched using the resist film 10 as a mask to form a control gate 8 formed by laminating the insulating film 9. And the resist film 1
After removing 0, at least the portion where the drain region is to be formed is covered with a photoresist film (not shown). Using the photoresist film as a mask, for example, phosphorus (31P +) ions are applied to the surface layer of the substrate 1 at an acceleration voltage of about 60 KeV. The source region 6 is formed by implanting at a dose of 5 × 10 ¹⁵ / cm 2. Subsequently, after the photoresist film is removed, at least the source region 6 is covered with a photoresist film (not shown), and the photoresist film is used as a mask to form, for example, phosphorus (31P +) ions on the surface layer of the substrate 1. Is implanted under conditions of approximately an acceleration voltage of 40 KeV and an implantation amount of 1 × 10 ¹³ / cm 2 to form a drain region 11 and remove the photoresist film. At this time, the field oxide film 3
1, floating gate 3 and control gate 8
Is used as a mask, so that the source region 6 and the drain region 11 are formed in a self-alignment manner on the surface layer of the substrate 1 so as to be adjacent to one ends of the floating gate 3 and the control gate 8.

Next, as shown in FIG. 6, an insulating film 12a made of, for example, a CVD SiO2 film having a thickness of about 2000 .ANG. Is formed on the entire surface of the substrate 1, and then, as shown in FIG. Is formed. These openings 13a are provided with contact holes 32, 3
4 are formed at positions where they should be formed (see FIGS. 1 and 2).

Then, the insulating film 12a and the insulating film 7 exposed at the bottom of the opening 13 are removed by etching.
As shown in FIG. 7, an upper surface of the drain region 11 is exposed and a sidewall insulating film 12 is formed. After that, the resist film 13 is removed. Next, a conductive film 15 is formed on the entire surface of the substrate 1 as shown in FIG. The conductive film 15 has a two-layer structure including, for example, a polysilicon film and a WSix film,
First, a polysilicon film is formed to a thickness of about 500 °, and then arsenic (75 As +) ions are applied to the polysilicon film at an acceleration voltage of about 100 KeV and an implantation amount of 5 × 10 ¹⁵ /
After implantation under the condition of cm 2, WSi
It is obtained by forming the x film to a thickness of about 1200 °. The material of the conductive film 15 is the above-mentioned polysilicon film and WS.
Although it is not limited to the two-layer structure with the ix film, it is preferable that the resistance value is small and the contact resistance with the impurity diffusion layer (source region or drain region) is small.

Next, as shown in FIG. 9, a photoresist film 16 having an opening 16a is formed on the conductive film 15,
By etching the portion of the conductive film 15 that is not covered with the photoresist film 16, the drain region 1 is removed.
1 and a second conductive cover film 17b that contacts the source region 6 through the contact holes 32 formed in the insulating films 7 and 12a (FIG. 2). reference).

Next, as shown in FIG. 10, an interlayer insulating layer 33 made of, for example, an NSG film and a BPSG film is formed on the entire surface of the substrate 1 and heat-treated, and a photoresist having an opening 22a thereon is formed thereon. A film 22 is formed, a contact hole 34 is formed in the interlayer insulating film 33 above the first conductive cover film 17a, and aluminum is deposited on the entire surface of the substrate 1 as shown in FIG. An aluminum film connected to the first conductive cover film 17a through the hole 34 is formed. Then, the metal film 35 is formed by patterning the aluminum film. Thereby, the nonvolatile semiconductor memory device of the present embodiment is completed.

In the present embodiment, as shown in FIG. 1, a first conductive cover film 17a is formed in a region between the drain region 11 and the control gate 8.
Even if the mask is misaligned when the contact hole 34 is formed in the interlayer insulating layer 33, the insulating film 9 covering the control gate 8 is not damaged, and a short circuit between the metal wiring 35 and the control gate 8 is prevented. It can be reliably prevented.

Further, in the present embodiment, a second conductive cover film 17b is formed along the source region 6, and the conductive cover film 17b and the source region 6 are formed as shown in FIG.
Are electrically connected at regular intervals via the contact holes 32 provided in the insulating films 7 and 12a, whereby the resistance value of the source region 6 can be reduced. Thus, even if the element is miniaturized, a voltage drop in the source region 6 can be suppressed, and higher integration can be achieved.

Further, in the method of the present invention, since the first and second cover films 17a and 17b are formed simultaneously, the increase in the number of steps can be suppressed, and the above-mentioned nonvolatile semiconductor memory device can be easily formed. it can. Hereinafter, another embodiment of the present invention will be described. First, as shown in FIG. 11, a gate insulating film 52 is formed on a semiconductor substrate 51 by about 100 °.
And a polysilicon film 53 on the insulating film 52.
a is formed to a thickness of about 1500 °, and is doped with phosphorus to make it conductive. Thereafter, an insulating film 54a is formed on the polysilicon film 53a, the insulating film 54a and the polysilicon film 53a are patterned by photolithography, and a floating gate is formed by laminating the insulating film 54 as shown in FIG. 53 is formed.

Next, as shown in FIG. 13, the surface of the substrate 51 is oxidized to form an insulating film 57 having a thickness of about 300 °.
To form Subsequently, a conductive film 58 having a two-layer structure composed of, for example, a polysilicon film and a WSix film is formed on the entire surface of the substrate 51.
a is formed. The conductive film 58a is formed by first forming a polysilicon film to a thickness of about 1000.degree. And then doping the polysilicon film with phosphorus using POCl3 as a diffusion source, and then forming a WSix film (tungsten silicide film) on the polysilicon film. ) To a thickness of approximately 1200 °. Then, after forming an insulating film 59 of, for example, a CVD SiO2 film having a thickness of about 2500 DEG on the conductive film 58a, a photoresist film 60 is formed on the insulating film 59, and the source / drain of the photoresist film 60 is formed. A hole 60 is formed at a position corresponding to the area to be formed.
a is formed.

Next, as shown in FIG. 14, the insulating film 59 and the conductive film 58a are etched using the resist film 60 as a mask to form a control gate 58 formed by laminating the insulating films 59. Then, after removing the resist film 60, at least a portion where a drain region is to be formed is covered with a photoresist film (not shown), and, for example, phosphorus (31P +) ions are The source region 5 is implanted under conditions of approximately an acceleration voltage of 60 KeV and an implantation amount of 5 × 10 ¹⁵ / cm 2.
6 is formed. Subsequently, after the photoresist film is removed, at least the source region 56 is covered with a photoresist film (not shown), and the photoresist film is used as a mask to form, for example, phosphorus (31P +) ion on the surface layer of the substrate 51. With an acceleration voltage of 40 KeV and an injection amount of 1 × 10 ¹³ /
implanted under the condition of cm 2 to form a drain region 61,
The photoresist film is removed.

Next, as shown in FIG. 15, after an insulating film 62a having a thickness of about 2000.degree.
This is etched back to expose the source region 56 and the train region 61 as shown in FIG. 16, and to form a sidewall insulating film 62 on the sidewalls of the floating gate 53 and the control gate 58. Thereafter, a conductive film 65 is formed on the entire surface of the substrate 51 as shown in FIG. The conductive film 65 has a two-layer structure composed of, for example, a polysilicon film and a WSix film. First, a polysilicon layer is formed to a thickness of about 500 °, and then arsenic (75 As) is formed on the polysilicon film. +) After ions are implanted under the conditions of an acceleration voltage of 100 KeV and an implantation amount of 5 × 10 ¹⁵ / cm 2, a WSix film is
It is obtained by forming it to a thickness of 0 °.

Hereinafter, the nonvolatile semiconductor memory device according to the other embodiment is manufactured in the same manner as the above-described nonvolatile semiconductor memory device manufacturing process. That is, a first and second conductive cover films are formed by forming a photoresist film having an opening on the conductive film 65 and etching a portion of the conductive film 65 not covered by the photoresist film. 67
a, 67b are formed, subsequently, an interlayer insulating film 83 is formed, and a metal wiring 85 connected to the first conductive cover film 67a through a contact hole 84 formed in the interlayer insulating film 83 is formed. .

Another embodiment of the present invention described above is:
The manufacturing process is simplified compared to the nonvolatile semiconductor memory device of the above-described embodiment. That is, in the nonvolatile semiconductor memory device of one embodiment, when the insulating film 12a is etched to expose the drain region 11, the corner of the floating gate 3 and the second conductive cover film 1 are removed.
In order to prevent short circuit due to contact with 7b, after forming an insulating film 12a on the entire surface as shown in FIG.
A step of forming the photoresist film 13 shown in FIG. 7 on at least the region including the source region 6 and removing only the insulating film 12a on the drain region 11 is required, which complicates the process. In the embodiment described above, by stacking an insulating film 54 having a predetermined thickness on the floating gate 53, a sufficient space can be obtained in which there is no possibility that the corners of the floating gate come into contact with the conductive cover film. As shown in FIG. 15, the entire surface can be etched after the insulating film 62a is formed on the entire surface, and the mask alignment step can be reduced by one step.

In the non-volatile semiconductor memory device of one embodiment, the source region 6 is also used as a wiring connecting each memory cell. The source region 6 is formed by diffusing impurities into the semiconductor substrate 1. For the purpose of preventing a relatively high resistance value, a large voltage drop in the source region 6 and a decrease in an operation margin due to the resistance value, a predetermined interval (for example, 16 memories) is used. In order to connect the second conductive cover film 17b and the source region 6 (for each cell), a contact hole 32 is formed in a region where the floating gate 3 is not formed, and a second hole is formed through the contact hole 32. Although the conductive cover film 17b is connected to the source region 6, the formation region of the contact hole 32 is limited to a portion where the floating gate 3 is not provided. It was not possible to reduce the resistance of the Surain.

However, in the non-volatile semiconductor storage device of another embodiment, as shown in FIG. 17, the second conductive cover film 67b is formed on the upper surface of the source region 56 without interposing a contact hole. Therefore, the source line resistance can be sufficiently reduced as compared with the nonvolatile semiconductor memory device of one embodiment.

[0033]

As described above, according to the nonvolatile semiconductor memory device of the present invention, the floating gate and the control gate are formed above the semiconductor substrate, and the first and second impurity diffusion regions are formed on the surface of the substrate. After forming
By forming a conductive cover film from above the first and second impurity diffusion regions to above the floating gate or the control gate, it is possible to make contact with an interlayer insulating film such as a conventional nonvolatile semiconductor memory device. When the holes are formed, when the mask is misaligned, the possibility that the control gate and the metal wiring are short-circuited is eliminated.

According to the non-volatile semiconductor storage device of one embodiment, the second conductive cover film is formed above the semiconductor substrate along the source region, and the source region and the second conductive cover film are formed. Since the conductive cover film is electrically connected through the plurality of contact holes, the resistance value of the source region can be reduced. As a result, a voltage drop in the source region can be suppressed, a decrease in operation margin can be avoided, and higher integration can be achieved.

Further, according to the nonvolatile semiconductor memory device of another embodiment, the second conductive cover film 67b is formed on the upper surface of the source region without interposing a contact hole. The resistance of the source line can be further reduced as compared with the nonvolatile semiconductor memory device of the embodiment. According to the method for manufacturing a nonvolatile semiconductor memory device of another embodiment, an insulating film having a predetermined thickness is laminated on the floating gate, so that the corner of the floating gate and the conductive cover film can be formed. Since a sufficient space without contact with the semiconductor device can be obtained, the entire surface can be etched after forming the insulating film on the entire surface, and the mask alignment can be performed as compared with the manufacturing process of the nonvolatile semiconductor memory device according to the embodiment. One process can be reduced.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a nonvolatile semiconductor memory device according to an embodiment of the present invention.

FIG. 2 is a top view showing a nonvolatile semiconductor memory device according to one embodiment of the present invention.

FIG. 3 is a first sectional view illustrating the method for manufacturing the nonvolatile semiconductor memory device according to the embodiment of the present invention.

FIG. 4 is a second sectional view illustrating the method for manufacturing the nonvolatile semiconductor memory device according to the embodiment of the present invention.

FIG. 5 is a third sectional view illustrating the method for manufacturing the nonvolatile semiconductor memory device according to the embodiment of the present invention.

FIG. 6 is a fourth sectional view illustrating the method for manufacturing the nonvolatile semiconductor memory device according to the embodiment of the present invention.

FIG. 7 is a fifth sectional view illustrating the method for manufacturing the nonvolatile semiconductor memory device according to one embodiment of the present invention.

FIG. 8 is a sixth sectional view illustrating the method for manufacturing the nonvolatile semiconductor memory device according to one embodiment of the present invention.

FIG. 9 is a seventh sectional view illustrating the method for manufacturing the nonvolatile semiconductor memory device according to one embodiment of the present invention.

FIG. 10 is an eighth sectional view showing the method for manufacturing the nonvolatile semiconductor memory device according to one embodiment of the present invention.

FIG. 11 is a first cross-sectional view showing a method for manufacturing a nonvolatile semiconductor memory device according to another embodiment of the present invention.

FIG. 12 is a second sectional view illustrating the method for manufacturing the nonvolatile semiconductor memory device according to another embodiment of the present invention.

FIG. 13 is a third sectional view illustrating the method for manufacturing the nonvolatile semiconductor memory device according to another embodiment of the present invention.

FIG. 14 is a fourth sectional view illustrating the method for manufacturing the nonvolatile semiconductor memory device according to another embodiment of the present invention.

FIG. 15 is a fifth sectional view showing the method for manufacturing the nonvolatile semiconductor memory device according to another embodiment of the present invention.

FIG. 16 is a sixth sectional view illustrating the method for manufacturing the nonvolatile semiconductor memory device according to another embodiment of the present invention.

FIG. 17 is a seventh cross-sectional view showing the method for manufacturing the nonvolatile semiconductor memory device according to another embodiment of the present invention.

FIG. 18 is an eighth sectional view showing the method for manufacturing the nonvolatile semiconductor memory device according to another embodiment of the present invention.

FIG. 19 is a sectional view showing an example of a conventional nonvolatile semiconductor memory device.

FIG. 20 is a cross-sectional view showing a problem of a conventional nonvolatile semiconductor memory device.

──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Shoichi Kobayashi 2-5-5 Keihanhondori, Moriguchi-shi, Osaka Sanyo Electric Co., Ltd. (72) Katsuhiko Iizuka 2-5-2 Keihanhondori, Moriguchi-shi, Osaka No. 5 Inside Sanyo Electric Co., Ltd. (56) References JP-A-7-273225 (JP, A) JP-A-6-216393 (JP, A) JP-A 8-139193 (JP, A) (58) Field (Int.Cl. ⁷ , DB name) H01L 21/8247 H01L 27/115 H01L 29/788 H01L 29/792

Claims (2)

(57) [Claims] A first conductive film and a second insulating film are formed on a semiconductor substrate with a first insulating film interposed therebetween, and a second conductive film having a predetermined thickness is formed.
Forming a floating gate formed by laminating the above insulating films; forming a third insulating film covering the periphery of the insulating film and the floating gate; and forming the third insulating film through the second and third insulating films. Forming a control gate formed by laminating a fourth insulating film having a predetermined thickness from the upper part to the side part of the floating gate; and forming a first and second control gates adjacent to one end of the floating gate or the control gate. Forming a second impurity diffusion region; forming a fifth insulating film on the entire surface; and etching back the entire surface to form a third and a fifth impurity diffusion region on the first and second impurity diffusion regions.
Removing the insulating film and forming a side wall insulating film covering at least the side wall of the floating gate and the control gate; and forming a third conductive film over the entire surface and then patterning via a photoresist film. Forming first and second conductive cover films on at least the second insulating film, the third insulating film, and the sidewall insulating film from above the first and second impurity diffusion regions; Forming an interlayer insulating film on the second conductive cover film, the floating gate, and the control gate; and forming a contact hole in the interlayer insulating film for contacting the first conductive cover film. Forming a metal wiring contacting the conductive cover film via a contact hole. Method of manufacturing location. 2. The method according to claim 1, wherein the conductive cover film has a two-layer structure including a polysilicon film and a silicide film.